JPH0731301B2 - Automatic focus detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention provides two A / D converters for converting analog data indicating a defocus amount into digital data, one for 1 bit and one for multiple bits. The present invention relates to an automatic focus detection device which is used properly and has a shorter processing time than that which uses a conventional 8-bit A / D converter.

(Prior Art) Conventionally, an image sensor that outputs an analog signal corresponding to an image of a subject that has passed through a lens and an A / D conversion unit that converts the analog signal from the image sensor into an 8-bit digital signal are provided. , An automatic focus detection device for performing focus detection by calculating a defocus amount from the 8-bit digital signal has been proposed and filed by our company.
In this conventional example, the defocus amount is exclusively calculated using only the 8-bit digital signal, and the defocus amount is not calculated using the 1-bit digital signal (binarized signal).

On the other hand, as an automatic focus detection device for performing focus detection by a 1-bit digital signal, there is one disclosed in Japanese Patent Laid-Open No. 59-165012. This device converts an analog distance signal into a 1-bit digital signal and processes it.
First, the analog distance signal is read out by thinning out. For example, a CCD for each pixel out of a pixels
Data is read, A / D converted, calculated to obtain the defocus amount, the lens is driven by this defocus amount, and after driving is completed, 1 / 2a continuous analog distance signals are read. , And calculates the defocus amount. This conventional example is intended to cover a change in the size of a subject in a field when a zoom lens is used.

Further, Japanese Patent Application Laid-Open No. 59-107312 discloses a focus detection device having means for selecting which of the first digital signal and the second digital signal is used for calculation for focus detection. Has been done.

(Problems to be Solved by the Invention) In the above-described first conventional technique, even if the 8-bit signal processing is not required or the 8-bit signal processing is not preferable, the 8-bit signal is always processed. Since the processing is performed, there is a problem that the focus detection speed is limited.

In addition, although the second prior art discloses a 1-bit signal processing, it is not a technology for speeding up focus detection and cannot solve the problem of the first prior art. .

Next, in the third conventional technique, the focus is first detected and the lens is driven, and then which signal is to be used is switched according to the situation. Therefore, the situation is judged while driving the lens. Therefore, the focus detection speed becomes slower. Further, since the accuracy of the data used for focus detection is changed during lens driving, the lens driving direction may be reversed and the lens may go back and forth, the movement of the lens is not smooth, and the feeling of focus detection is not smooth. There was a problem that it was not so good.

The present invention has been made in view of the above points,
It is an object of the present invention to improve the conventional automatic focus detection device and to provide an automatic focus detection device capable of performing focus detection in a shorter time and with the same accuracy and feel as the conventional device.

(Means for Solving Problems) In the automatic focus detection device according to the present invention, in order to solve the above problems, as shown in FIG. Image sensor that outputs an analog signal corresponding to the luminance distribution of the image sensor, a first A / D conversion unit that converts the analog signal from the image sensor into a digital signal having a first bit number, and a first A / D A first calculating means for calculating a digital signal from the converting means to obtain a defocus amount for a subject and an analog signal from the image sensor are converted into a digital signal having a second bit number larger than the first bit number. A second A / D conversion means for A / D conversion, a second calculation means for calculating a digital signal from the second A / D conversion means, and obtaining a defocus amount for the object, and the first bit number. Digital signal And a second bit number digital signal to be used, which is automatically selected before the lens is driven in accordance with the subject condition or the photographing condition.

(Operation) In the present invention, as described above, the analog signal from the image sensor is converted into the digital signal of the first bit number by the first or second A / D converter, or the first signal. It is converted into a digital signal having a second bit number larger than the bit number, and the defocus amount is obtained from the digital signal by the first or second arithmetic means. The digital signal of the first bit number and the digital signal of the second bit number are
When the focus detection is performed by the selection means and the focus detection by the digital signal of the second bit number is not necessary, the focus detection by the digital signal of the first bit number can be performed, and the number of bits decreases. , The focus detection speed becomes faster. In addition, the digital signal of the first bit number and the second signal
The signal to be used is selected before the lens is driven in accordance with the subject condition or the shooting condition, so that it is compared with the case where the number of bits is switched after the lens is driven. Since it is not necessary to determine the shooting condition while driving the lens, the focus detection speed is increased. Furthermore, if the accuracy of the data used for focus detection changes during lens driving, the lens driving direction may be reversed and the lens may move back and forth, the movement of the lens is not smooth, and the feeling of focus detection is not very good. However, as in the present invention, if the number of bits is selected before driving the lens, the accuracy of the data used for focus detection does not change during lens driving, so the movement of the lens becomes smooth. The feeling of focus detection is good.

(Example) Hereinafter, a preferred example of the present invention will be described with reference to the accompanying drawings. A circuit configuration diagram of the entire camera used in the embodiment of the present invention is shown in FIG. 2 and described. (E) is a battery that is the power source for the entire circuit of the camera, and (S1) is a shooting preparation start switch that is turned on by the first stroke of the release button (not shown).
In 5), an “L” level signal is output, the power supply transistor (Tr ₁ ) is turned on, and power is supplied to each circuit. (S
2) is a release switch which is turned on by the second stroke of the release button, and when the switch is turned on, the exposure operation is started. (S3) is a one-frame winding switch which is turned on when the exposure is completed and is turned off when the one frame is completed. The release mechanism is charged when winding up one frame, and the charging of the release mechanism is already completed when the winding up of one frame is completed. (S4)
Indicates continuous shooting when the single frame / continuous switching switch for switching between single frame shooting and continuous shooting is turned on.

(1) is an exposure calculation control circuit, a signal corresponding to the open aperture value of the lens sent from the microcomputer described later, and a signal corresponding to the brightness of the subject sent from the photometric circuit (3), The control aperture value and the shutter speed are calculated from the signal according to the film sensitivity sent from the film sensitivity setting circuit (4) and the signal according to the set shooting mode sent from the shooting mode setting circuit (5). Then, by inputting a release signal, exposure control is performed based on the calculated control aperture value and shutter speed. (2) is a control circuit for controlling a motor (M1) for winding one frame of film in response to a signal from the exposure calculation control circuit (1). Reference numeral (6) is a release signal forming circuit for sending a release signal to a microcomputer (8) described later in accordance with the single frame shooting mode and the continuous shooting mode. (7) is a lens circuit provided in the interchangeable lens, and is composed of a ROM that stores information corresponding to each lens and a control circuit necessary to read the contents from the ROM. (8) is a microcomputer (hereinafter, referred to as a microcomputer) that performs automatic focus detection and control. The microcomputer (8) sends a control signal to an interface circuit (1) to input subject information necessary for focus detection.
0), by which the subject information obtained from the photoelectric conversion circuit (12) consisting of a CCD sensor via the interface circuit (10) is calculated to perform focus detection.
Based on the result, the lens control circuit (13) that controls the display circuit (9) and the motor (M2) that drives the lens
To control. Reference numeral (11) is a booster circuit that boosts the battery voltage up to a voltage required to drive the photoelectric conversion circuit (12). (25) enables focus detection even at low brightness.
It is an auxiliary light circuit that emits light toward a subject.

Before describing the operation of the circuit configured as described above, the optical system and the photoelectric conversion unit used in the examples will be described with reference to FIGS. 3 to 5.

In FIG. 3, (TL) is a taking lens, (F) is a film equivalent surface, (CL) is a condenser lens, (L ₁ ),
(L ₂ ) is an imaging lens, (M) is a diaphragm that limits the light incident on the imaging lens, and (I ₁ ) and (I ₂ ) are charge storage type image sensors, which are equivalent to the film equivalent surface (F). The image in the range of A and B is converted into a condenser lens (CL), an imaging lens (L ₁ ),
(L ₂₎ image sensor by (I _1), each image on the _{(I 2) (A 1)} , (B 1) and (A _2), and re-formed as (B _2). The image sensors (I ₁ ) and (I ₂ ) send two image signals corresponding to the intensity distributions of the two images formed thereon to the focus detection circuit, and the focus detection circuit has the respective image signals. By having the correlation, the amount of image shift and the focus state are determined.

Figure 4 is above the image sensor (I _1), shows a photoelectric conversion unit comprising (I _2), the photoelectric conversion unit, P _1, P
₂ , ... P (n- ₁ ), Pn photo sensor array (PA), integral clear circuit (ICG) for initializing this photo sensor array (PA), photo sensor array (P
A) A shift gate circuit (SG) that transfers the accumulated charge accumulated in A) to a CCD shift register (SR) described later, R ₁ , R ₂ , ...
-A CCD shift register (SR) consisting of R (n + ₂ ) and R (n + ₃ ) is provided. Here, the accumulated charge sent from the photo sensor array (PA) is transferred to a transfer pulse (φ
₁ ), (φ ₂ ) in synchronization with the video signal output circuit (V
The number of cells in the CCD shift register (SR), which is the transfer unit for transferring to (s), is three more than the number of photosensor arrays (PA) photosensors. CCD shift register (SR) cells R ₁ , R ₂ , R
₃ is for idle feed, and the accumulated charge of each photo sensor P ₁ , P ₂ , ..., P (n- ₁ ), Pn of the photo sensor array (PA) is CCD by the shift pulse (SH) described later. Shift register (SR) cells R ₄ , R ₅ , ..., R (n + ₂ ), R (n
+ ₃ ) in parallel. As shown in Fig. 5, each photosensor has a photodiode (D ₁ ), a charge storage diode (D ₂ ) utilizing the junction capacitance of the PN junction, a cathode of the photodiode (D ₁ ) and a charge storage diode (D _2). ) Is connected to the cathode and the gate is grounded, the FET circuit (Q ₁₀ ), the cathode of the charge storage diode (D ₂ ) and the switch (S) connected in series to the power supply + V. . This switch (S) is an integration clear circuit (IC
G) is equivalent to the semiconductor switching element,
When this switch is closed (integral clear signal (ICGS) is sent and the semiconductor switching element is turned on), the cathode side level of the charge storage diode (D ₂ ) is raised to the level of the power source + V. That is, the photo sensor is set to the initial state. When the switch (S) is opened (the semiconductor switching element is turned off after the integration clear signal (ICGS) disappears), the photocurrent of the photodiode (D ₁ ) is used for charge storage via the FET circuit (Q ₁₀ ). The charge of the diode (D ₂ ) is discharged, and the cathode voltage of the charge storage diode (D ₂ ) drops with the passage of time. That is,
Photocurrent integration is performed. It may be considered that negative charges are accumulated in the cathode of the charge storage diode (D ₂ ) at a speed according to the intensity of light incident on the photodiode (D ₁ ). Therefore, it is considered that each photosensor accumulates electrification at a speed corresponding to the incident light intensity. The accumulation of charges in the photo sensor starts after the integration clear signal (ICGS) disappears and ends when a shift pulse is input to the shift gate circuit (SG). That is, the charge accumulated in the photo sensor is transferred to the CCD shift register (SR) by the input of the shift pulse. In the CCD shift register (SR), the transferred accumulated charges are sequentially output to the video signal output circuit (Vs) one cell at a time by the transfer pulses (φ ₁ ) and (φ ₂ ).

(T ₈ ) and (T ₉ ) in FIG. 4 are photosensor arrays (PA),
It is a power supply terminal and a ground terminal for supplying the power supply + V to the brightness monitor circuit (MC), the reference signal generation circuit (RS), and the video signal output circuit (Vs). (MP) is a light receiving element for brightness monitor, which is located near the photo sensor array (PA), and includes the brightness monitor circuit (MC), reference signal generation circuit (RS), and video signal output circuit (Vs). , And these also constitute the photoelectric conversion unit. The brightness monitor circuit (MC)
FET circuit (Q ₁ ), (Q ₂ ), (Q ₃ ) and capacitor (C ₁ )
The gate of the FET circuit (Q ₁ ) is connected to the integration clear circuit (ICG), and is made conductive by the integration clear signal (ICGS), and the gate of the FET path (Q ₂ ) and the capacitor (C ₁ ) are connected. Raise the connection point (J ₁ ) to the power supply + V. The brightness monitor light receiving element (MP) operates in the same manner as described for the photo sensor. That is, after the integration clear signal (ICGS) disappears, the brightness monitor light receiving element (MP) accumulates negative charges in the capacitor (C ₁ ) at a speed according to the intensity of incident light. The FET circuits (Q ₂ ) and (Q ₃ ) form a buffer, and from the terminal (T ₁ ) drawn from the connection point of the FET circuits (Q ₂ ) and (Q ₃ ) to the connection point (J ₁ The voltage (AGCOS) equal to the voltage of () is output.

FIG. 10 shows the temporal change of the output voltage (AGCOS), and (l1) to (l7) show that the speed of the voltage effect changes depending on the brightness.

Returning to FIG. 4, the reference voltage generation circuit (RS) is composed of FET circuits (Q ₄ ), (Q ₅ ), (Q ₆ ), and a capacitor (C ₂ ), and a connection point (J ₂ ). Is exactly the same as the brightness monitor circuit (MC) except that it is connected only to the gate and capacitor (C ₂ ) of the FET circuit (Q ₄ ) and the FET circuit (Q ₅ ). The characteristics of each are also the same. Therefore, the integration clear signal (ICGS)
The reference voltage (DOS) of the terminal (T ₂ ) and the voltage (AGCOS) of the (T ₁ ) terminal of the brightness monitor circuit (MC) immediately after disappearance of
Almost the same. Therefore, it can be used as a reference voltage for measuring the amount of voltage that drops over time.

The video signal output circuit (Vs) is composed of FET circuits (Q ₇ ), (Q ₈ ),
(Q ₉ ) and capacitor (C ₃ ), the connection point (J ₃ ) is a CCD shift register in addition to the gate and capacitor (C ₃ ) of the FET circuit (Q ₇ ) and FET circuit (Q ₈ ). (S
R) output. The gate of the FET circuit (Q ₇ ) is connected to the (T ₄ ) terminal of the transfer pulse (φ ₁ ), and every time this pulse (φ ₁ ) is input, the FET circuit (Q ₇ ) becomes conductive and the capacitor (C _{7 3} ) is charged to the level of the power supply voltage + V, and the video signal output circuit (VS) is reset. After that, the transfer pulse (φ ₁ ) causes the capacitor (C ₃ ) to repeatedly discharge the charge according to the accumulated charge of the CCD shift register (SR) to be transferred, thereby forming a buffer FE.
The voltage corresponding to each photosensor is output as the video signal (OS) of each pixel from the terminal (T ₃ ) at the connection point of the T circuits (Q ₈ ) and (Q ₉ ), and they form the video signal as a whole. To do.

FIG. 6 shows the CCD shift register (SR) in this embodiment.
3 is a map showing the function sharing of each cell of FIG. There are cells from No. 1 to No. 128, and 27 cells between No. 31 to No. 57 correspond to the image sensor (I ₁ ) in FIG.
Five cells correspond to the image sensor (I ₂ ) in FIG.
The number of cells in the portion corresponding to the image sensor (I ₂ ) is the first to correspond to the image sensor (I ₁ ).
80 to 10 corresponding to 27 cells and image sensor (I ₂ )
Compare the 27 cells up to No. 6, then shift one pixel, compare with the 27 cells from 81 to 107, and finally compare the 27 cells from 87 to 114. _This is because the outputs corresponding to the image sensor (I ₁ ) are sequentially compared while shifting the outputs corresponding to ₂ ) one by one. Focusing, front focus, and rear focus are determined by correlating the results of the respective comparisons. Cells Nos. 1 to 3 are blank feed cells, and half of Nos. 4 to 15 are black reference parts that are covered with a light-shielding mask by aluminum vapor deposition so that light does not completely enter. The electrical characteristics have changed slightly due to vapor deposition.

FIG. 7 shows the circuit configuration of the interface circuit (10). When the microcomputer (8) detects that the shooting preparation switch (S ₁ ) is turned on by pressing the first stroke of the release button (not shown), the microcomputer (8) starts focus detection control. First, the microcomputer (8) uses the integration clear signal (IC
GS) to the photoelectric conversion circuit (12) to reset each photo sensor to the initial state and restore the output (AGCOS) of the brightness monitor circuit (MC) to the initial power supply voltage level by the above signal (ICGS). Let At the same time, the microcomputer (8) receives the high level shift pulse enable signal (SHE
N) is output. At the same time that the integration clear signal (ICGS) disappears, each photosensor of the photoelectric conversion circuit (12) starts optical integration, and the brightness monitor circuit (MC) starts measuring the brightness of the subject and outputs it (AGCOS ) Drops from the power supply voltage in the initial state at a speed according to the brightness of the subject. The gain control circuit (15) is a reference voltage generation circuit (RS).
Output of the reference voltage (DOS) and brightness monitor circuit (M
The output (AGCOS) of C) is used as an input, and 6 levels of other reference voltages are created internally based on the reference voltage (DOS), and these voltages are compared with the brightness monitor voltage (AGCOS). And decide the gain. Output of the brightness monitor circuit (MC) (AGCO) within a certain time TA from the disappearance of the integration clear signal (ICGS)
When the voltage drop of S) is large and becomes a predetermined voltage or less, a high level (TINT) signal is output from the gain control circuit (15) and sent to the microcomputer (8) and the AND circuit (AN1).
As a result, the shift pulse enable signal (SHEN) becomes High.
The AND circuit (AN1) outputs a high level with the signal.
This output signal is output to the shift pulse generation circuit (20) through the OR circuit (OR1) and the shift pulse generation circuit (2
In response to this, 0) outputs a shift pulse (SH) to the photoelectric conversion circuit (12). By this signal (SH), each photosensor of the photoelectric conversion circuit (12) ends integration, and the accumulated charges are transferred in parallel to the corresponding cells of the CCD shift register (SR).

On the other hand, the microcomputer (8) outputs a clock pulse (CL) to the transfer pulse generation circuit (21) from the time when the photographing preparation switch (S1) is turned on. The transfer pulse generation circuit (21) transfers the signals to each other based on the clock pulse.
The transfer pulses φ ₁ and φ ₂ that are out of phase are output. The transfer pulse generation circuit (21) outputs a transfer pulse (φ ₁ ) which rises in synchronization with the output of the OR circuit (OR1) when the output of the OR circuit (OR1) becomes High level. That is, the transfer pulse (φ ₁ ) is synchronized with the shift pulse (SH), but the CCD shift register (SR) has a slight light sensitivity, so that the shift pulse (SH) and the transfer pulse (φ) are _When not synchronized with ₁ ), the CCD shift register (SR) senses light for a shift time which is not synchronized, and charges corresponding to the intensity of light are accumulated as an erroneous signal. Therefore, the transfer pulse (φ ₁ ) is synchronized with the shift pulse (SH) to eliminate the shift time and prevent an erroneous signal from occurring.
After that, the transfer pulses (φ ₁ ) and (φ ₂ ) are sent from the transfer pulse generating circuit (21) to the photoelectric conversion circuit (12. The photoelectric conversion circuit (12) outputs (φ ₁ ) among these transfer pulses.
In synchronism with the falling edge of, the charge accumulated in the CCD shift register (SR) is output as a video signal (OS) in order from the cell edge (No. 1 of the cell in FIG. 6), and is output to the subtraction circuit (14). Output monkey. The video signal (OS) has a lower voltage as the intensity of light incident on the corresponding photosensor is higher, and the voltage (D) subtracted from the reference voltage (DOS) by the subtraction circuit (14).
OS-OS) is output as a pixel signal.

Integration control time TB after the integration clear signal (ICGS) disappears
The output voltage (AGCOS) of the brightness monitor circuit (MC) does not fall below the specified voltage within the predetermined range, and the gain control circuit (15) outputs (TIN
If the T) signal is not output, the microcomputer (8) outputs the shift pulse generation command signal (SH
M) is output to the shift pulse generation circuit (20) through the OR circuit (OR1). The shift pulse generation circuit (20) receives this signal and converts the shift pulse (SH) into a photoelectric conversion circuit (1
2) and outputs the accumulated charge of the photo sensor array (PA) to C
Transfer to CD shift register (SR). Then, as in the case described above, the video signal (OS) is output from the video signal output circuit (Vs) by the transfer pulses (φ ₁ ) and (φ ₂ ),
(DOS-OS) is output from the subtraction circuit (14) as an image signal. The sample-hold circuit (16) is sent from the microcomputer (8) when the pixel signal (DOS-OS) corresponding to the 7th to 10th aluminum mask parts of the CCD shift register (SR) is output. Sample hold signal (S /
H) and hold those pixel signals. This signal is output to the variable gain amplifier circuit (17), and this signal and the eleventh and subsequent pixel signals output from the subtraction circuit (14) are subtracted by the variable gain amplifier circuit (17), and the output of this difference is , A gain controlled by a gain control circuit (15). This amplified signal is A / D converted and digitized by 8-bit pixel signal data or by the binarization circuit (19) and output as 1-bit pixel signal data to the microcomputer (8). . The gain control data obtained by the gain control circuit (15) is also output to the microcomputer (8), and the microcomputer (8) calculates based on the both data, and calculates the amount of image shift until focusing. The microcomputer (8) also calculates a lens drive amount corresponding to the image shift amount based on the pixel signal data, and performs lens control so as to drive a photographing lens (not shown) by the lens drive amount. Controls the circuit (22). Then, the microcomputer (8) repeats the sequence from the generation of the integration clear signal (ICGS) to the lens driving until the photographing lens reaches the in-focus position. As a result of the focus detection calculation, the microcomputer (8) determines that focus detection cannot be performed because of low brightness (LO-LIGHT), and if auxiliary light means is attached, focus detection by auxiliary light is performed. To do. If the auxiliary light unit is not attached, the display circuit (9) displays that focus cannot be detected.

Next, the operation of the entire camera including the focus detection operation will be described with reference to the basic circuit diagram of FIG. 2 and the flow chart of the microcomputer (8) shown in FIGS. 11 to 16.

When the power supply is installed, the reset resistor (R _R ) and capacitor (C _R ) input a signal that changes from “L” level to “H” level to the reset terminal (R) of the microcomputer (8). Then, the microcomputer (8) executes the reset routine shown in FIG. First, the microcomputer (8)
Disables interrupts to this routine and initializes all flags and registers (# 0,5). Then output terminal (O
P1 to OP23) are all set to "L" and it is determined whether or not the shooting preparation switch (S1) is turned on. If not, only the interrupt to INT1 is allowed and the operation is stopped (# 15 ~ # 25).

Shooting preparation switch (S1) is ON with batteries installed
Then, the output of the AND circuit (AN5) becomes "L" level, the power supply transistor (Tr ₁ ) is turned on, the power is supplied to each circuit, and the photometry circuit (3) and the film sensitivity setting circuit (4 ), The photographing mode setting circuit (5) is started and sends a signal to the exposure calculation control circuit (1). Based on the input signal, the exposure calculation control circuit (1) outputs "H" from the terminal (HL) when the aperture value (AV) indicated by the apex is 8 or more.
The signal of is output. When the switch (S1) is turned on, the inverter (IN2) outputs an "H" level signal. This signal is input to the exclusive OR circuit (EOR) via the delay circuit (DEL) and directly to the exclusive OR circuit (EOR) without passing through the delay circuit (DEL). Therefore, the exclusive OR circuit (EOR) is "L" → "H".
→ Output a signal that changes to “L” level to the interrupt terminal (INT1) of the microcomputer (8). Similarly, when the switch (S1) is turned off from ON, a signal changing from "L" to "H" to "L" level is input to the interrupt terminal of the microcomputer (8). As a result, an interrupt is generated in the microcomputer (8) and the INT1 interrupt flow shown in FIG. 11 is executed.

First, the microcomputer (8) enables interrupts other than the timer interrupt, and this interrupt causes the shooting preparation switch (S1).
Input terminal (IP15) for turning on or turning off
It is judged according to the level of (# 35, 40). When it is OFF, the output terminal (OP
Input the signal from (7, 8) and reset the motor flag (MOTF) (# 45, 50). And output terminals (OP9,10,
11) to "L" level to turn off the display, and determine whether or not the film is being wound by the signal input to the input terminal (IP21). If it is winding, wait for the winding to be completed (# 55,60). ). That is, it waits until the level of the terminal (IP21) becomes "H" level. When winding is completed,
Terminal (OP20) to turn off the power supply transistor (Tr ₁ )
To output an "L" level signal (# 65). If it is not winding, immediately feed the transistor (Tr ₁ ).
Control to turn off. And a low contrast flag (LCF) indicating low contrast, 2 in continuous shooting mode
A two-time flag (TWF) that indicates the second and subsequent shots, a low-contrast back flag (LCBF) that indicates the lens retracted state in the lens scan for contrast detection performed at low contrast, and a low-conscan inhibit flag (LSIF) Reset each and set terminal (OP23) to "L"
Set to level to disable interrupts other than INT1 and INT2 interrupts and stop (# 75-90).

In step # 40, if the shooting preparation switch (S1) is ON, the power supply transistor (Tr ₁ ) is turned ON (# 9
2) In order to input the conversion coefficient (KL) from the interchangeable lens, which converts the lens's maximum aperture value and defocus amount into the number of rotations of the lens driving motor, serial data transfer is performed with the circuit inside the interchangeable lens.

First, the chip select signal (CS) indicating that data transfer is performed is set to the “H” level, the variable N indicating the number of times of data transfer is set to 0, and the transfer is performed (# 95 to 105). In this transfer, the clock (SCK) is output from the microcomputer (8) to the lens circuit (7), 1-bit data is output from the lens circuit (7) in synchronization with this rising, and the clock (SCK) rises. In synchronization with the fall, the microcomputer (8)
Read the data. This is performed 8 times, that is, for 8 bits, and one data transfer is completed. Next microcomputer (8)
Adds 1 to the variable N, determines whether N becomes 2, and 2
If not, the process proceeds to step # 105, and if it is 2, it is assumed that the 2-byte data transfer is completed, and the chip select signal (CS) is set to "L" to indicate this.
(# 110-120).

Next, the microcomputer (8) controls focus detection. Before that, reading of data sent from the shift register will be described.

In FIG. 7 described above, after the variable gain control circuit (17), a binarization (1-bit A / D conversion or comparator) circuit is provided in addition to the 8-bit A / D conversion circuit. This binarization circuit is provided in order to speed up the processing related to distance measurement (excluding lens driving) (instead, the distance measurement accuracy is somewhat lowered). The reason why the processing becomes faster is as follows. (I) Since the A / D conversion time for each data is shortened, the data read interval can be shortened.

(Ii) Since the calculation of each data is 1 bit, the calculation time is short.

(Iii) Since it is 1-bit A / D conversion, an analog data signal does not require a data voltage as high as that required for 8 bits. That is, the accumulation (integration) time for accumulating information can be shortened.

The reason is. Specifically, regarding (i), the frequency of the transfer clocks φ ₁ and φ ₂ of the CCD is increased. With regard to (ii), in the operation in the microcomputer (8), the 1-bit operation can be performed at a much higher speed than the 8-bit operation. Regarding (iii), it is performed by changing the average output reference voltage required as data. This will be described. Conventionally, with 8 bits,
Due to the required resolution and S / N, a predetermined voltage (average output reference voltage) (V1) or higher was required as analog data. Therefore, by the time this voltage (V1) is reached,
At a constant brightness, a certain integration time
And) needed. On the other hand, in the case of 1 bit, considering the resolution and S / N due to noise such as dark current, the voltage may be 1/4 or less of the voltage (V1) required for the 8 bits. At the same brightness as in the case of 8 bits, the integration time also
It becomes 1/4 (the dark current of the noise component due to the shortening of the integration time is also reduced and the S / N is the same as that of the 8-bit integration). In the embodiment, instead of monitoring the voltage (V1), the voltage (V1) is managed by the integrated voltage by the light receiving element for monitoring provided near the light receiving portion of the CCD.

The relationship between the integrated voltage and the integration time by the light receiving element for monitoring with respect to brightness will be described with reference to FIG. 10. When processing is performed with 8 bits, the integrated voltage by the light receiving element for monitoring is 1.4V to 2.8V. I have decided. The upper limit of 2.8 V is
It is set so that each pixel of the CCD will not be saturated for a general subject. Therefore, if this voltage (2.8 V) is reached within a predetermined time (50 msec in the example), the CCD
The electric charge stored in is shifted to the shift register. On the other hand, in the case of 1 bit, as described above, 1/4 voltage (0.35 to 0.7V) is sufficient as compared with the case of 8 bits, so if the above-mentioned predetermined time is set to 1/4 (12.5 msec) The good is clear. In order to achieve the above, including this, in the case of 1-bit processing, the circuit of FIG. 8 is configured so that the reference voltage becomes 1/4 times.
This circuit is a detailed depiction of the gain control circuit (15) and variable gain amplifier circuit (17) of FIG.

In FIG. 8, (T11), (T12) and (T13) are terminals connected to the terminals (T1), (T2) and (T3) of FIG. 4, respectively. (T14) is a terminal for inputting the shift pulse generation exponent signal (SHM) output from the microcomputer (8) after the set integration time limit TB has elapsed, and (T15) is the zone in FIG. 5 within the integration time limit. (E) (1 bit) or output terminal of (TINT) signal output when entering zone (G) (8 bits), (T16) is a pixel signal amplified by the variable gain amplifier circuit (17) Is an output terminal for outputting 1 to 8 bits to the A / D conversion circuits (19) and (18). (B1), (B2), (B3), (B4) are buffers, (14 is a subtraction circuit for subtracting the video signal (voltage) OS from the reference voltage (DOS), and (16) holds dark output correction data. This is a sample hold circuit.

First, to explain from the gain control circuit (15), after the disappearance of the integration clear signal (ICGS), a comparator (AC1) that determines the degree of the drop of the output voltage (AGCOS) of the brightness monitor circuit (MC) stepwise, (AC2), (AC3), (AC4) are provided. The inverting input of each comparator is output from the brightness monitor circuit (MC) (AG
COS) is connected to each input terminal (T11).
The non-inverting inputs of the comparators (AC1), (AC2), (AC3) and (AC4) are connected to the connection point (J4) between the resistor (R28) and constant current (IS1), the resistor (R26) and constant current (IS2). Connection point with (J
5), connection point (J6) between the resistor (R24) and constant current (IS3),
They are connected to the connection point (J7) between the resistor (R22) and constant current (IS4), respectively. Resistance (R28), (R26), (R24), (R2
2) Each has a resistor (R27) and an analog switch (AS13)
Series connection, resistor (R25) and analog switch (AS13)
Series connection, resistor (R23) and analog switch (AS11)
Series connection, resistor (R21) and analog switch (AS10)
Are connected in parallel. The value of the resistance (R28) and the value of the resistance (R27) are R28 = (1/3) R27.
Similarly, R26 = (1/3) R25, R24 = (1/3) R23, R22 = (1 /
3) It is R21. As a result, when each analog switch is turned on, the value of the parallel resistance becomes 1/4 of that when the analog switch is turned off. When processing a signal with 1 bit, a signal of "H" level is output from the terminal (OP1) of the microcomputer (8), the analog switch is turned on via the buffer (B4), and the reference voltage changes. .

The resistors (R21) to (R28) are connected to the terminal (T12) to which the reference voltage (DOS) is input via the buffer (B2).
The reference voltage of the comparator is the reference voltage generation circuit (RS).
The output voltage (DOS) of is the voltage obtained by multiplying the (resistance value) and (constant current value) by subtraction. If the resistance value and the constant current value are properly selected, any reference voltage can be obtained. It is possible to make In this way, the brightness monitor circuit (M
It becomes possible to invert the comparator stepwise according to the degree of the drop of the output voltage (AGCOS) of C).
The outputs of the comparators (AC1), (AC2), (AC3) are
They are respectively input to the data terminals (D) of the D flip hoops (DF1), (DF2), (DF3). A shift pulse generation command signal (SHM) of the microcomputer (8) is input to a clock pulse input terminal (CP) that determines the timing of fetching data from these D flip-flops. Specifically, the shift pulse command signal (SHM) is input to the force terminal (CP) of the clock pulse after the integration time limit TB has elapsed, and at this timing, the comparator (AC1), (AC
2) Take in the information of (AC3). Comparator (AC
The output signal (e) of 4) is output when the output point voltage (AGCOS) of the brightness monitor circuit (MC) enters zone (E) or zone (G) in FIG. 10 within the integration time limit ( TINT) signal. The AND circuit (AN11) receives the output Q of the D flip-flop (DF1) and the output of the D flip-flop (DF2) as input, and the AND circuit (AN12)
Has the output Q of the D flip-flop (DF2) and the output of the D flip-flop (DF3) as inputs, and the output signals are (b) and (c), respectively. Further, the output signal of the output of the D flip-flop (DF1) is (d), and these signals (a), (b), (c), (d) and (TINT) signal (e) are the tenth, respectively. Zones (A), (B) in the figure,
It corresponds to (C), (D), (E) (when 1 bit) or zones (C), (D), (E), (F), (G) (when 8 bits). The states of these signals are shown in Table 1.

Of these signals, (a), (b), (c) and (d) are received, and the gain corresponding to each signal is set in the variable gain amplifier circuit (17) described below. In the variable gain amplifier circuit (17), (OP) is an operational amplifier, and its input terminals (f) and (g) are input resistors (R5) and (R6) through a subtraction circuit (4) and a sample hold. Each is connected to the circuit (1). The resistors (R5) to (R14) are resistors that determine the gain, and the resistors (R5), (R6), (R7), (R
If the resistance of 8), (R11), and (R12) is r, the resistance (R
9) and (R13) are set to 2r, and resistors (R10) and (R14) are set to a resistance value with a resistance ratio of 4r. (AS1) ~ (A
S8) is an analog switch, which is described in (a), (b),
Receiving the signals of (c) and (d), the analog switch (AS
1) to (AS4) select resistors (R7) to (R10) to determine the feedback resistance value of the operational amplifier (OP), while analog switches (AS5) to (AS8) select resistors (R11) to (R11) to (R8). R14) is selected to determine the bias resistance value of the operational amplifier (OP).
An analog switch (AS) that conducts when each of the signals (a), (b), (c), and (d) becomes "High".
Table 2 shows the correspondence with 1) to (AS8) and the resistance and gain selected at that time.

Returning to the flow of FIG. 11, when performing the processing with 1 bit as described above, the microcomputer (8) first sets the transfer clocks φ ₁ and φ ₂ to the clock (f ₂ ) at 8 bits. more from faster clock (f ₁₎ and to order the terminal (OP5) outputs a switching signal at "H" level, so as to a reference voltage for gain determination in 1/4 to the terminal (OP1) "H" level Output the signal (# 125, 130). Integration time limit TA, TB is 12.5msec, 25msec
(# 135,140), the pulse signal indicating the integration clear signal is output from the terminal (OP6), the integration to the CCD is started, and the shift pulse enable signal (SHEN) is output (# 135,140,14).
5,150). Then, the integration timer (TM1) is reset and started (# 155).

If the integration is completed while the integration time TA (12.5 msec) is elapsed, the process proceeds to step # 180. If the integration is not completed within the integration time TA, the integration time TB (25 msec) is waited for (# 160- 170). From integration start to integration time TB (25ms
If the integration does not end within ec), the shift register (S
In order to shift the accumulated charge of (R), the shift pulse generation command signal (SHM) of "H" level is output from the terminal (OP3) (# 175), and the shift pulse enable signal (SHEN) is set to "L".
Set level and stop integration timer (# 175
~ 182).

The microcomputer (8) reads the 1-bit data sent in synchronization with the transfer clocks φ ₁ and φ ₂ from the terminal (IP8) and sets the shift pulse generation command signal (SHM) to “L”.
Then, the defocus amount is calculated based on this data (# 185-190). Based on this calculation result, when focus detection is not possible, the process proceeds to step # 237. On the other hand, when focus detection is possible, the low contrast display is turned off and the defocus amount Δε1 is set to this defocus amount # 95 to # 12.
The motor movement amount / rotation speed N1 is obtained by multiplying by the conversion coefficient KL that converts the motor movement amount obtained from the lens by the serial communication explained in 0 to the rotation speed (# 197,20).
0).

Next, the microcomputer (8) sets the low contrast flag (LC
F) is set. If it is set, the flag (LCF) is reset and the process proceeds to step # 210. If it is not set, the motor flag (MOTF) is set.
Is set (# 202 to 205).

If the motor flag (MOTF) is set, that is, if the motor is being driven, the count number ΔX indicating the movement amount of the moved motor during the integration and calculation described above.
Is subtracted from the above-obtained movement amount rotation number N1 to obtain the true movement amount and rotation number N1 (# 205, 210). Similarly to when the motor flag (MOTF) is set, the moving amount rotation speed N1 is set to N2 (# 215). Based on the signal sent from the exposure control calculation circuit (1) and input at the terminal (IP17), the control aperture value (AV) indicated by the apex is 8 or more (F _NO = 16
Or more), or whether it is the second and subsequent shots during continuous shooting, determined by the graph (TWF) indicating this, and whether the aperture value (AV) is 8 or higher If it is the first and subsequent sheets, the motor is driven, the motor flag is set, the process returns to step # 95, and focus detection by 1 bit is performed (# 220 to 235). As described above, this is less accurate in focus detection than in the case of 8 bits, but if the aperture is narrowed down, it will be well within the depth of field, and as a photograph, it will be in good focus. Will be things. The value to be narrowed down is AV = 8 or more. It should be noted that this value differs depending on the operation system and the optical system, and is not limited to this value, and may be any value as long as the focus width in the above 1-bit operation falls within the depth of field. On the other hand, the second and subsequent times of continuous shooting are because the time between shootings is very short, and thus the conventional 8-bit focus detection cannot be performed.

Here, a flow for monitoring the rotation of the motor will be described. The microcomputer (8) performs the count interrupt shown in FIG. 15 every time the pulse signal from the encoder shown in FIG. 7 is received. The encoder is designed to generate 16 pulses each time the motor makes one revolution. To explain the count interrupt shown in FIG. 15, first, the timer interrupt is enabled (# 900). This timer interrupt is an interrupt that is performed when the pulse from the encoder does not arrive for a certain period set by the timer, and is generated when the lens moved by the motor cannot be further moved by driving in the same direction. Next, the microcomputer (8) resets and starts the timer for timer interruption, subtracts 1 from the moving amount rotation speed N2, and obtains ΔX indicating the rotation speed during integration processing (# 905 to 915). Next, if the movement amount rotational speed N2 is less than or equal to the value K2 indicating the vicinity of the in-focus point, the speed of the motor is reduced to determine the movement amount rotational speed N2 to be 0, that is, whether or not the in-focus state is achieved (# 920-935) . If the rotation speed N2 is not 0, the process proceeds to step # 925 and returns. If it is 0, the motor is stopped, the motor flag (MOTF) is reset, and the timer interrupt is prohibited (# 940 to 948). . Then, it is determined whether or not the flag (FIF) indicating 1-bit focus detection in the fill light mode is set, and if it is set, it is reset and the process proceeds to the fill light mode in step # 700. (# 965,9
70). On the other hand, if it is not set, the focus is displayed and an interrupt occurs (# 955,960).

Next, the timer interrupt shown in FIG. 16 will be described. When the pulse from the encoder does not come within the predetermined time, this interrupt occurs, first disable the timer interrupt (# 1000), stop the motor, and reset the motor flag (MOTF) (# 1005,1010). ). Flag indicating whether the motor was moving backward (retracting) (LCBF)
If it is not set, it indicates that the vehicle was moving forward. Control the motor so that it reverses, drive the motor, and set the motor flag (MOTF) (#
1045-1055). Furthermore, the flag (LCBF) that indicates the state in which the motor is moving backward is set, timer interrupts are enabled, and the timer is reset and started (# 1060 ~
1070). The low light flag (LLF) in the auxiliary light mode is determined, and if it is set, the operation proceeds to the auxiliary light mode in step # 700, and if it is not set, the operation proceeds to the normal integration mode in step # 125 (# 1075 to 1085). ). If the flag (LCBF) indicating the reverse drive state of the motor is set, proceed to step # 1020, stop the motor, reset the motor flag (MOTF), perform low contrast display, and reset the above flag (LCBF). And wait for an interrupt (# 1020-1040).

If neither AV ≧ 8 nor TWF = 1, the process proceeds to step # 270, and it is determined whether or not the rotation amount of the moving amount is a predetermined value (K1) or more. If it is the predetermined value or more, the motor is driven. , Set the flags (# 275,280). Where (K
1) is the number of rotations that the motor rotates within the integration time of 100 msec plus the data input and calculation time. In step # 270, the moving amount rotation speed is less than or equal to the predetermined value (K1), or after executing step # 280, the microcomputer (8) sets the integration control time TA, TB to 50 msec, 100 msec.
, The transfer clocks φ ₁ and φ ₂ are f ₂ (<f ₁ ), the reference voltage that determines the gain is 8 bits, the pulse integration clear signal (ICGS) is output, and it is the same as 1 bit. To
Perform the processing required for CCD integration up to step # 342 (# 28
5-342). Then, the 8-bit data is transferred to the terminals (IP _{0 to} I
Input from P ₇ ), set the above command signal (SHM) to “L”,
The defocus amount is calculated, and if focus detection is not possible as a result of this calculation, low contrast display is performed, a flag (LSIF) indicating prohibition of low contrast scanning is set, and step # 125
Move to # (345-402).

If the focus can be detected, the defocus amount Δε1 is multiplied by the conversion coefficient KL to obtain the motor movement amount rotation speed N1. If the motor flag is set, the movement amount rotation moved during integration, data reading, and calculation The number is subtracted from the calculated rotation amount N1 of the moving amount (# 410, 415), and the process proceeds to step # 420.
If the motor flag (MOTF) is not set, step # 415 is skipped, the process proceeds to step # 420, the moving amount rotational speed N1 is set to N2, the process proceeds to step # 275, and the process from this step is repeated.

If focus detection is not possible in steps # 190 and # 195, the process proceeds to step # 237, and if the flag (LSIF) indicating prohibition of low-conscan is set, step # 237
Proceed to 125, and if not set, proceed to step # 240. Then, it is judged whether the reason why the focus cannot be detected is due to the low contrast or the low brightness (hereinafter, referred to as low light) is whether the gain input from the gain control circuit (15) is 4 or more. If it is 4 or more, it is determined to be low light, and the process proceeds to step # 250. If it is less than 4, it is determined to be low contrast and the process proceeds to step # 245 to call a low contrast subroutine.

This subroutine is shown in FIG. 13 and explained. First, low contrast display is performed, it is determined whether the low contrast flag (LCF) is set, and if it is set, it is assumed that this routine has been executed once. Proceed to 525 (# 500,505). On the other hand, if it is not set, proceed to step # 510 and set this flag (LCF).
Is set, and a signal is output to rotate the motor in the normal direction (the direction in which the lens is extended) to drive the motor (# 510-520). At this time, the predetermined value K3 is input to N1 and N2, and the process proceeds to step # 125. The above K3 is a value that is larger than the total number of rotations of the motor in the time required for one integration data input and distance calculation.

Returning to the flow of FIG. 11, when the gain is 4 or more in step # 240, the process proceeds to step # 250, a low light flag (LLF) indicating low brightness is set, and whether the auxiliary light unit is attached is checked. Judging by the terminal (IP20),
If not attached, the process proceeds to step # 285 to perform 8-bit focus detection processing. This is because focus detection may be possible (especially when it is dark) because the resolution increases with 8 bits.

If the fill light means is attached, a flag (FIF) indicating 1-bit processing of fill light is set and a fill light subroutine is called (# 255 to 265). The auxiliary light subroutine is shown in FIG. 14 and explained. First, it is judged whether or not the flag (FIF) indicating the 1-bit processing is set, and if it is set, the integration time is set to 25 msec (# 700, 70).
Five). At this time, the transfer clocks φ ₁ and φ ₂ and the reference voltage for determining the gain remain 1 bit. (flag
FIF) is not set, the integration time is 100ms.
ec, the transfer clocks φ ₁ and φ ₂ are set to f ₂ , and the reference voltage for gain determination is changed to 8 bits (# 710 to 720). After step # 705 or step 720, an “H” level signal is output to the terminal (OP22) to emit auxiliary light (# 725). It outputs the pulse integration clear signal (ICGS) and shift pulse enable signal (SHEN), and resets and starts the integration timer (# 730-740). Waiting for the integration time to elapse, and when this time elapses, the shift pulse generation command signal (SHM) is output to shift the charge stored in the CCD to the shift register (SR) and the "L" level indicating shift pulse inhibition Signal (SHEN) is output to stop the timer (# 745-755). Then, the microcomputer (8) controls to stop the auxiliary light emission, judges the flag (FIF) indicating 1-bit processing, and if set, 1-bit data is set to φ ₁ , φ as 1-bit processing. ₂ is read synchronously, the shift command signal (SHM) is set to the “L” level, and then the defocus amount Δε1 is calculated (# 96
5 to 975). If focus detection is possible from the result of this calculation, a low contrast flag (LCF), a flag indicating the backward movement of the lens (LCBF), and a flag indicating 1-bit processing (FI
F) is reset, and the calculated defocus amount Δε1 is multiplied by the conversion coefficient KL to obtain the moving amount rotation speed N1 (# 785 to 80).
0). Set the travel speed N1 to N2, drive the motor,
Set the flag (MOTF) (# 805-815). And
Turn off the low contrast display and wait for an interrupt (# 82
0,825). On the other hand, in step # 765, when the flag (FIF) indicating 1-bit processing is not set,
As 8-bit processing, 8-bit data is sequentially input in synchronization with clocks φ ₁ and φ ₂ , and a shift command signal (SH
After setting M) to “L”, the defocus amount is calculated by Δε2, and this value is multiplied by the conversion coefficient KL to obtain the moving amount rotation number N1 (# 835 to # 845), and the process proceeds to step 805.

If focus detection is not possible in step # 780, the process proceeds to step # 850, low contrast display is performed, and the moving amount rotation number K3 used during low contrast is set in N2 (# 850, 855). Next, by determining whether the low contrast flag (LCF) is set, it is determined whether the processing for this flow is the first time or the second time or later (# 86).
0). If this flag (LCF) is not set, it is the first process, and first the low contrast flag (LCF) is set, the motor is controlled to drive in the forward direction, the motor is driven, Flag (MOTE)
Set (# 865-880). And step # 700
Repeat the flag from.

When a release signal indicating the start of exposure is input to the interrupt terminal (INT2) of the microcomputer (8) during the focus detection control described above, the microcomputer (8) executes the INT2 interrupt routine shown in FIG. To do. First, all interrupts to this flow are prohibited, the motor is stopped, and the motor flag (MOTF) is reset (# 600-610).

The release signal is also input to the exposure calculation control circuit (1) in FIG. 2, and the aperture and shutter speed are controlled according to the brightness of the subject, the film sensitivity, and the set mode. Then, when the trailing curtain has completed running, the switch (S3) indicating the completion of exposure is turned on, and this signal is converted into a predetermined signal by the exposure calculation control signal (1) and output to the motor control circuit (2). . As a result, the motor control circuit (2) winds one frame, and when the winding of one frame is completed, the switch (S3) is turned off. This switch (S
When 3) turns on, the inverter (IN10) and delay circuit (DE
A signal for switching from “L” to “H” level is input to the microcomputer (8) via L). This signal is input to the microcomputer (8) after the time required for the reflection mirror for guiding the light to the range finder to be stable.
When one frame is wound by the motor (M1), charging of the release system for the next shooting starts at the same time, and along with this, the reflecting mirror is also returned to a position where distance measurement is possible. The delay circuit delays the time required for stabilizing the reflection mirror from the completion of exposure.

The microcomputer (8) waits for a signal that changes from "L" to "H" level to be input. When this signal is input, the signal from the terminal (IP19) is detected to determine whether or not the continuous shooting mode is set. (# 615,620). If it is in continuous shooting mode, it is determined whether or not the release switch (S2) is turned on. If it is not in continuous shooting mode in step # 620, or if the switch (S2) is off in step # 625, , And proceeds to step # 40, and the flow after step # 40 is performed (# 620,625,645). On the other hand, when the continuous shooting mode is set and the release step (S2) is turned on, the flag (TWF) indicating the second and subsequent shootings in the continuous shooting mode is set and the terminal (OP23) is set to ""H", prohibit interrupts other than timer interrupts, and proceed to step (# 125) (# 630-640).

Next, a concrete example of the release signal generating circuit (6) is shown in FIG. 9 and briefly described. First, when it is not the second shooting in the continuous shooting mode, the terminal (OP23) of the microcomputer (8).
The "L" level signal is input from the input terminal, and the AND circuit (AN10) becomes inactive. At this time, the AND circuit (AN11) receives an "H" level signal obtained by inverting the "L" level signal from the terminal (OP23) by the inverter (IN11), and thus is in an active state. When the release switch (S2) is turned on, the “H” level signal is input to the AND circuit (AN11) via the inverter (IN1), and the AND circuit (AN11) outputs the “H” signal Output to shot circuit (OS11). On the other hand, in continuous mode 2
During the second shooting, the signal at the terminal (OP) is at "H" level, so the AND circuit (AN10) receives the inverted "L" level signal and becomes inoperative, and the AND circuit (AN10) becomes active. So, the switch at the end of winding one frame (S3)
The AND circuit (AN10) outputs the release signal.

Next, a modified example is shown in FIG. 17 and will be described. The flow of FIG. 17 is a modification of a part of the flow of FIG. 11. Compared with FIG. 11, steps # 220 and 270 are deleted, and step # 225 is followed by step # 1100. Explaining this flow from step # 215, in step # 215, the moving amount rotation speed N1 is set to N2, and the process proceeds to step # 225.
It is judged whether it is the second or later shooting in continuous shooting, and if it is the second or later shooting, the process proceeds to step # 230, the motor is driven,
Set the motor flag (MOTF) (# 225,230,23
Five). If other than the above, the process proceeds to step # 1100, the moving amount rotation speed N2 is compared with K4 indicating whether the rotation speed corresponds to a predetermined focusing width, and the moving amount rotation speed N2 is greater than this value K4. If is smaller, proceed to step # 275 to drive the motor. If the moving amount rotation speed N2 is K4 or more, the process proceeds to step # 230. The above K4 is preferably a rotation speed corresponding to a focusing width or more that can be obtained by 1-bit processing.

A second modification is shown in FIGS. 18 and 19. The flow in FIG. 18 is the same as the flow in FIG.
It is provided between 5 and # 225, and in this mode, since it is desired to follow the subject at the fastest possible cycle, 1-bit processing is always performed.

Explaining only the flow in FIG. 18, the movement amount rotation number N1 is set to N2 in step # 215, and then the subroutine for tracking mode determination is called. As a result of the subroutine, it is determined whether or not the flag (RAF) indicating the follow-up mode is set, and if it is set, the process proceeds to step # 230 to repeat the 1-bit processing as described above. If the flag (RAF) is not set, the process proceeds to step # 225 and the same processing as the flow shown in FIG. 17 is performed.

Next, the follow-up mode subroutine is shown in FIG. 19 and explained. The one-time flag (ONF) indicating the passage of this flow for the first time is determined, and if it is the first time, step # 1
215, set this flag (ONF), and if you want to control the lens to move out (forward) according to the result of defocusing at this time, set the forward flag (FORF) that indicates this, When controlling to revolve (reverse), reset the foreword flag (FORF) (# 1210-1230). The tracking mode determination flag is reset, the movement amount rotational speed N1 is set to N3, and the process returns (#
1235 ~ # 1245). If the one-time flag is set in step # 1210, the process proceeds to step # 1250, it is determined whether the foreword flag (FORF) is set, and if it is set, the movement of the lens this time is performed. Is determined to be the moving direction, and if it is the moving direction, the process proceeds to step # 1270, and the current moving amount rotational speed N1
The difference between the absolute value of and the previous absolute value of the rotation amount N3 is calculated, and if the direction of the current rotation number N1 is large, that is, if the subject moves, the defocus amount increases. If there is, a follow-up flag indicating this is set, and the defocus amount that becomes larger due to the moving object is corrected by adding the difference in the moving amount rotation speed between this time and the previous time to N2, and the process proceeds to step # 1240. Forward (# 1250, # 1255,
# 1270, # 1275). When the moving amount rotation number N1 of this time is smaller than that of the previous time, step # 1275 is skipped and the process proceeds to step # 1240. If the lens movement is delayed in step # 1255, the one-time flag is reset and the process proceeds to step # 1235. When the forward flag (FORF) is not set in step # 1250, that is, when the previous lens movement is in the retraction direction, the process proceeds to step # 1265, and the current lens movement direction is retraction (retraction). For example, if it is not renormalization, go to step # 1270 and step # 1260, respectively.

Returning to FIG. 18, in the flow when the rightmost shooting preparation switch (S1) is turned off, the one-time flag (ON
F), foreword flag (FORF), follow mode flag (R
Added a step to reset AF).

In the second modification, the follow-up mode determination is performed by the 1-bit processing flow. As a result, if it is the follow-up mode, the 1-bit processing is continuously performed. The flow may be performed (FIG. 11 or FIG. 18), and as a result, when it is determined that the tracking mode is set, 1-bit processing may be performed.

In the above embodiment, the 1-bit A / D converter and the 8-bit A / D converter are used.
Although it is done using the / D converter, the 8-bit A / D converter may be any A / D converter as long as it is larger than 1 bit, and based on this, the flow during the operation of the microcomputer, or The microcomputer itself may be a microcomputer of another bit.

Further, in the case where the arithmetic operation is not performed by the microcomputer but the data respectively input by the separately provided arithmetic circuit is performed under the predetermined arithmetic operation, the arithmetic result may be selected and used.

(Effects of the Invention) As described above, according to the present invention, an image sensor that outputs an analog signal corresponding to an image of a subject on which a lens is dropped, and an A / D converter that converts the analog signal into a digital signal. In the automatic focus detection device including means and a calculation means for calculating the defocus amount by calculating the digital signal, the number of bits of the digital signal is set to a first number of bits or is larger than the first number of bits. Since the selection means for selecting whether to set the number of bits to 2 is provided,
When the focus detection by the second bit number digital signal is not required, the A / D conversion time and the calculation time can be shortened by performing the focus detection by the first bit number digital signal. In addition, since which of the first bit number digital signal and the second bit number digital signal is to be used is selected before lens driving according to the subject situation or the shooting situation, lens drive Compared with the case where the number of bits is changed later, it is not necessary to determine the subject condition or the photographing condition during the lens driving, so the focus detection speed becomes faster. Furthermore, if the number of bits is selected before driving the lens, the accuracy of the data used for focus detection does not change during lens driving, so the movement of the lens is smooth and the feeling of focus detection is good. .

[Brief description of drawings]

FIG. 1 is a claim correspondence diagram showing the basic configuration of the present invention, and FIG.
FIG. 4 is an overall circuit diagram of an automatic focus detection device according to an embodiment of the present invention, FIG. 3 is a schematic configuration diagram showing an optical system used in the above embodiment, and FIG. 4 is a photoelectric conversion circuit used in the above embodiment. 5 is a circuit diagram for explaining the principle of the photosensor used in the above embodiment, FIG. 6 is an explanatory view of the CCD shift register used in the above embodiment, and FIG. FIG. 8 is a circuit diagram showing a structure of an interface circuit used in the example, FIG. 8 is a circuit diagram showing a structure of a gain control circuit and a variable gain amplifier circuit used in the above embodiment, and FIG. 9 is a release signal generation used in the above embodiment. FIG. 10 is a circuit diagram showing the configuration of the circuit, FIG. 10 is an explanatory diagram showing the temporal change of the output voltage of the luminance monitor circuit used in the above embodiment, and FIGS. 11 to 16 are flowcharts showing the operation of the above embodiment. FIG. 17 shows a modification of the above embodiment. Flowchart showing the work,
FIG. 18 and FIG. 19 are flowcharts showing the operation of another modification of the above-mentioned embodiment. (18) is an 8-bit A / D converter, and (19) is a binarization circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuyuki Taniguchi 2-30 Azuchi-cho, Higashi-ku, Osaka-shi, Osaka, Osaka, Osaka International Building Minolta Camera Co., Ltd. (72) Hiroshi Otsuka 2-chome, Azuchi-cho, Higashi-ku, Osaka-shi, Osaka No. 30 Osaka Kokusai Building Minolta Camera Co., Ltd. (56) Reference JP-A-59-107312 (JP, A) JP-A-58-181288 (JP, A)

Claims (7)

[Claims] 1. An image sensor for outputting an analog signal corresponding to a luminance distribution of an image of a subject transmitted through a lens,
The first A / D conversion means for converting the analog signal from the image sensor to the digital signal of the first bit number and the digital signal from the first A / D conversion means are operated to defocus the subject. First calculation means for obtaining the amount, and second A / D conversion means for A / D converting the analog signal from the image sensor into a digital signal having a second bit number larger than the first bit number. A second calculating means for calculating the digital signal from the second A / D converting means to obtain a defocus amount for the object; and the digital signal having the first bit number and the digital signal having the second bit number. An automatic focus detection device including a selection unit that automatically selects which signal to use before driving a lens according to a subject situation or a shooting situation. 2. The apparatus according to claim 1, wherein the selecting means inputs the data after A / D conversion to the arithmetic means and selects the arithmetic means to which the data has been input. An automatic focus detection device, which is a selection unit. 3. The automatic focus detection device according to claim 1, wherein the selecting means is a selecting means for selecting data after calculation. 4. The apparatus according to claim 1, wherein the selection means drives a lens for focus detection if focus detection fails as a result of focus detection, and outputs a 1-bit digital signal. An automatic focus detection device, characterized in that it is means for selecting to perform focus detection using the automatic focus detection device. 5. The automatic focus detection device according to claim 4, wherein the focus detection is performed when auxiliary light for illuminating a subject is used for focus detection prior to photographing. . 6. The apparatus according to claim 1, wherein the selecting means always selects a focus detection using a 1-bit digital signal when the control aperture value is a certain value or more. An automatic focus detection device characterized in that 7. The apparatus according to claim 1, wherein the selection means is set to 1 for the second and subsequent sheets in the continuous shooting mode.
An automatic focus detection device, characterized in that it is means for selecting to perform focus detection using a bit digital signal.