JPH0731618B2 - Information processing equipment - Google Patents

Description

The present invention relates to an information processing apparatus that operates in a micro program control system and has a data buffer.

[Conventional technology]

Conventionally, this type of information processing apparatus detects that the data buffer is empty at the end of processing in operation units,
If it was not empty, it was reporting a failure.

[Problems to be solved by the invention]

The above-mentioned conventional information processing apparatus detects a state in which the data buffer is empty and reports a failure. Therefore, in an apparatus in which there is a state in which the data buffer does not become empty at the end of processing for each operation, an abnormality in the data buffer is detected. There is a drawback that you cannot do it.

[Means for solving problems]

An information processing apparatus according to the present invention operates in a micro program control system, and a control storage unit that stores a micro instruction group that generates a control signal for realizing a function of a software instruction in the information processing apparatus, A request control unit that receives a control signal from the memory operand, generates a memory operand read request signal, and generates a final read request signal when the final data of each soft instruction, and a memory in response to the memory operand read request from the request control unit. A memory control unit that sends an operand and sends a final response information at the same time as a memory operand when a final read request is received from the request control unit, and a memory operand sent by this memory control unit and a final response information are stored. A data buffer and a control signal from the control storage unit. The time of reading the last data operations from the data buffer, and a check means said final response information corresponding to the data for reporting a failure if not stored in the data buffer.

[Action]

When the final data of the operation is reached, the data buffer stores the memory operand and final information. Then, when the control storage unit recognizes that it is the last data of the operation and issues the final buffer read to read the memory operand stored in the data buffer, if there is no final response information corresponding to the memory operand, the read operation is performed. Since the memory operand is not the final data of the operation, it can be determined that the device is abnormal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus of the present invention, and FIG. 2 is a time chart showing its operation.

The control storage unit 1 is a control storage unit that stores a plurality of microinstruction words and sequentially executes the microinstruction words corresponding to software instructions. The request control unit 2 receives an operation start signal from the control storage unit 1 via the signal line 100,
A read request for the memory operand used by the software instruction is issued to the memory control unit 3. That is, a normal read request RQN via the signal line 200, a final read request RQL via the signal line 201, and a memory address ADS corresponding to the normal read request RQN and final read request RQL via the signal line 202.
Respectively. The memory control unit 3 sends a memory operand MO and a normal response RPN to the normal read request RQN from the request control unit 2, and sends a memory operand MO and a final response RPL to the final read request RQL. The normal response RPN is transmitted via the signal line 300, the final response line RPL is transmitted via the signal line 301, and the memory operand MO is transmitted via the signal line 302. The data buffer 40 is a buffer in which the memory operand MO sent by the memory control unit 3 and the final response RPL are stored, and has a plurality of entries.
The write address is given by the value WP held by the buffer write pointer 41 via, and the read address is given by the value RP held by the buffer read pointer 42 via the signal line 402. The buffer write pointer 41 is a pointer to which +1 is added by the normal response RPN or the final response RPL. The buffer read pointer 42 is a pointer to which +1 is added by the normal buffer read RDN or the final buffer read RDL issued from the control storage unit 1. The normal buffer read RDN and the final buffer read RDL are output from the control storage unit 1 via the signal line 101 and the signal line 102, respectively. The register 43 receives the memory operand MO ₁ read from the data buffer 40 and the final response information RPL ₁ on the signal line 4 respectively.
00, hold via signal line 403. The register 44 is a register that receives and holds the final buffer read RDL. The hold condition HLD of the register 43 and the register 44 is HLD = ▲ ▼. The memory operand held by register 43 is M
O ₂ and final response information are RPL ₂ . Memory operand MO ₂
Is output to the outside via the signal line 404. The final read held by register 44 is RDL ₁ .

Register 43 when control memory 1 issues final read RDL
If there is no final response information RPL ₂ corresponding to the data in the data buffer 40 read out, the fault detection signal CK is output to the outside via the signal line 405. The fault detection signal CK is CK = RDL ₁ · ▲ ▼ ₂ . The failure detection signal CK is stored in the data buffer 40 storing the memory operand output by the memory control unit 3 in response to the memory operand read request issued by the request control unit 2 in accordance with an instruction from the control storage unit 1 to the register 43.
When the data is read, the validity of the last data of the operation unit is checked to detect an abnormality in the data. That is, the control storage unit 1 recognizes that it is the last data of the operation and reads the final buffer read RD.
When the memory operand MO ₁ stored in the data buffer 40 is read to the register 43 by issuing L, if the final response information RPL ₁ corresponding to the memory operand MO ₁ is not “1”, the read memory operand is Since it is not the final data of the operation, it is possible to detect the abnormal state of the device.

Next, the operation of this embodiment will be described with reference to the time chart of FIG.

In FIG. 2, a ₀ and a ₁ are operations A, b ₀ is operation B, c ₀ , c ₁ and c ₂ are operations C, d ₀ and d _1.
Indicates a memory operand read request of operation D. The operation here is a memory operand request used by a software instruction. That is, the operations A, B, C, D are software instructions A, B, C, D. Operations A, B, C, D can also be processes A, B, C, D of a memory read operation. In operation A, a ₀ indicates a normal read request and a ₁ indicates a final read request. Operation A will read two memory operands. Operation B
This is the final read request for b ₀ . Operation B performs one memory operand read. Similarly, operation C reads three memory operands and operation D reads two memory operands.

In operation A, a ₀ is a normal read request RQN issued by the request control unit 2 and a ₀₁ is a normal response RPN output by the memory control unit 3 in response to the a ₀ . a ₁ is the final read request RQL issued by the request control unit 2, and a ₁₁
Is the final response RPL output by the memory control unit 3 for the a ₁ .
Is. The buffer write pointer WP is incremented by 1 by a ₀₁ and a ₁₁ . The memory operands output from the memory control unit 3 corresponding to a ₀₁ and a ₁₁ are sequentially stored in the data buffer 40. Buffer entry 0 in FIG.
8 to 8 show a state in which the final response RPL is stored. In operation A, the final response RPL of a ₁₁ is timing T ₅
Indicates that it is stored in the buffer entry 1. A _{02 at} timing T ₆ is the normal buffer read RDN issued by the control storage unit 1, and a _{12 at} timing T ₇ is the final buffer read R issued by the control storage unit 1.
It's DL. The a ₀₂ and a ₁₂ are issued in correspondence with the a ₀ → a ₀₁ and a ₁ → a ₁₁ .

Similarly, in operation B, b ₀₂ corresponds to b ₀ → b ₀₁ , and in operation C, c ₀₂ corresponds to c ₀ → c ₀₁ ,
It is assumed that c ₁₂ is issued to c ₁ → c ₁₁ , c ₂₂ is issued to c ₂ → c ₂₁ , and d ₀₂ is issued to d ₀ → d ₀₁ in the operation D. At the timing T ₈ , the final response information corresponding to the data stored in the data buffer 40 read to the register 43 by a ₁₂ is “1”, so this data is normal. Similarly, at timings T ₉ and T ₁₂ , b ₀₂ and c ₂₂
The data read by is also normal. Timing T ₁₃
The final response information corresponding to the data stored in the data buffer 40 read at d ₀₂ is “0”. That is, there is a contradiction between the request control unit 2, the memory control unit 3, and the control storage unit 1. At this time, the failure detection signal CK is output, and the abnormality in the state of the device is reported to the outside.

〔The invention's effect〕

As described above, according to the present invention, the memory read request, the response to the request, and the instruction for reading the data stored in the data buffer are divided into two types, that is, the final time of the operation and the time of not, and the data is read from the data buffer. By checking whether the collected data is valid, it is possible to detect the abnormality of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of an embodiment of the information processing apparatus of the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1 ... Control storage unit, 2 ... Request control unit, 3 ... Memory control unit, 40 ... Data buffer, 41 ... Buffer write pointer, 42 ... Buffer read pointer, 43,44
… Register, 100 to 102,200 to 202, ... (Signal line), 300
~ 302,400 ~ 405… (Signal line.)

Claims (1)

[Claims] 1. An information processing apparatus, which operates in a micro program control system and has a data buffer, stores a micro instruction group for generating a control signal for realizing a function of a software instruction in the information processing apparatus. And a request control unit that receives a control signal from the control storage unit to generate a memory operand read request signal, and generates a final read request signal when the final data of each software instruction, and a memory operand read from this request control unit. A memory control unit that sends a memory operand in response to a request, and sends the final response information at the same time as the memory operand when a final read request is received from the request control unit, and a memory operand and a final output sent by this memory control unit. Data buffer that stores response information And a check means for reporting a failure when the final data of the operation is read from the data buffer according to the control signal from the control storage unit and the final response information corresponding to the data is not stored in the data buffer. An information processing device comprising: