JPH0731774B2 - Circuit for magnetic head - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit technique and a technique particularly effective when applied to a circuit for a magnetic head. For example, a semiconductor integrated circuit for recording / reproducing in a magnetic disk device. The present invention relates to a technique effectively used for the configuration of the head drive unit.

[Prior Art] FIG. 3 shows a write write amplifier which constitutes a head drive of a magnetic storage device such as a hard disk driver or a floppy disk driver, particularly a recording / reproducing IC (semiconductor integrated circuit) in a magnetic disk device. It is shown. That is, the write amplifier WA has a read / write terminal A to which the power supply voltage Vcc and the inductance load L are connected,
Bipolar transistors Q ₁₁ and Q ₁₂ connected to form a pair between B and transistors Q ₁₃ and Q ₁₄ connected to form a pair between terminals A and B and the constant current source CC ₃ in the same manner.
Including and Then, an inductance load L constituting a magnetic head such as a thin film head is externally attached between the terminals A and B. Complementary write data signals D and d are applied to the base terminals of the transistors Q ₁₁ , Q ₁₂ and Q ₁₃ , Q ₁₄ , respectively. The signal d, is a level-shifted signal of D. As a result, when the write data signal changes, the transistors Q ₁₁ and Q ₁₂ and Q ₁₃ and Q ₁₄ are complementarily switched to change the direction of the current i _H flowing in the head. Data is written to the disc.

An invention relating to a circuit for a magnetic head is, for example, Japanese Patent Application No.
There is a 60-95498 issue.

[Problems to be Solved by the Invention] The magnitude of the inductance load of the magnetic head connected to the recording / reproducing IC is not constant and varies depending on the type of head. In the conventional recording / reproducing IC, the constant current source CC ₀ of the write amplifier WA is composed of an external circuit, and the write amplifier WA
It was designed to be able to change the magnitude of the current flowing to the head depending on the head.

Here, the amplitude of the input signal D of the transistors Q ₁₁ and Q ₁₂ is V
_{If B} and the head inductance are L _H , the change of the current i _H is expressed by di _H / dt = V _B / LH. This means the following. That is, when the magnitude of the current i _H flowing through the load L changes depending on the type of head, the upper transistor Q ₁₁ ,
Q ₁₂ switching speed changes. Specifically, as the current i _H becomes smaller (but V _B is constant), the switching time becomes shorter. However, the lower transistors Q ₁₃ and Q
₁₄ is a current switch circuit are connected to common constant current source CC _0, The input voltage d of the transistor Q _13, Q _14,
Is a signal of constant amplitude generated inside the IC. Therefore,
The switching speed of the lower transistors Q ₁₃ and Q ₁₄ is substantially constant regardless of the magnitude of the current flowing through the head.

As a result, when the magnitude of the current flowing through the load L (head) changes, the switching speeds of the upper transistors Q ₁₁ and Q ₁₂ deviate from the switching speeds of the lower transistors Q ₁₃ and Q ₁₄ , and the current i _H and When the inductance L _H is large, the write current is normal as shown in FIG. 4 (B), but when the current i _H and the inductance L _H are small, the current waveform becomes as shown in FIG. 4 (C). The present inventors have revealed that there is a problem that distortion occurs.

That is, for example, the change of the current i _H when D and d change from the low level to the high level and vice versa changes as follows.
The transistors Q ₁₁ and Q ₁₂ are changed from the off state to the on state and from the on state to the off state at relatively early timings by decreasing the value of at least one of L and i _H. Turning on the transistors Q ₁₁ and Q ₁₂ ,
During such a transient off period, transistor Q ₁₃ ,
Q ₁₄ is still on and off. In other words, there is a period in which the crossed transistors Q ₁₁ and Q ₁₄ are not on at the same time. by this,
The state where the change of i _H is interrupted appears. As a result, the fourth
Distortion appears as shown in FIG.

An object of the present invention is to prevent current distortion even if the inductance of a magnetic head connected to a magnetic head circuit and the current flowing therethrough differ, thereby preventing deterioration of write characteristics and preventing write current It is an object of the present invention to provide a write circuit for a magnetic head that can improve the amplitude margin.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for Solving Problems] An outline of typical ones of inventions disclosed in the present application will be described below.

That is, paying attention to the fact that the switching speed of the transistor pair forming the write amplifier is proportional to the amplitude of the input signal, a current means for flowing a current having a magnitude proportional to the current flowing through the write amplifier, and this current means. A differential amplifier circuit having a constant current source as a constant current source is provided in the preceding stage of the write amplifier, and the amplitude of the write control signal supplied to the write amplifier is changed according to the magnitude of the current supplied to the write amplifier. Is.

[Operation] According to the above-mentioned means, when the current flowing through the write amplifier becomes small, the amplitude of the input signal of the write amplifier becomes small, which speeds up the switching of the transistor pair in the lower stage or the switching of the transistor pair in the upper stage. The speed is slowed down so that the switching speed of the upper and lower transistor pairs is made substantially constant regardless of the magnitude of the current flowing in the write amplifier, so that the current flowing in the head is not distorted. As a result, it is possible to achieve the above-described object of preventing the deterioration of the write characteristics and improving the amplitude margin of the write current.

[Embodiment] FIG. 1 shows an embodiment of a magnetic head circuit according to the present invention.

The circuit of this embodiment is formed on a silicon single crystal semiconductor substrate by a known monolithic integrated circuit technique.

The write amplifier WA as the write circuit of this embodiment has the same structure as the write amplifier in the conventional magnetic head circuit shown in FIG. That is, the write amplifier WA includes a transistor pair Q ₁₁ , Q ₁₂ connected between a pair of read / write terminals A, B to which the power supply voltage Vcc and the inductance load L are connected, and the read / write terminal A, It is composed of a transistor pair Q ₁₃ and Q ₁₄ connected between B and an external constant current source CC ₀ , for example.
The transistor pair Q ₁₁ and Q ₁₂ are input by the input signal D, and the transistor pair Q ₁₃ and Q ₁₄ are input by the input signal d,
By (d, is a signal obtained by level-shifting D,) a complementary switching operation is performed to bridge drive the inductor load L of the head. As a result, the direction of the current passed through the head is changed and the magnetic field is inverted to write on the magnetic disk or the like.

In this embodiment, an external constant current source CC ₀ and a transistor Q
_A transistor Q ₂₁ is connected between the common emitter terminals of ₁₃ and Q ₁₄ , and a shunt transistor Q ₂₂ is provided in parallel with the transistor Q ₂₁ . The emitter terminals of the transistors Q ₂₁ and Q ₂₂ are respectively connected to the constant current source CC ₀ , and the same bias voltage Vc is applied to the base terminals. As a result, a current, which is obtained by dividing the constant current I _0, is supplied to the transistors Q ₂₁ and Q ₂₂ at a rate according to the ratio of the device dimensions. That is, the current flowing in the constant current source CC ₀ is shunted by the transistors Q ₂₁ and Q ₂₂ . In this embodiment, the dimensional ratio is determined so that a large amount of current can flow through the transistor Q ₂₁ on the write amplifier WA side.

Then, the current shunted by the transistor Q _{22 is made} to flow to the differential amplifier circuit PA as a preamplifier provided in the preceding stage of the write amplifier WA. That is, transistors Q ₁ and Q whose emitters are commonly connected to each other
_2, the transistor Q _1, a differential amplifier circuit by a respective resistor connected R _1, R ₂ between the collector terminal Q ₂ 'and the current-voltage terminal Vcc PA is composed, of the transistors Q ₁ and Q ₂ The write signal d, is applied to the base terminal.

Further, the differential amplifier circuit signal d differential output is level-shifted by the level shift circuit LS of PA ',' it has been applied to the base terminal of the lower transistor Q _13, Q ₁₄ of the write amplifier WA. The level shift stage LS is for giving an appropriate level difference to the lower control signal with respect to the upper write control signal D of the write amplifier WA.

In the circuit of the above embodiment, when the current flowing through the load L by the constant current source CC ₀ , that is, the current flowing through the transistor Q ₂₁ is reduced, the current flowing through the differential amplifier circuit PA by the transistor Q ₂₂ is also the same. It is made smaller by the tendency. Therefore, the collector resistance R of the transistors Q ₁ and Q _2
The amount of voltage drop in ₁ and R ₂ is reduced, and the amplitude of the write control signals d ′ and ′ applied to the base terminals of the lower transistors Q ₁₃ and Q ₁₄ forming the write amplifier WA is reduced. As described above, when the current flowing through the load L becomes smaller, the switching speed of the upper transistors Q ₁₁ and Q ₁₂ becomes faster, but the control signal d applied to the base terminals of the lower transistors Q ₁₃ and Q ₁₄ as described above. ',' switching speed of the transistor Q _13, Q ₁₄ also increases accordingly if the amplitude decreases.

In the conventional write amplifier shown in FIG. 5, when the write current i _H becomes smaller, only the switching speed of the upper transistors Q ₁₁ and Q ₁₂ becomes faster, and as a result, the switching speeds of the upper and lower stages become unbalanced. Oops. According to this embodiment, when the switching speed of the upper transistors Q ₁₁ and Q ₁₂ increases as the write current decreases, the lower transistors Q ₁₁ and Q _{12 change} the amplitude of the write control signal supplied to them. Becomes smaller, the switching speed becomes faster. As a result, even if the write current changes, the switching speeds of the upper and lower stages of the write amplifier are kept in balance, and the current waveform is not distorted as shown in FIG. 4 (C).

FIG. 2 shows a second embodiment of the magnetic head circuit according to the present invention.

This embodiment, like the first embodiment, and the transistors Q _21, Q ₂₂ in front of the write amplifier WA is a differential amplifier circuit PA provided to shunt the current I ₀ of the constant current source CC ₀ . The difference from the first embodiment is that a control signal for the upper transistor pair Q ₁₁ and Q ₁₂ forming the differential amplifier circuit PA is supplied from the differential amplifier circuit PA. Moreover, since the forms on the basis of the control signal D for the upper stage transistors Q _11, Q ₁₂ ',' a write control signal D, the level shift circuit LS between the differential amplifier circuit PA and the write amplifier WA also unnecessary is there.

Also in this embodiment, when the current flowing through the load L of the write amplifier WA is reduced, the current flowing through the differential amplifier circuit PA is reduced and the control applied to the base terminals of the transistors Q ₁₁ and Q ₁₂ is controlled. The amplitude of the signals D ',' is reduced. Then, the transistors Q ₁₁ and Q in the upper stage of the write amplifier
_When the amplitude of the base voltage of ₁₂ becomes small, the base voltage of ₁₂ acts to slow down the switching speed, contrary to the transistors Q ₁₃ and Q _{14 in the} lower stage.

As a result, be short load current is small switching time flows L, and the switching speed is slow base voltage amplitude (V _B) is smaller, the transistors of the upper overall Q _11, Q The switching time of ₁₂ is almost constant regardless of the magnitude of the write current. on the other hand,
The switching time of the lower transistors Q ₁₃ and Q ₁₄ is constant regardless of the magnitude of the current. Therefore, the switching times of the pair of transistors in the upper stage and the lower stage of the write amplifier are balanced, and the distortion of the current waveform is prevented.

Although the constant current source CC ₀ is described as an external circuit in the above embodiment, the present invention is not limited to this and may be formed on the same semiconductor substrate as the write amplifier WA. In that case, by providing a constant current transistor and the current mirror connected transistor in place of the transistors Q _21, Q ₂₂ for shunting the size is proportional to the write current flowing to the write amplifier WA to the differential amplifier PA You may make it flow the electric current.

As described above, in this embodiment, attention is paid to the fact that the switching speed of the transistor pair forming the write amplifier is proportional to the amplitude of the input signal, and a current having a magnitude proportional to the current passed through the write amplifier is passed. And a differential amplifier circuit using this current means as a constant current source are provided in the preceding stage of the write amplifier, and the amplitude of the write control signal supplied to the write amplifier is set to the magnitude of the current passed through the write amplifier. As the current flowing to the write amplifier becomes smaller, the amplitude of the input signal of the write amplifier becomes smaller, which speeds up the switching of the lower transistor pair or the switching speed of the upper transistor pair. Is slowed down, and the switching speed of the upper and lower transistor pairs depends on the magnitude of the current flowing in the write amplifier. The effect that is substantially constant regardless, become distorted current flowing to the head does not occur, thereby prevents deterioration of the writing characteristic,
In addition, the amplitude margin of the write current is also improved.

Although the invention made by the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. Absent. For example, in the above embodiment, the amplitude adjusting means is configured by the current branching transistor and the differential amplifier circuit PA. However, the amplitude adjusting means uses the input signals D, D or D depending on the current passed through the write amplifier WA.
Any configuration can be adopted as long as the amplitudes of d and d can be changed.

In the above description, the invention mainly made by the present inventor is described as being applied to the magnetic head circuit in the recording / reproducing IC in the magnetic disk device which is the field of application of the background, but the present invention is not limited thereto. However, it can also be used in a magnetic head drive circuit of a magnetic tape device.

[Effects of the Invention] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to prevent the write current from being distorted, prevent the write characteristic from deteriorating, and improve the amplitude margin.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of a magnetic head circuit according to the present invention, FIG. 2 is a circuit diagram showing a second embodiment of a magnetic head circuit according to the present invention, and FIG. 3 is a magnetic head. FIG. 4A, FIG. 4B, and FIG. 4C are circuit diagrams showing a general configuration example of the write amplifier in the circuit for use in the current, and current waveforms due to differences in the magnitude of the write current and the inductance in the circuit for the conventional magnetic head. FIG. 6 is a waveform diagram showing the difference between FIG. WA …… writing circuit (write amplifier), PA …… differential amplifier circuit, CC _{0 to} CC ₂ …… constant current source, Q ₁₁ , Q ₁₂ …… first transistor pair, Q ₁₃ , Q ₁₄ …… second Transistor pair, Q ₂₁ , Q ₂₂ ……
Current branching means (shunt transistor).

Claims (2)

[Claims] 1. A pair of connection terminals to which a magnetic head constituting an inductance load is connected, and the connection terminal so that the magnetic head is bridge-driven by being complementarily switched during a write operation. A write circuit consisting of a first transistor pair and a second transistor pair connected to the first transistor pair, and the first transistor pair or the second transistor pair in front of the write circuit in proportion to the magnitude of the current applied to the magnetic head. A magnetic head circuit comprising an amplitude adjusting means for changing the amplitude of an input signal of a transistor pair. 2. The amplitude adjusting means is composed of a current branching means for branching a part of a current passed through the write circuit, and a differential amplifier circuit driven by the current branched by the current branching means. The magnetic head circuit according to claim 1, wherein: