JPH0731910B2 - Semiconductor memory circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit device (hereinafter referred to as a memory), and more particularly to a memory composed of complementary insulated gate field effect transistors.

In the memory, one of a plurality of unit storage circuits (hereinafter referred to as memory cells or cells) is selected based on the output signal of the address decoder circuit.

Usually, the address decoder circuit is an insulated gate field effect transistor (hereinafter referred to as FET) which is connected in series or in parallel and is switch-controlled by an address signal.
(Referred to below) as a switch element.

As memory capacity has increased in recent years, an address signal with an increased number of bits is required accordingly, so the number of switch elements connected in series or in parallel must be increased. Come on.

However, the address decoder circuit including an increased number of switch elements has a higher operating speed because the switch elements provide stray capacitances to various nodes of the circuit and have a non-negligible operating resistance. It will be severely limited.

A plurality of memory cells configured as a semiconductor integrated circuit are usually arranged in a matrix on a substrate such as a semiconductor substrate, and the unit decoder circuit forming the address decoder circuit is a memory cell row or column arranged in the matrix. It is arranged corresponding to.

It is required that the unit decoder circuits can be arranged at a pitch corresponding to the pitch of the memory cell rows or the memory cell columns.

However, it becomes difficult for the unit decoder circuit including the increased number of switch elements to be able to be arranged at the above pitch.

The increase in the number of switch elements as described above also means an increase in the area of the element region forming the address decoder circuit on the substrate.

The address decoder circuit can be configured with complementary FETs in order to reduce power consumption by reducing its operating current.

However, the address decoder circuit composed of complementary FETs requires a much larger number of switch elements than the address decoder circuit composed of only single-channel FETs. It is desirable that particular consideration is given to operating speed, pitch, area, and the like.

Therefore, one object of the present invention is to provide a memory capable of increasing the operating speed.

Another object of the present invention is to provide a memory that can reduce the substrate area.

Another object of the present invention is to provide a memory capable of effectively utilizing the surface of the substrate.

Another object of the present invention is to provide a memory suitable for a complementary FET.

Another object of the present invention is to provide a memory that is easy to design.

Other objects of the present invention will be apparent from the following description and drawings.

Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a circuit block diagram of the memory of the embodiment.

In the figure, reference numerals 1 and 14 are row and column address buffer circuits, 2 and 13 are first row and column decoder circuits, and 4 and 12 are second row and column decoder circuits, 5 respectively. And 6 are word drive circuits, 7 and 8 are first and second memory arrays, respectively, and 3 is a word control circuit. Each of the above circuit blocks will be described later in detail with reference to FIGS. 2 to 6. In the figure, 10 is a write circuit, 11 is a read circuit, and 15 is a control circuit.

The control circuit 15 receives the chip select signal and the write control signal at the chip select terminal ▲ ▼ and the write control terminal ▲ ▼, respectively, so that the terminals CS ₁ , CS ₂ , C _W and C _R respectively have the word control circuit 3, A control signal for controlling the operations of the writing circuit 10 and the reading circuit 11 is output.

According to this embodiment, although not particularly limited, each of the memory arrays 7 and 8 is arranged in a matrix of 128 rows and 64 columns in order to obtain a memory capacity of 16 kilobits.
It is composed of 192 static memory cells of 8192 bits.

Each memory cell has a selection terminal and a data input / output terminal.

The selection terminals of the memory cells arranged in the same row are commonly connected to one word line, and the data input / output terminals of the memory cells arranged in the same column are commonly connected to the data line. It

Therefore, each of the memory arrays 7 and 8 has 128 word lines and 64 data line pairs.

The word lines W ₀ to W ₁₂₇ of the memory array 7 are selected by the word drive circuit 5, and the word lines W ₀ ′ to W ₁₂₇ ′ of the memory array 8 are selected by the word drive circuit 6.

In addition, the data line pair of the memory arrays 7 and 8 No Are selected by the input / output circuit 9.

An address signal for selecting the word lines W ₀ to W ₁₂₇ and W ₀ ′ to W ₁₂₇ ′ is supplied by terminals A ₀ to A ₆ and the data line pair Address signals for selecting the to no terminal A ₇ A ₁₃
Supplied by

The row address buffer circuit 1 has a 7-bit address signal (hereinafter referred to as an address signal) supplied to the terminals A ₀ to A _6.
A ₀ to A ₆ ) and non-inverted address signals B ₀ to B ₆ and inverted address signals Is output.

Although not particularly limited, in this embodiment, of the 7-bit address signals output from the address buffer circuit 1, 6-bit address signals, that is, Is supplied to the first decoder circuit 2 and the remaining 1-bit address signal Are supplied to the word control circuit 3.

The first decoder circuit 2 outputs the address signal In response to this, the decode signals MX ₀ to MX ₁₁ are output.

The decode signals MX ₀ to MX ₁₁ are the 6-bit address signals, respectively. No Signal obtained by a combination of specific address signals among the above.

For example, the address signal Are divided into three groups of 2 bits each by the first decoder circuit 2 and are decoded in units of each group.

In this embodiment, the decode signals MX ₀ to MX
₁₁ is finally the address signal No It is called an intermediate term signal because it is a signal obtained in an intermediate stage for obtaining a decoded signal which has a one-to-one correspondence with the state of.

The second decoder circuit 4 outputs the decoded signals K ₀ to K ₆₃ by receiving the intermediate term signal output from the first decoder circuit 2.

Each of the decode signals K ₀ to K ₆₃ is the address signal It is made to correspond one-to-one with the 6-bit state of.

As described above, since each of the intermediate term signals MX ₀ to MX ₁₁ is formed by the logical operation of the 2-bit address signal, each of the decode signals K ₀ to K ₆₃ has the above-mentioned 12-bit intermediate signal. It can be formed by decoding every 3 bits of the term signal.

Decode signal K ₀ output from the second decoder circuit 4
Through K ₆₃ are supplied to the word drive circuits 5 and 6.

The word drive circuits 5 and 6 are the word control circuit 3
Controls its operation.

The word control circuit 3 includes the address buffer circuit 1
Address signal B ₆ and And control signals CS ₁ and CS ₂ output from the control circuit 15,
Address signal B ₇ output from the address buffer circuit 14
as well as By receiving the control signals L ₀ , L ₁ and L ₂ for supplying to the word drive circuit 5 and the control signals R ₀ , R ₁ and R ₂ for supplying to the word drive circuit 6. .

The word drive circuit 5 includes the second decoder circuit 4
A word for selecting 128 word lines of the memory array 7 on the basis of the 64 kinds of decode signals output from the word control circuit 3 and the control signals L ₀ , L ₁ and L ₂ output from the word control circuit 3. It is configured to output a signal.

Similarly, the word drive circuit 6 also has control signals R ₀ , R ₁ and R.
128 word signals, controlled by ₂
It is configured to output to W ₀ ′ to W ₁₂₇ ′.

When a single decoder circuit is used in place of the above first and second decoder circuits, the unit decoder circuits that make up this single decoder circuit each have a 6-bit address signal. Must be decoded.

On the other hand, in the case of the configuration as shown in FIG. 1, the unit decoder circuits constituting the first decoder circuit 2 are each 2
Only the bit address signal needs to be decoded, and the unit decoder circuit constituting the second decoder circuit only needs to decode the 3-bit intermediate term signal as described above.

That is, it is possible to reduce the number of switch elements that are subordinated from the address signal input terminal to the input end of the word drive circuit.

In addition, the number of switch elements in the entire first and second decoder circuits can be reduced.

As shown in FIG. 1 above, when the address signals are substantially decoded by the word drive circuits 5 and 6, the number of unit decoder circuits forming the second decoder circuit 4 with respect to the number of word lines of the memory arrays 7 and 8. Can be reduced.

The address buffer circuit 14 in the above column has the same configuration as the address buffer circuit 1 in the above row, and the input address signal
Non-inverted address signals B ₇ to B ₁₃ and inverted address signals for A ₇ to A ₁₃ Is output.

The first decoder circuit 13 includes a 6-bit address signal of the 7-bit address signal, that is, B ₇ to B ₁₂ and The intermediate term signal based on these address signals
Outputs MY ₀ to MY ₁₁ .

The second decoder circuit 12 receives the intermediate term signals MY ₀ to MY ₁₁
And address signal B ₁₃ and In response, the decoding signals I ₀ to I ₁₂₇ are output.

The decode signals I ₀ to I ₁₂₇ are address signals B ₇ to B ₁₃ and One corresponding to is set to, for example, a high level, and the other is set to a low level.

The input / output circuit 9 is connected between the pair of common data lines and the common data lines and the data lines of the memory arrays 7 and 8 and outputs the output signals I ₀ to I ₀ of the second decoder circuit 12, respectively.
And a column selection circuit (not shown) which is switch-controlled by I ₁₂₇ . The input / output circuit 9 further includes a sense amplifier (not shown) that receives a signal from the common data line, if necessary.

The writing circuit 10 has a non-inverting output terminal Di and an inverting output terminal ▲ which are connected to the common data line of the input / output circuit 9.
I have ▼.

The operation of the write circuit 10 is controlled by a control signal C _W , and when the control signal C _W is at a write operation level such as a high level, the output terminals Di and ▲
The non-inverted signal and the inverted signal corresponding to the signal applied to the input terminal Din are output to ▼. When the control signal C _W is at the non-writing operation level, the output terminals Di and ▲ ▼ are brought into a floating state.

The read circuit 11, its operation is controlled by a control signal C _R, a signal corresponding to the signal outputted from the output circuit 9 when the control signal C _R is the read operation level as the high level Output. When the control signal C _R is a non-read operation level, such as the low level, the output terminal of the readout circuit 11 is in a floating state.

In the memory shown in FIG. 1, the word lines of the memory arrays 7 and 8 are selected by the word drive circuits 5 and 6, and the data lines of the memory arrays 7 and 8 are selected by the input / output circuit 9.

Therefore, only one memory cell selected by the word line and the data line in the memory array 7 or 8 is coupled to the common data line in the input / output circuit 9.

In reading information, the signal level of the common data line determined by the stored information of the selected memory cell is amplified by the sense amplifier in the input / output circuit 9, and the output signal of this sense amplifier is read by the read circuit 11. Read out.

In writing information, the signal level of the common data line in the input / output circuit 9 is determined by the write circuit 10, and the signal of this common data line is supplied to the memory cell via the selected data line. As a result, the signal output from the writing circuit 10 is written in the selected memory cell.

Each of the above circuit blocks is formed on one semiconductor substrate by a known semiconductor integrated circuit technology.

In that case, the above terminals A ₀ to A ₁₃ , Din, Dout, ▲ ▼
The power supply terminals V _CC and GND are used as external terminals of the semiconductor integrated circuit device (IC) together with ▲ and ▼.

Next, a specific circuit example in each of the above circuit blocks will be described.

The present invention is not particularly limited, but is particularly suitable for a memory including complementary FETs. Therefore, the following circuits are mainly composed of complementary FETs.

FIG. 2 shows a specific circuit of a part of the memory arrays 7 and 8 and the input / output circuit 9.

The memory arrays 7 and 8 include memory cells 100 to 103, 104 to 107 and word lines W ₀ ,
W ₁ , W ₀ ′, W ₁ ′, paired data lines Includes data line load FETs N ₁ and N ₂ .

All the memory cells have the same configuration.
As shown in detail as a representative, N-channel FET
A flip-flop circuit composed of N ₇ and N ₈ and load resistances R ₁ and R ₂ composed of a high resistance polysilicon layer, and N channel type FETs N ₅ and N ₆ for transfer. .

It should be noted that the memory cell configured to use the load resistance composed of the high resistance polysilicon layer can be formed on a semiconductor substrate in a relatively small size as compared with the memory cell composed of the complementary FET. . Each of the memory cells can have sufficiently low power consumption by setting the load resistance to a high resistance value. Therefore, although not particularly limited, in this embodiment, the memory cell is of the single-channel type as described above regardless of the fact that other circuits, which will be described later, are constituted by complementary FETs.
Composed of FET.

The gates of the transfer FETs N ₅ and N _{6 form} a memory cell selection terminal. Also, for the above transfer
One output electrode of the FETs N ₅ and N ₆ constitutes the input / output terminal of the memory cell.

As shown in the figure, in each memory array 7 and 8, the selection terminals of the memory cells arranged in the same row are commonly connected to one word line, and a pair of input terminals of each memory cell arranged in the same column are connected. The output terminal is connected to the pair of data lines.

The gates and drains of the above data lines have power supply terminals V _CC
It is connected to the source of the load N-channel FET N ₁ or N ₂ connected to.

The input / output circuit 9 is an N-channel type which constitutes a column selection circuit.
FET N ₃ , N ₄ , common data line Di, ▲ ▼, sense amplifier
_Includes 120 and output line D _OU .

The data line pairs of the memory arrays 7 and 8 are coupled to the common data line Di, ▲ ▼ via the FETs N ₃ and N ₄ , respectively.

The commonly connected gates of the FETs N ₃ and N ₄ corresponding to the data line pair are coupled to the output terminal of the second decoder circuit 12 (see FIG. 1).

The common data lines Di, ▲ ▼ are connected to a pair of input terminals of the preamplifier 120 and a pair of output terminals of the write circuit 10 (see FIG. 1).

The output terminal of the sense amplifier 120 is connected to the output line D _OU .

In the memory arrays 7 and 8, each word line is selected by the high level of the signal because the transfer FET in the memory cell is of the N channel type.

Each data line pair is selected by the high level of the signal output from the second decoder circuit 12.

FIG. 3A is a circuit diagram of the address buffer circuit 1 and the first address decoder circuit 2.

The address buffer circuit 2 is composed of unit buffer circuits 1a to 1g associated with the terminals A ₀ to A ₆ , respectively.

Each unit buffer circuit is composed of _two inverter circuits IV ₁ and IV ₂ connected in cascade.

In each of the inverter circuits IV ₁ and IV ₂ , as shown in FIG. 3C, p-channel FETs P ₀ and n having drains commonly connected to the output terminal OUT and gates commonly connected to the input terminal IN. It is composed of a channel type FET N ₀ . Although not shown in FIG. 2 and the subsequent drawings for convenience of illustration, the body gate of the p-channel FET is similar to the body gate S ₁ of the p-channel FET P _{0 in} FIG. The body gate of the n-channel FET is connected to V _CC, and is connected to the other power supply terminal GND similarly to the body gate S ₂ of the n-channel FET N ₀ .

The first decoder circuit 2 is composed of unit decoder circuits 2a to 2l which output intermediate term signals by receiving partial address signals each divided into 2 bits.

It should be noted that, in the unit decoder circuit, four of them correspond to the above-mentioned partial address signal and substantially form one circuit group. The unit decoder circuit groups 2a to 2il have the same configuration. Therefore, in FIG. 3A, only the circuits of the unit decoder circuit group 2ad are shown in detail.

In the unit decoder circuit group 2ad, the unit decoder circuit 2a includes p-channel type FETs P ₁ and P ₂ and N-channel type FET N.
A NAND circuit configured complementary ₉ and N _10, is composed of a p-channel type FET P ₃ and N-channel type FET N ₁₁ complementary constructed from the inverter circuit receiving an output signal of the NAND circuit There is.

The output signals B ₀ and of the unit buffer circuits 1a and 1b Is at a low level, at least one of the p-channel FETs P ₁ and P ₂ connected in parallel is turned on, and the N-channel FETs connected in series are connected.
Since at least one of N ₉ and N ₁₀ is turned off,
The output signal of the NAND circuit 2a is set to high level.

Above signal By simultaneously setting B ₁ and B ₁ to the high level, the output signal of the NAND circuit 2a is set to the low level. The inverter circuit outputs an inverted signal of the output signal of the NAND circuit 2a.

In the NAND circuit 2a, the rate of change of its output signal is limited by the stray capacitance (not shown) existing between the nodes NA ₀ and NA ₁ of the circuit and the ground point of the circuit, and the ON resistance of each FET. To be done. p-channel FETs P ₁ and P ₂ are connected in parallel, while n-channel FETs N ₉ and N
_{Since 10} are connected in series, the falling speed of the output signal is particularly limited as compared with the rising speed.

However, in this embodiment, as described above,
Since only N-channel FETs are connected in series, the falling speed of the output signal can be made relatively high.

The unit decoder circuits 2b to 2d are the above unit decoder circuits.
Similar to 2a, it is composed of a complementary NAND circuit and an inverter circuit.

With the connection as shown, each of the unit decoder circuits 2a to 2d has a signal B ₀ , formed based on the partial address signals A ₀ and A ₁ . On the other hand, the intermediate term signals MX ₀ to MX ₃ respectively satisfying the following expressions (1) to (4) are output.

The unit decoder circuits 2e to 2h and 2i to 2l similarly use the intermediate term signal MX ₄ based on the partial address signal, respectively.
To MX ₇ and MX ₈ to MX ₁₁ are output.

Each unit decoder circuit group outputs the same number of intermediate term signals as the four signals from the two unit buffer circuits.

When the address signal is divided into 2-bit partial address signals and the partial address signals are decoded as described above, the number of unit decoder circuits can be relatively reduced. In addition, the types of intermediate term signals to be supplied to the second decoder circuit 4 can be reduced accordingly.

FIG. 3B shows detailed circuits of the second decoder circuit 4 and the word drive circuit 5.

The second decoder circuit 4 includes 64 unit decoder circuits 4a.
To 4x, and the word drive circuit 5 is composed of 128 unit drive circuits 5a to 5y.

The unit decoder circuits 4a to 4x have the same configuration.

That is, each of the unit decoder circuits 4a to 4x has p
Channel FET P ₄ to P ₆ and N Channel FET N
_It is composed of a complementary NAND circuit composed of ₁₂ to N ₁₄ .

Each of the unit decoder circuits 4a to 4x has three input terminals. The input terminal connected to the gates of the pair of FETs P ₄ and N ₁₂ is supplied with one of the intermediate term signals MX ₀ to MX ₃ and connected to the gates of the pair of FETs P ₅ and N ₁₃ . The input terminals are connected to the intermediate signal MX ₄ to MX ₇
One of the FETs, and the remaining pair of FETs
The input terminal connected to the gates of P ₆ and N ₁₄ is supplied with one of the intermediate term signals MX ₈ to MX ₁₁ .

Each of the unit decoder circuits 4a to 4x is configured to selectively receive the above-mentioned three types of intermediate term signals, so that each unit decoder circuit 4a to 4x is made to correspond one-to-one with a combination of 6-bit address signals A ₀ to A ₅ .

For example, since the unit decoder circuit 4a is configured to receive the intermediate term signals MX ₀ , MX ₄ and MX ₈ , it is assumed that all the 6-bit address signals A ₀ to A ₅ are at low level. In response, a low level signal K ₀ is output.

The respective output signals of the unit decoder circuits 4a to 4x are supplied to two unit word drive circuits 5a, 5b to 5X, 5Y by the circuit connection shown in the figure.

Each unit word drive circuit is also adapted to receive control signals L ₀ to L ₂ from the word control circuit 3.

The control signal L ₀ is set to the low level corresponding to the low level of the chip selection signal ▲ ▼ of the control signal ▲ ▼ output from the control circuit 15, and the address buffer circuit
When the signal B ₇ output from 14 is set to low level, it is set to low level. The control signal L ₁ is the above control circuit.
Control signal CS1 output from 15 is the chip selection signal ▲
A signal which is set to a high level according to the low level of ▼ and is output from the address buffer circuits 1 and 13 Is set to a low level by setting it to a high level. The control signal L _2, said control signal CS1 is high level addition signal B ₆ Is brought to a high level by bringing it to a high level.

In FIG. 3B, each unit drive circuit 5a to 5y is operated by the output of the corresponding unit decoder circuit 4a to 4x when the chip selection signal {circle around (5)} and the column address signal B ₇ are at low level.

The pair of unit drive circuits 5a or 5b are substantially the same as the row address signal B ₆ or One of them is operated by.

For example, when the output signal K ₀ of the unit decoder circuit 4a is set to the low level according to the low level of the address signals A ₀ to A ₅ as described above, the row address signal Is high level, the control signal L ₁ is set to high level and the control signal L ₂ is set to low level accordingly. The unit drive circuit 5a outputs the high-level word signal W ₀ because the FET P ₇ is turned on and the FETs N ₁₅ to N ₁₇ are turned off. In the unit drive circuit 5b, the control signal L ₂ is set to low level, and the FE
Since TN ₁₆ is turned on, the low-level word signal W
Output ₁

On the contrary, if the row address signal B ₆ is at high level,
In response to this, the word signal W ₁ of the unit drive circuit 5b is set to the high level.

Although not shown, the word drive circuit 6 for the memory array 8 has a configuration similar to that of the word drive circuit 5. The word drive circuit 6 has a chip selection signal ▲
▼ and column address signal Is at a low level, it is operated by the output signal of the second decoder circuit 4.

According to the above configuration, the number of unit decoder circuits in the second decoder circuit can be reduced to half the number of word lines required in the memory array.

In each unit decoder circuit that constitutes the second decoder circuit 4, the number of series-connected FETs that limit the operating speed of the circuit is reduced similarly to the unit decoder circuit in the first decoder circuit.

In FIG. 3A, the complementary inverter circuits IV ₁ and IV ₂ forming the unit buffer circuit need only drive two pairs of FETs. Therefore, the inverter circuits IV ₁ and IV ₂ can be configured to drive a relatively light load.

Similarly, each unit decoder circuit forming the first decoder circuit 2 needs to drive only a relatively small number of pairs of FETs forming the second decoder circuit 4.

As a result, the circuits of FIGS. 3A and 3B can be made relatively small and can operate at high speed.

FIG. 4A shows specific circuits of the column address buffer circuit 14 and the first column decoder circuit 13.

The address buffer circuit 14 is a unit buffer circuit 14a.
Or 14g. Similar to the unit buffer circuit shown in FIG. 3A, each unit buffer circuit is composed of serially connected complementary inverter circuits IV ₁ and IV ₂ .

The first decoder circuit 13 is composed of twelve unit decoder circuits 13a to 13l as shown in the figure.

The unit decoder circuits 13a to 13l have similar configurations to each other. That is, each unit decoder circuit 13
a to 13l are p-channel FETs P ₈ , P ₉ and N, respectively.
From a complementary NOR circuit composed of channel FETs N ₁₈ and N ₁₉ and a complementary inverter circuit composed of P-channel FET P ₁₀ and N-channel FET N ₂₀ for receiving the output signal of the NOR circuit. It is configured.

The unit decoder circuits 13a to 13d constitute a first unit decoder group 13ad and output intermediate term signals MY ₀ to MY ₃ for the 2-bit partial address signals A ₇ and A ₈ , respectively.

With the circuit configuration shown in the figure, the respective intermediate term signals MY ₀ to MY ₃ satisfy the relationships of the following equations (5) to (8), respectively.

_{MY 3 = B 7 + B 8} ...... (8) the unit decoder circuit group 13eh and 13il likewise, in accordance with the partial address signals, to no intermediate term signal MY ₁ outputs the MY ₇ and MY ₈ to MY _11.

Each of the intermediate signal MY ₀ to MY ₁₁ and the output signal B ₁₃ of the unit buffer circuit 14g and Are supplied to the second column decoder circuit 12 of FIG. 4B.

The second decoder circuit 12 is composed of 128 unit decoder circuits 12a to 12u.

As shown, each unit decoder circuit 12a to 12u is composed of a complementary NOR circuit composed of P-channel FETs P ₁₁ to P ₁₄ and N-channel FETs N ₂₁ to N ₂₄ , respectively.

Each unit decoder circuit 12a to 12u has a signal One signal selected from, one signal selected from intermediate term signals MY ₀ to MY _3, one signal selected from intermediate term signals MY ₄ to MY _7, and selected from intermediate term signals MY ₈ to MY _11. A total of four types of signals, each of which is a single signal, are supplied.

As described above, the data line of the memory array is selected by the high level signal from the second decoder circuit 12.

Therefore, the above-mentioned four kinds of signals supplied to each unit decoder circuit are selected to have a high level in a one-to-one correspondence with a desired combination of the levels of the input address signals A ₇ to A ₁₃ .

For example, the unit decoder circuit 12a uses the connection shown in the figure to set all the signals MY ₀ , MY ₄ , MY ₈ and B ₁₃ to the low level, that is, when the address signals A ₇ to A ₁₃ are all set to the low level. At, the high level data line selection signal I ₀ is output.

By providing the first decoder circuit 13, the third decoder
The number of FETs in the second decoder circuit 12 can be reduced and the operating speed of the second decoder circuit 12 can be increased for the same reason as in the case of FIGS.

On the other hand, when the first decoder circuit 13 is not provided, in the unit decoder circuit in the second decoder circuit, a pair of P-channel FETs are provided for each input address signal.
And one N-channel FET will be required. Therefore, for the input address signals A ₇ to A ₁₃ , the unit decoder circuit requires 7 pairs, that is, 14 FETs.

In this example, the input address signal A ₁₃ has no pair of input address signals. Therefore, the address signal generated based on this input address signal A ₁₃ Are sent to the second decoder circuit as described above. By doing so, the number of input lines required for the second decoder circuit 12 is only 14. This number is the same as the number of input lines of the decoder circuit when the first decoder circuit 13 is not provided.

Instead of the above, 3 bits of the input address signals A ₁₁ , A ₁₂ and A ₁₃ may be used as an intermediate term signal to be supplied to the second decoder circuit by decoding this as a partial address signal. By doing so, it is possible to reduce the number of FETs in the unit decoder circuit forming the second decoder circuit by two.

Since the number of FETs in the second decoder circuit is reduced as described above, the number of P-channel type FETs connected between the power supply terminal V _CC and its output is also reduced in this second decoder circuit. Therefore, when all of the P-channel FETs P ₁₁ to P ₁₄ are turned on, the on-resistance of the FET existing between the power supply V _CC and the output node is also reduced. As a result, the driving capability of the second decoder with respect to the load is increased, and the change of the signal from low level to high level can be accelerated.

Moreover, the number of gates of the FETs connected to the input line of the second decoder 12 is 64, which is 1/2 of the number of gates of the FETs connected to the line of the decoder when the first decoder circuit 13 is not provided.
Becomes That is, the load on the first decoder is reduced.
Therefore, the operating speed of the first decoder can be increased. Moreover, since the load of each buffer is only the first decoder, the operating speed of the buffer can be increased.

FIG. 5 is a logic diagram of the word control circuit 3.

The word control circuit 3 includes NAND circuits 150 to 153, NOR circuits 154 and 155, and an inverter 15 as shown in FIG.
It is composed of 6 to 161.

Each of the above circuits is composed of complementary FETs.

Control signals L ₀ and R ₀ output from the word control circuit 3
Is generated to select either the first memory array 7 or the second memory array 8 as described above.
Therefore, when one memory array is selected by the control signal, the other array is deselected.
Therefore, it is possible to prevent an increase in power consumption in the non-selected memory array.

That is, in the memory arrays 7 and 8, the load FETs N ₁ and N ₂ are connected to each data line as shown in FIG. This load FET has a relatively low impedance as compared with the resistance in the memory cell.

When the word line is set to the high level in a memory array in which there is no memory cell to be selected, the high level of this word line causes the transfer FE of the memory cell to be transferred.
TN ₅ and N ₆ are turned on.

As a result, the FET N ₇ or N ₈ of the memory cell
A relatively large current will flow through the FET N ₁ or N ₂ and the transfer FET N ₅ or N ₈ .

According to this embodiment, all word lines in the memory array which do not contain the memory cell to be selected are kept at low level by the control signal L ₀ or R ₀ .
Therefore, it is possible to prevent the above-mentioned current from flowing through the memory cells in this memory array, which prevents an increase in power consumption.

According to the present invention, each of the circuits described above can be formed on one substrate in an arrangement that reduces the reference size.

FIG. 6 shows a pattern of each circuit block formed on one semiconductor substrate 150.

In the figure, the second decoder circuit 4 is formed in the substantially center of the surface of the substrate 150. Word drive circuits 5 and 6 are formed by sandwiching the second decoder circuit 4, and further, a first array 7 and a second array 8 are formed by sandwiching them.

The second decoder 12 is divided into 12 'and 12 ", which are formed below the first array 7 and the second array 8, respectively, and the input / output circuit 9 is also divided into 9'and 9". They are divided and formed between the first array 7 and the second decoder 12 'and between the second array 8 and the second decoder 12 ".

Similarly, the first decoder circuit 13 and the address buffer circuit 14 are also divided into 13 ', 13 "and 14', 14", respectively, and as shown in the figure, the first and second arrays and the second decoder circuits 12 'and 12'. ″, And is formed in a peripheral portion on the surface of the substrate 150 which is separated from the ″ ″.
And formed on the peripheral portion of the surface of the substrate 150 away from the word drive circuits 5 and 6.

The word control circuit 3, the control circuit 15, the writing circuit 10, and the reading circuit 11 are also formed in the peripheral portion on the surface of the substrate 150, as shown in FIG.

In addition, the input add signals A ₀ to A ₀
Bonding pads PA ₀ to PA ₁₃ for connecting the terminal receiving ₁₃ to the terminal outside the circuit device are arranged, and similarly,
Bonding pads P ₁ , P ₂ , P for connecting terminals for receiving voltage, terminals for receiving control signals ▲ ▼, ▲ ▼, terminals for receiving input signal Din, terminals for outputting signal Dout, etc. to terminals outside the circuit device ▲ ▼, P ▲ ▼ and PDin, PDou
The t and the like are arranged around the surface of the substrate 150.

Mutual wiring of each circuit and each bonding pad is performed in a wiring region 151 as indicated by a dot in the figure.

By the way, the repeated dimension, that is, the pitch in the column direction of the plurality of cells forming the array 7 or 8, the pitch of the unit drive circuit in the drive circuit corresponding to the cell, and the second decoder 4 corresponding to the drive circuit. It is desirable that the pitches of the unit decoder circuits in are the same in order to reduce the occupied area of the memory. That is, if the respective pitches of the above three parties are different, the wiring connecting them will be bent, and this bending requires an increased area on the semiconductor substrate. Alignment is required.

Since each memory cell is composed of a relatively small number and a small number of elements, the pitch of the plurality of memory cells is relatively small.

The unit drive circuit forming the word drive circuit and the unit decoder circuit forming the second decoder include a relatively large number of elements. The elements and wirings forming the unit drive circuit and the unit decoder circuit are usually arranged so as to match the pitch of the memory cells.

According to this embodiment, since the number of elements of the second decoder circuit is reduced as described above, the second decoder circuit can be formed in a relatively small lateral dimension.

In the memory, the memory array, the word drive circuit and the second decoder circuit are densely integrated with each other as described above, and as a result, there is no area where other circuits such as peripheral circuits can be arranged. Can't get

On the other hand, a relatively large vacant area can be provided between the peripheral circuits arranged around the circuit and in the vicinity of the bonding pad.

According to this embodiment, the first decoder circuit is arranged around the substrate 150, as shown. As described above, the first decoder circuit can be divided into several unit decoding circuit groups for decoding the partial address signal of 2 bits each, and therefore the first decoder circuit is arranged by effectively utilizing the empty area around the substrate 150. be able to.

As a result, according to this embodiment, the semiconductor substrate can be downsized.

FIG. 7A is a plan view of the unit decoder circuit 4a in the second decoder circuit 4 according to the embodiment of the present invention. In the figure, due to space limitations, P in the unit decoder circuit 4a is shown.
Only channel FET P ₆ and N channel FET N ₁₄ are shown.

In the figure, 150 is an N-type substrate, 152 is a P-type well formed on the substrate 150, 153 and 154 are P-type semiconductor regions, 155 and 156 are N-type semiconductor regions, 82 to 85 and 15.
Reference numeral 9170 denotes aluminum wiring, 157 and 158 conductive polysilicon, and 162 to 164 contact holes.

In the figure, the P-channel type FET P ₆ has a P-type region 153.
And 154 and polysilicon 158, the N-channel FET N ₁₄ is composed of N-type regions 155 and 156 and polysilicon 157. Although not shown in the figure, the P-type region 154 is also used as the drain region of the FETs P ₄ and P ₅ .

The aluminum wirings 82 to 85 are connected to the intermediate term signals MX ₀ to M from the decoder circuits 2a to 2d in the unit shown in FIG. 3A.
X ₃ is supplied. The aluminum wiring 82 has contact holes 16
It is connected to the gate electrode 158 of the FET P ₆ via 2 and further connected to the gate electrode 157 of the FET N ₁₄ via the contact hole 163.

The aluminum wiring 159 is connected to the P-type region 153 through the contact hole 164, and the aluminum wiring 159 is connected to the voltage V
_It serves to supply _CC to one output electrode of PFET P ₆ .

The aluminum wiring 170 is connected to the P-type region 15 through the contact hole 161.
4 connected to N-type region through contact hole 160
It is connected to 156. The output signal K ₀ is taken out through the aluminum wiring 170.

L in the figure indicates the vertical dimension (pitch) of the unit decoder circuit, which is made equal to the pitch of a plurality of cells in the memory array.

FIG. 7 (B) is a sectional view of a section taken along line TT ′ of FIG. 7 (A).

In the figure, 116 and 167 are thick insulating films, and 157
And 169 are the gate oxides of PFET P ₆ and NFET N ₁₄ , respectively.

When the capacity of the memory is increased by reducing the size of the cell, the present invention can be applied to the memory to reduce the size of the second decoder according to the size of the cell as described above. As a result, the chip area can be used effectively.

According to the present invention, the number of FETs forming the second decoder can be reduced. Therefore, the area per FET of the second decoder can be increased by the area occupied by the reduced number of FETs.

By increasing the area of the element in this way, the on-resistance of the element can be reduced. Therefore, the operating speed of the second decoder described with reference to FIGS. 3 and 4 can be further increased.

FIG. 8A is a plan view of an embodiment of the unit decoder circuit which is an alternative to FIG. In the figure, due to space limitations, P-channel FETs P ₅ , P ₆ and N-channel FET N
Only ₁₃ , N ₁₄ are shown.

In the figure, 150 'is an N type substrate, 152' is a P type well,
171, 172 and 173 are P type semiconductor regions, and 174, 175 and 176 are N regions.
Type semiconductor regions, 82 to 89 and 159, 191, 192, 193 are aluminum wirings, and 176, 177 and 179 are conductive type polysilicon.

In the figure, FET P ₆ is composed of P-type semiconductor regions 171, 172 and conductive polysilicon 177, and FET P ₅ is P
It is composed of the type semiconductor regions 171, 173 and the conductive polysilicon 176. FET N ₁₄ is composed of N-type semiconductor regions 174 and 175 and conductive polysilicon 181, and FET N ₁₃ is
It is constituted by N-type semiconductor regions 175 and 176 and conductive polysilicon 180. The aluminum wiring 86 is connected to the gate electrode 176 of the FET P ₅ via the contact hole 202, and further connected to the gate electrode of the FET N ₁₃ via the contact hole 203. Further, the aluminum wiring 82 is connected to the gate electrode 177 of the FET P ₆ via the contact hole 198, and further connected to the gate electrode 181 of the FET N ₁₄ via the contact hole 199.

Further, reference numeral 159 in the figure is an aluminum wiring, which is connected to the P-type semiconductor region 171 through the contact hole 204. The aluminum wiring serves to supply the voltage V _CC to the P-type semiconductor region 171 forming one output electrode of the FETs P ₆ and P ₅ .

The aluminum wiring 193 is for electrically connecting the P-type semiconductor region 173 forming the other output electrode of the FET P ₅ to the conductive polysilicon 179, and the contact holes 200 and 2
It is connected to the P-type region 173 and the polysilicon 179 through 01.

The aluminum wiring 192 is for electrically connecting the P-type region 172 forming the other output electrode of the FET P _{6 to} the polysilicon 179, and is formed through the contact holes 196 and 197.
It is connected to the mold region 172 and the polysilicon 179.

The aluminum wiring 191 is for electrically connecting the N-type region 174 and the polysilicon 179, and is a contact hole.
Via 194 and 195, the polysilicon 179 and the N
It is connected to the mold area 174.

The output signal X ₀ of the unit decoder circuit is taken out from the polysilicon 179.

A sectional view of the above plan view taken along the line P-P 'is shown in FIG. 8 (B).

In the figure, 182 and 183 are thick oxide films. Again 184
Is the gate oxide of FET P ₆ and 185 is the gate oxide of FET N ₁₄ .

The present invention is not limited to the above embodiment.

For example, instead of the unit decoder circuit 12 of Figure 4B, as the 4C view, 'and, the unit decoder circuit 12a' unit decoder circuit 12a unit decoder receiving the output signal and the intermediate-term signal MY ₈ to MY ₁₁ of It can be combined with a circuit. 4th C
In the case of the figure, the number of circuits such as 12a 'can be reduced to 1/4 of that in the case of FIG. 4B.

Further, each circuit may be composed of only a single channel type FET.

FIG. 9 (A) is a circuit diagram of a unit decoder circuit composed of N-channel FETs N ₂₈ to N ₃₂ . This is a circuit diagram of the unit decoder circuit. By doing so, the number of unit decoder circuit elements can be further reduced as compared with a circuit using complementary FETs.

FIG. 9B is a circuit diagram of a unit decoder circuit composed of N-channel type FETs N ₃₃ to N ₃₈ . In this case, the FET N ₃₃ is switch-controlled by the control signal CS1 from the control circuit 15. Therefore, it is possible to prevent the unit decoder circuit from consuming power when the memory is not selected.

FIG. 9C is a circuit diagram of a unit decoder circuit composed of N-channel FETs N ₃₉ to N ₄₆ and inverters 210 to 213. In this case, by providing the inverter, the power consumption of the second decoder can be reduced.

In each of the above embodiments, four address signals corresponding to two input address signals are decoded in the first decoder circuit, and the intermediate term signal obtained by the decoding is decoded again in the second decoder circuit. Was there.

However, the number of input address signals is set to 3 or more, and 6 or more address signals corresponding thereto are decoded in the first decoder circuit, and the intermediate term signal obtained by this is
Further decoding may be performed in the second decoder circuit. By doing so, the number of FETs forming the second decoder circuit can be further reduced.

For example, in the above-described embodiment, the input address signal
When the above-described configuration is applied to A ₀ , A ₁ and A ₂ , the number of FETs forming the second decoder can be set to four.

In this case, the first decoder has a logic circuit as shown in FIG.

The first decoder 2a 'is composed of NAND circuits 222 to 229 and inverters 214 to 221. The address signals B ₀ to B ₂ and B ₀ generated from the address buffer circuit 1 based on the input address signal. To B ₂ are input and decoded intermediate term signals E ₀ to E ₇ are output.

When such a first decoder 2a 'is used, the second decoder
The circuit is as shown in FIG. 10 (B).

The second decoder includes P-channel FETs P ₁₇ , P ₁₈ and N.
It consists of channel FETs N ₄₇ and N ₄₈ .

This second decoder has only two inputs. Any one of the intermediate term signals E ₀ to E ₇ may be applied to each input, for example, the input IN ₈ .

That is, one second decoder is used for the input address signals A ₀ , A
Only two FETs are needed for ₁ and A ₂ .

Therefore, the number of elements of the second decoder circuit can be further reduced.

Although the above-described embodiments apply the present invention to the memory using the static type cells, the present invention is not limited to this and can be applied to the memory using the dynamic type cells. The effect in this case is similar to the effect in each of the above-described embodiments.

[Brief description of drawings]

1 is a block diagram of a memory according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a memory array and an input / output circuit, FIG. 3A is a circuit diagram of a row address buffer circuit and a first decoder circuit, 3B is a circuit diagram of a second decoder circuit and word drive circuit in a row, FIG. 3C is a circuit diagram of an inverter circuit, FIG. 4A is a circuit diagram of a column address buffer circuit and a first decoder circuit, 4B FIG. 4 and FIG. 4C are circuit diagrams of a second decoder circuit, FIG. 5 is a circuit diagram of a word control circuit, FIG. 6 is a layout diagram on a substrate of a memory embodying the present invention, and FIG. ) And (B) are a plan view and a sectional view of a second decoder when the present invention is implemented, and FIGS. 8A and 8B are planes of another second decoder when the present invention is implemented. The drawings, and the cross-sectional views, and FIGS. 9A to 9C show the present invention. Another circuit diagram of a second decoder, and FIG. 10 (A) is a circuit diagram of another first decoder, FIG. 10 (B) is a circuit diagram of another second decoder.

Claims (6)

[Claims] 1. A plurality of memory arrays each having a plurality of memory cells arranged in a row direction and a column direction and having word lines separated from each other, and a row address signal of a plurality of bits are divided into a plurality of groups to be decoded. A first decoder circuit; a second decoder circuit that receives and decodes a decode signal output from the first decoder circuit; A column decode circuit for forming a signal for selecting one of the memory arrays, and one memory array of the plurality of memory arrays for receiving an address signal other than the row address signal and the column address signal of the input address signal. And a control circuit for generating a signal for selectively selecting A plurality of word drive circuits for selectively selecting one word line of the plurality of word lines in each memory array in response to the decode signal from the second decoder circuit. A word to which a memory cell to be selected in one memory array of the plurality of memory arrays is connected by activating one of the plurality of word drive circuits by an output signal of the control circuit. A semiconductor memory circuit device characterized by being configured to activate a line. 2. The second decoder circuit is arranged between the plurality of memory arrays, and the first decoder circuit is arranged outside the second decoder circuit and the plurality of memory arrays. The semiconductor memory circuit device according to claim 1. 3. The plurality of word drive circuits are arranged between the corresponding plurality of memory arrays, and the control circuit is outside the plurality of word drive circuits, the second decoder circuit and the plurality of memory arrays. 3. The semiconductor memory circuit device according to claim 2, wherein the semiconductor memory circuit device is arranged in 4. A plurality of memory arrays in which a plurality of memory cells are arranged in the row direction and the column direction, respectively, and word lines are separated from each other, and a row address signal of a plurality of bits is divided into a plurality of groups and each is decoded. A first decoder circuit and a second decoder circuit for receiving a decode signal output from the first decoder circuit and decoding these signals to form signals for selecting a plurality of word lines from the plurality of memory arrays, respectively. A decoder circuit, a column decode circuit that decodes a multi-bit column address signal to form a signal for selecting one from each of the plurality of columns of the plurality of memory arrays, and the row address of the input address signal Signal and a column address signal other than the address signal to receive one of the plurality of memory arrays. A control circuit for generating a signal for selectively selecting one of the plurality of word lines, and a decoding circuit provided for each of the plurality of memory arrays and decoded by the second decoder circuit. A plurality of word drive circuits that selectively receive one of the plurality of word lines in the corresponding memory array by receiving a signal and an output signal from the control circuit, and decoding these signals. , The word drive circuit selectively activates one word line to which the memory cell to be selected in any one of the memory arrays in which the memory cell to be selected is present is connected. A semiconductor memory circuit device, characterized in that 5. The second decoder circuit is arranged between the plurality of memory arrays, and the first decoder circuit is arranged outside the second decoder circuit and the plurality of memory arrays. The semiconductor memory circuit device according to claim 4, 6. The plurality of word drive circuits are arranged between the corresponding plurality of memory arrays, and the control circuit is outside the plurality of word drive circuits, the second decoder circuit and the plurality of memory arrays. The semiconductor memory circuit device according to claim 5, wherein the semiconductor memory circuit device is arranged in