JPH0732164B2 - Semiconductor device manufacturing method - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a semiconductor device manufacturing method.

[Prior Art] In manufacturing semiconductor devices, a so-called self-alignment technique using a composite mask material is disclosed, for example, in Japanese Patent Application Laid-Open No. 60-1754.
51, JP 60-180482, JP 57-157541
and Japanese Patent Laid-Open No. 62-226667.
Typically, a composite masking member is used, which comprises a first masking member made of silicon dioxide coated on the semiconductor material and a second masking member made of silicon nitride coated on top of that.

The first mask member made of silicon dioxide may contain pinholes or scratches, which, if left untreated, may allow etchant or impurities to penetrate and etch or dope unintended portions of the semiconductor material.

There is a need for improved and new manufacturing methods for semiconductor devices.

[Means for Solving the Problem] The present invention has been made in view of the above-mentioned problems, that is, a method for forming a first coating of silicon dioxide on a main surface of a body of semiconductor material, a region where an impurity is to be introduced into the body of semiconductor material,
a second coating formed over the first coating and the thin silicon dioxide layer, the second coating comprising silicon nitride over the entire surface of the first coating and the thin silicon dioxide layer; a second coating formed over the first coating and the thin silicon dioxide layer, the second coating being formed over the entire surface of the first coating and the thin silicon dioxide layer; a second coating formed over the selected windows, the second coating being formed over the selected windows, the second coating being formed over the selected windows; and a second coating formed over the selected windows, the second coating being ...

[Embodiment] An embodiment of the present invention will now be described with reference to the drawings.

Referring to FIG. 1, the doping step of the planar silicon transistor fabrication process is
A suitable starting material for the N ⁺ -type semiconductor buried region 2 is
The semiconductor device comprises a P-type silicon substrate 1 having a P-type silicon layer 2, an N-type semiconductor epitaxial layer 3 in contact with the substrate 1 and the buried region 2, and a silicon dioxide layer 4 covering the surface of the epitaxial layer 3 and spaced apart from the substrate 1. The silicon dioxide layer has a thickness of about 1 μm. As noted above, the P-type silicon semiconductor substrate 1 is a portion of a silicon wafer in which a plurality of devices fabricated in the manufacturing process are found.

Referring to Figure 2, silicon dioxide layer 4 is masked and etched to leave some surface area of epitaxial layer 3 exposed, and other surfaces of epitaxial layer 3 remain covered with silicon dioxide regions 41 and 42. The outer gap between regions 41 and 42 forms a circular or rectangular ring; that is, the surface of epitaxial layer 3 between region 41 and outer region 42 forms an elongated circular ring and a rectangular shape.
The exposed area of the epitaxial layer 3 is a window through which impurities are introduced into the epitaxial layer 3 in several stages.
The exposed areas are all defined in one step by a single mask. If the perimeter of the gap between regions 41 and 42 is annular, the window in silicon dioxide region 42 will have an annular, or partially annular and rectangular perimeter.
When the perimeter of the gap between 41 and 42 is generally rectangular, the window in region 42 has a generally rectangular perimeter.

Continuing with FIG. 2, photolithographic techniques are used in the masking step, and the etching operation is completed by wet or dry etching. That is, dry etching, which is a plasma etching, is preferred because it provides better precision than wet etching, which results in excessive etching of the sides of the window. Of course, dry etching will attack both silicon dioxide and silicon nitride if both are present, but it can also attack silicon dioxide alone. At the FIG. 2 step, the relative positions of the windows in the silicon dioxide layer corresponding to the windows in the single mask are checked to ensure that the critical dimensions of the mask are preserved in the transfer of the mask to the silicon dioxide layer.

Referring to Figure 3, the exposed surface areas of the epitaxial layer are covered with regions 51, 52 and 53 of thermally grown silicon dioxide having a thickness of approximately 1000 Å. The configuration of regions 51, 52 and 53 of thermally grown silicon dioxide is similar to that of regions 41 and 42.
does not change the relative position of the window defined by

Referring to FIG. 4, silicon dioxide regions 41, 42, 51, and 52
and 53 are covered with a silicon nitride layer 6 having a thickness of about 2,200 Å. The silicon nitride layer 6 is made of silicon nitride (Si
It is formed by a deposition process involving the decomposition of silane (SiH ₄ ) and ammonia (NH _{3 ) to generate silane (SiH 4 )} and ammonia (NH ₃ ), which generates silane (SiH 4 ) and hydrogen (H ₂ ).

Referring to FIG. 5, silicon nitride is a region of nitride material.
A larger mask is used to remove the oxide region 51, leaving 61 and 62. The mask is not only used to remove the larger nitride layer, but does not require precise alignment, since the area through which the diffusion will occur is already defined by the oxide layer below the nitride layer. As is clear from FIG. 5, the nitride layer is removed from the oxide region.
41 and 42 are removed beyond the edges of the oxide region 41
The exact amount of nitride layers 61 and 62 beyond 42 is not critical. Removal of the nitride layer regions is effected by an etchant capable of etching nitride layers much faster than it etches oxide layers. Etching is stopped when the oxide layer thickness in region 51 is estimated to be approximately 500 Å.

6, oxide layer 51 is removed by applying an oxide etchant without significantly reducing regions 41 and 42 that are significantly thicker than oxide layer 51. In fact, to ensure complete removal of oxide region 51, the oxide etchant over-etches region 51, thereby reducing oxide regions 41 and 42.
Some semiconductor material is removed in the area bounded at 42 .

Referring to Figure 7, in this stage boron, a P-type impurity, is diffused into the exposed regions bounded by oxide regions 41 and 42 until the diffusion extends through epitaxial layer 3 into substrate 1, effectively separating epitaxial layer 3 into outer region 31 and inner region 32. Inner region 32 of original epitaxial layer 3 is plate-like and is isolated from outer region 31 by a deep diffusion that extends around the perimeter of inner epitaxial region 32. Thus, the diffusion step of Figure 7 isolates inner epitaxial region 32 from the remainder of original epitaxial layer 3 and isolates oxide regions 41 and 42.
This is completed by growing an oxide region 410 to close the window between the

Referring to Figure 8, the second stage of the process begins by removing the nitride regions overlying the oxide regions 53, again using a larger mask that does not require precise alignment to remove the nitride regions beyond the edges of the oxide regions 53. As previously mentioned, the etchant used is
It is possible to etch nitride semiconductors faster than it etches silicon dioxide, and over time, when the nitride covering oxide region 53 is removed, the thickness of oxide region 53 is reduced to 500 Å.

Referring to Figure 9, the interior epitaxial layer 32 is prepared for the second diffusion step of the process by etching away the thin oxide region 53. As previously mentioned, the thickness of the oxide region 42 bordering region 53 is slightly reduced by exposure to the oxide etchant. The surface of the interior epitaxial region is also slightly eroded due to the etching time required to ensure that all of the oxide layer 53 is removed by the etchant.

Referring to FIG. 10, phosphorus, an N-type impurity,
Diffused into the exposed surface of interior epitaxial region 32 in the exposed areas previously covered with oxide 53, N ⁺ doping material 323 extends through interior epitaxial region 32 and into N ⁺ -type buried region 2. The diffusion step is completed by growing oxide region 411 to close the window of oxide region 42.

11, the inner epitaxial region 32 is prepared in a third stage by removing portions 61 and 62 of the original nitride layer 6 to expose a thin oxide region 52. The oxide region 52 is then removed in a subsequent etching step. As the oxide region 52 is removed, a small amount of the semiconductor material underneath the oxide region 52 is also removed.

Referring to FIG. 12, a thin oxide layer 7 is grown on the exposed surface of the semiconductor and boron ions are implanted through thin oxide layer 7 to create P-type regions 8.

Referring to FIG. 13, the process produces a thin oxide region 7 and a somewhat thicker oxide layer 41, 42, 410 covering the rest of the surface.
and 411 are removed, preparing for the next stage shown in FIG.

Referring to FIG. 14, the structure is heated to diffuse region 8 into inner epitaxial region 32 and to grow a new oxide layer 9 over the entire surface of the structure.

The process shown in FIGS. 1-14 is completed by opening windows in oxide layer 9 covering P-type region 8, and diffusing N-type regions into region 8 from the open windows in oxide layer 9 covering regions 8 and 323.
This is preferably accomplished by providing metal regions that contact regions 8, 323 and the additional region introduced into region 8. The completed device is an NPN planar transistor in which region 32 is the N-type collector electrode, region 8 is the P-type base electrode, and the additional N-type region diffused into region 8 is the emitter electrode.
This completion step, which does not form part of the present invention, is not shown or described in detail.

15-18 show alternative steps from those shown in FIGS. 11-14 that ultimately result from the arrangement of FIG. 10 in the result shown by FIG.

Referring to FIG. 15, the process steps of FIGS. 1-10 are followed by the removal of oxide region 52 without removing any other nitride.
This is achieved by removing the nitride coating covering oxide region 52. The nitride coating covering oxide region 52 is removed using a larger mask, leaving a slightly thicker, surrounded edge of oxide region 42 exposed.

Referring to Figure 16, oxide region 52 is removed and replaced with thin oxide region 7. An N-type impurity such as boron is implanted to provide implanted region 8 within epitaxial region 32, effectively a step that somewhat depresses the semiconductor surface initially covered by oxide region 52.

Referring to Figures 17 and 18, it is clear that the following steps will give the same results as those shown in Figures 13 and 14, respectively.

19-23 illustrate subsequent steps in the fabrication of a planar structure semiconductor resistor, beginning with the step depicted in FIG.

Referring to FIG. 19, along the lines described above in FIG. 7, a deep isolation diffusion effectively completes the isolation of region 32 of the epitaxial layer, and the diffusion area is further covered with silicon dioxide region 410.

Referring to FIG. 20, nitride coating 63 is formed on a thin silicon dioxide coating 54 bounded by thicker silicon dioxide regions 42.
is removed to expose the

Referring to FIG. 21, the thin silicon dioxide coating 54 is removed with an etchant to expose the silicon material indicia.

Referring to FIG. 22, a thin coating of silicon dioxide 10 is grown on the exposed silicon material surface, and a photoresist coating 11 having apertures defining two rectangular perimeter regions is applied over the epitaxial layer 32.
Impurities are implanted using the host resist coating and silicon dioxide coating as masks to provide doped regions 324 and 325. Referring to Figure 23,
The photoresist coating is removed and impurities are implanted through the silicon dioxide coating 10 to provide a semiconductor resistor body 326 connected to implanted regions 324 and 325 which serve as terminals.

As described above, the remaining layers 41, 42, 410, and 10 of the original silicon dioxide coating are removed from the structure shown in FIG. 23;
A new coating of silicon dioxide is then formed to provide a generally planar surface for subsequent process steps.

24 and 25 show the body of the resistor shown in FIG.
Shown in plan view are implant areas 324 and 325 which are semiconductor end contact areas for resistor 326 and contact pads 27 and 28 which will be provided in later processing steps to facilitate external connection to resistor body 326.

Referring to Figure 24, contact pads 27 and 28, which are smaller than end contact areas 324 and 325, are positioned to add the length of the resistor body 326 to the length of the shaded areas 21 and 22. Thus, the value of the semiconductor resistor is effectively the resistance of the body 326, but that value is increased only slightly by the resistance of the entire length of the shaded areas 22 and 23, which coincide with the extension of the resistor body 326.

Referring to Fig. 25, contact pads 27 and 28 may be placed in slightly different positions on contact areas 324 and 325, but obviously the total length of the shaded areas shown in Fig. 25 is the same as the total length of shaded areas 21 and 22 shown in Fig. 24, and therefore the resistor provided by the arrangement represented by Fig. 24 has the same value as the value provided by the arrangement represented by Fig. 25. That is, the arrangement of the mask defining the area covered by contact pads 27 and 28 need not be performed with great precision, the only practical restriction being that pads 27 or 28 may not extend outside of areas 324 and 325.
The total length of the shaded areas 23 and 24 along the line
27 and the spacing of the windows for contact pads 27 and 28 on the mask containing these windows.

1-23 represent major steps in the fabrication of planar semiconductor devices, thus resulting in substantially complete planar transistors, e.g., requiring only conventional emitter diffusion, final passivation, and metallization to complete the planar transistor on a complete wafer. Thus, it will be appreciated that wafers containing nearly complete devices can be fabricated in-situ by the fabrication methods described herein and then moved to another location for completion.

The main features of the fabrication process described with reference to the accompanying drawings are as follows: 1. The fabrication method can utilize a three layer composite mask to provide the base region, deep N ⁺ connection to the buried collector layer for the planar transistor.

2. A four layer composite mask can be used if the fourth layer is an implant resistor layer.

3. In applying this method to silicon wafers, dry (plasma-assisted) etching can be used because etching of the masking silicon dioxide coating occurs before any silicon nitride deposition occurs. Furthermore, the amount of features transferred from the composite mask to the silicon dioxide coating can be inspected before further processing occurs. Dry etching is a more precise manufacturing process than wet etching, which must be used if silicon nitride is present.

4. The composite mask does not include (it does not require) any resistate tolerances, so that no semiconductor material is consumed in providing the resistate tolerances.

5. Defects in the first coating, i.e., silicon dioxide coating, can occur when silicon semiconductor wafers are used:
Any imperfections such as pinholes or scratches are generally covered by the second coating during the manufacturing process and do not result in defects, and imperfections in the second coating do not result in exposed semiconductor material due to the presence of the first coating.

6. The first coating is inspected after an etching step that transfers the features of the three or four layer composite mask, and all dimensions, including the critical dimensions, are available for inspection.
This is not the case if the etching of the coating is done with a second coating in place.

7. All remaining first and second coatings are meant to be encountered in planar transistors where any final metallization layer will be thicker than the thickness of a single coating of semiconductor compound along the surface of the finished device.

8. All dimensions are set by the mask used to define the window in the first coating. The mask used to open the masking in the second coating does not need to be manufactured or positioned with high precision, since their function is actually to select the window already defined by the mask used for the window in the first coating.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 14 are cross-sectional views illustrating a manufacturing method of a first embodiment of the present invention, FIGS. 15 to 18 are cross-sectional views illustrating a manufacturing method of a second embodiment of the present invention, and FIGS. 19 to 20 are cross-sectional views illustrating a manufacturing method of a second embodiment of the present invention.
FIG. 23 is a cross-sectional view illustrating a manufacturing method of a third embodiment of the present invention, and FIGS. 24 and 25 are plan views of the resistor shown in FIG. 23.

Explanation of Reference Signs 3... Body of semiconductor material, 4, 41, 42... First coating, 6, 61,
62... second coating, 51, 52... thin silicon dioxide portions, 3
23...Dope area.

Claims (7)

[Claims] [Claim 1] A method for manufacturing semiconductor devices in which, in each of the separate stages, a plurality of doped regions of a semiconductor device are formed by introducing impurities into a body of semiconductor material from specific regions of a major surface of the body of semiconductor material, the method comprising: forming a first coating of silicon dioxide over the major surface of the body of semiconductor material, the first coating including a plurality of windows defining all regions of the semiconductor device including isolation regions, each of the windows having a portion that is significantly thinner than the thickest portion of the first coating; forming a second coating of silicon nitride immediately over the first coating and covering the entire surface of the first coating, and releasing selected ones of the windows; and, in each of the separate stages, removing the thin portions of the first coating and then introducing impurities into the body of semiconductor material through the released windows by diffusion to form the doped regions of the semiconductor device. 2. A method for manufacturing semiconductor devices in which, in each separate stage, an impurity is introduced into a body of semiconductor material from a specific region of a major surface of the body of semiconductor material, comprising: forming a first coating of silicon dioxide over the major surface of the body of semiconductor material; etching windows in the first coating that define regions of the body of semiconductor material into which the impurity is to be introduced, the regions including isolation regions;
1. A method for fabricating a semiconductor device, comprising the steps of: covering the etched areas with a layer of silicon dioxide that is significantly thinner than said first coating; forming a second coating of silicon nitride immediately over said first coating and thin silicon dioxide layer, said second coating comprising silicon nitride over said first coating and thin silicon dioxide layer, and releasing selected ones of said windows; and after removing said thin silicon dioxide layer in one of said stages, introducing impurities by diffusion through said released windows into said body of semiconductor material to form doped regions of said semiconductor device. [Claim 3] A method for manufacturing a bipolar semiconductor device in which impurities are introduced into a body of semiconductor material in separate stages from specific regions of a major surface of the body of semiconductor material, the method comprising the steps of: forming a first coating of silicon dioxide over the major surface of the body of semiconductor material, the first coating including windows defining areas of the body of semiconductor material where the impurities are to be introduced, the areas including isolation regions, each of the windows having a thickness that is significantly thinner than the thickest portion of the first coating; forming a second coating of silicon nitride immediately over the first coating and covering the entire surface of the first coating, and releasing selected ones of the windows; and removing the thinner portions of the first coating in one of the stages and then introducing impurities into the body of semiconductor material through the released windows by diffusion to form doped regions of the bipolar semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the window in the first coating is formed by substantially removing by etching the portion of the first coating that is above the specific area defined by a mask, and then removing the first coating.
a thin portion of the coating is formed in the window. 5. A method for manufacturing a semiconductor device as claimed in any one of claims 1 to 4, further comprising the step of closing the window with a third coating made of the same material as the first coating, following the step of introducing the impurity through the opened window. [Claim 6] A semiconductor device manufacturing method as described in any one of claims 1 to 5, further comprising the steps of: removing the second coating from the finally selected window; removing the thin silicon dioxide layer or a thin portion of the first coating from the finally selected window; and coating the finally selected window with a fourth coating made of the same material as the first coating formed to a thickness that allows for the implantation of impurities. 7. The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: introducing the impurity from the finally selected window;
The method for manufacturing a semiconductor device further comprising the step of removing the remainder of each coating to provide a substantially flat surface for further processing.