JPH0732300B2 - Method for forming a circuit pattern conductive film on a flat metal substrate - Google Patents
Method for forming a circuit pattern conductive film on a flat metal substrateInfo
- Publication number
- JPH0732300B2 JPH0732300B2 JP22483685A JP22483685A JPH0732300B2 JP H0732300 B2 JPH0732300 B2 JP H0732300B2 JP 22483685 A JP22483685 A JP 22483685A JP 22483685 A JP22483685 A JP 22483685A JP H0732300 B2 JPH0732300 B2 JP H0732300B2
- Authority
- JP
- Japan
- Prior art keywords
- metal substrate
- plating
- substrate
- flat metal
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims description 64
- 229910052751 metal Inorganic materials 0.000 title claims description 39
- 239000002184 metal Substances 0.000 title claims description 39
- 238000000034 method Methods 0.000 title claims description 11
- 238000007747 plating Methods 0.000 claims description 40
- 238000009713 electroplating Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 3
- 239000003566 sealing material Substances 0.000 claims description 3
- 238000009826 distribution Methods 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PEVJCYPAFCUXEZ-UHFFFAOYSA-J dicopper;phosphonato phosphate Chemical compound [Cu+2].[Cu+2].[O-]P([O-])(=O)OP([O-])([O-])=O PEVJCYPAFCUXEZ-UHFFFAOYSA-J 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
Landscapes
- Electroplating Methods And Accessories (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、平面状金属基板への回路パターン状導電膜形
成方法に関し、特に平面状金属基板上に電解メッキによ
り所望する回路パターン状導電膜を付着させる導電膜形
成方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for forming a circuit pattern conductive film on a flat metal substrate, and particularly to a desired circuit pattern conductive film by electrolytic plating on a flat metal substrate. The present invention relates to a method for forming a conductive film which adheres.
［開示の概要］ 本発明は、平面状金属基板上に電解メッキにより回路パ
ターンの導体膜を付着させて平面状印刷回路基板を製造
するにあたり、前記平面状金属基板にメッキ電流を通電
するための電極は、前記平面状金属基板と電気的に接続
される接点を有し、その接点の個数を、前記平面状金属
基板の面積300〜1200cm2あたりに１個づつ設け、前記電
極のうち前記接点の部分以外をシール材によりメッキ浴
に対してシールし、前記接点を前記平面状金属基板に電
気的に接続した状態で前記電極に取り付けた前記平面状
金属基板を前記メッキ浴に浸漬して電解メッキを行うこ
とにより、平面状金属基板に対するメッキ膜厚の分布を
均一にでき、基板面積に見合った個数の接点をあらかじ
めカソード電極に設けておけば、平面状金属基板が大版
であっても、そのメッキ膜厚の分布を均一にでき、平面
状印刷回路基板を歩留りよく量産するのに好適である。[Summary of Disclosure] The present invention provides a method for applying a plating current to a flat metal substrate when a flat printed circuit board is manufactured by depositing a conductor film of a circuit pattern on the flat metal substrate by electrolytic plating. The electrode has a contact that is electrically connected to the planar metal substrate, and the number of the contact is provided one per 300 to 1200 cm 2 of the planar metal substrate. The portion other than the above is sealed with a sealing material against the plating bath, and the flat metal substrate attached to the electrode in a state where the contacts are electrically connected to the flat metal substrate is immersed in the plating bath for electrolysis. By plating, the distribution of the plating film thickness on the flat metal substrate can be made uniform, and if the number of contacts corresponding to the substrate area is provided on the cathode electrode in advance, the flat metal substrate will be a large plate. Also, can a distribution of the plating film thickness uniform, it is suitable for mass production well planar printed circuit board yield.
本願の平面状基板の面積は、表裏両面の合計を示し、た
とえば40cm×50cmの基板の面積は4000cm2となる。The area of the planar substrate of the present application indicates the total of the front and back surfaces, and for example, the area of a 40 cm × 50 cm substrate is 4000 cm 2 .
なお、この概要はあくまでも本発明の技術内容に迅速に
アクセスするためにのみ供されるものであって、本発明
の技術的範囲および権利解釈に対しては何の影響も及ぼ
さないものである。It should be noted that this outline is provided only for quick access to the technical contents of the present invention, and has no influence on the technical scope and the interpretation of rights of the present invention.
［従来の技術］ 金属薄板上において、回路部以外の所にレジストを設
け、電解メッキにより回路部に導電体を形成した後、該
金属薄板の全面または回路部以外の所を除去することに
より、平面状の印刷回路基板を製造する方法において、
従来の電解メッキ工程では導電性の材質によるクリップ
を使ってメッキ電流を基板に供給していたが、基板のメ
ッキを行いたい箇所以外にも不所望にメッキ電流が流れ
たり、クリップ自体が漏れたメッキ電流によってメッキ
されるので、メッキ電流を制御するのが困難であった。
これを解決すべく、特開昭57−207393号では、メッキを
行う基板への電流供給電極の部分をメッキ液に対して封
止することが開示されている。[Prior Art] By providing a resist on a portion other than a circuit portion on a metal thin plate, forming a conductor on the circuit portion by electrolytic plating, and then removing the entire surface of the metal thin plate or a portion other than the circuit portion, In a method of manufacturing a planar printed circuit board,
In the conventional electrolytic plating process, a clip made of a conductive material was used to supply the plating current to the board.However, the plating current flowed undesirably in places other than where the board was desired to be plated, or the clip itself leaked. Since plating is performed by the plating current, it is difficult to control the plating current.
In order to solve this, JP-A-57-207393 discloses that the portion of the current supply electrode for the substrate to be plated is sealed with the plating solution.
この方法によって、メッキ電流全体の制御はなされて
も、基板に流れる電流の分布は一様ではなく、電解メッ
キにより平面基板上に均一な厚さで導電体膜を形成する
のは困難である。特に、大量生産を目指して、１枚の基
板上に多数の電子部品のパターンを配置するような場合
には、基板の面積が1000〜2000cm2以上にもなり、均一
な厚さの膜を作ることが非常に困難である。加えて、か
かるパターンが微細であるときには、上述したメッキ電
流の分布は一様でない影響が大きく、歩留りが悪い。Even if the entire plating current is controlled by this method, the distribution of the current flowing through the substrate is not uniform, and it is difficult to form a conductor film with a uniform thickness on a flat substrate by electrolytic plating. In particular, when a large number of electronic component patterns are arranged on one substrate for mass production, the area of the substrate becomes 1000 to 2000 cm 2 or more, and a film with a uniform thickness is formed. Is very difficult. In addition, when such a pattern is fine, the above-mentioned distribution of the plating current has a large uneven effect, resulting in a poor yield.
［発明が解決しようとする問題点］ そこで、本発明の目的は、上述した欠点を解決し、平面
状金属基板上に均一な膜厚分布で電解メッキを行って、
平面状金属基板への回路パターン状導電膜形成方法を提
供することにある。[Problems to be Solved by the Invention] Therefore, an object of the present invention is to solve the above-mentioned drawbacks and perform electrolytic plating with a uniform film thickness distribution on a flat metal substrate,
Another object of the present invention is to provide a method for forming a circuit pattern conductive film on a flat metal substrate.
［問題点を解決するための手段］ このような目的を達成するために、本発明は、平面状金
属基板上に電解メッキにより回路パターンの導体膜を付
着させて平面状印刷回路基板を製造するにあたり、平面
状金属基板にメッキ電流を通電するための電極は、平面
状金属基板と電気的に接続される接点を有し、その接点
の個数を、平面状金属基板の面積Ｓdm2 あたりに１個ずつ設け、電極のうち接点の部分以外をシ
ール材によりメッキ浴に対してシールし、接点を平面状
金属基板に電気的に接続した状態で電極に取り付けた平
面状金属基板をメッキ浴に浸漬して電解メッキを行うこ
とを特徴とする。[Means for Solving Problems] In order to achieve such an object, the present invention manufactures a planar printed circuit board by depositing a conductor film of a circuit pattern on a planar metal substrate by electrolytic plating. At this time, the electrode for supplying the plating current to the flat metal substrate has a contact electrically connected to the flat metal substrate, and the number of the contacts is determined by the area Sdm 2 of the flat metal substrate. One on each side of the electrode, except the contact part of the electrode is sealed against the plating bath with a sealing material, and the flat metal substrate attached to the electrode is plated while the contact is electrically connected to the flat metal substrate. It is characterized in that it is immersed in a bath for electrolytic plating.
［作用］ 本発明によれば、平面状金属基板に対するメッキ膜厚の
分布を均一にでき、基板面積に見合った個数の接点をあ
らかじめカソード電極に設けておけば、平面状金属基板
が大版であっても、そのメッキ膜厚の分布を均一にで
き、平面状印刷回路基板を歩留りよく量産するのに好適
である。[Operation] According to the present invention, the distribution of the plating film thickness on the flat metal substrate can be made uniform, and if the cathode electrode is provided in advance with a number of contacts commensurate with the substrate area, the flat metal substrate becomes a large plate. Even if there is, the distribution of the plating film thickness can be made uniform, which is suitable for mass-producing flat printed circuit boards with high yield.
［実施例］ 以下に、図面を参照して本発明を詳細に説明する。[Examples] Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図は本発明方法を実施するのに用いるカソード電極
の一例を示す。ここで、１はロ形フレーム形状のカソー
ド電極であり、たとえば、銅などの導電体製のほぼロ形
形状をなした骨組をメッキ浴に対して耐性のある絶縁
体、たとえば2mm厚のシリコーンゴムで被覆し、その内
部空間に向けて複数個、たとえば４つのクリップ２を突
出させる。これらクリップ２により平面状金属基板３を
挟持するが、ここで、クリップ２の接点部分では絶縁体
を塗布せず、骨組の導電体を露出させて平面基板３と電
気的に接続する。このように構成した２枚のカソード電
極１により平面状金属基板３の両面をはさみ込んで、両
フレームを固着し、そのクリップ２の接点部により平面
状金属基板３に対して電気的接続を行うと共にこの基板
３を把持する。このように平面状金属基板３を支持した
カソード電極１をメッキ浴４中に浸漬して、このカソー
ド電極１とアノード電極（図示せず）との間で電解メッ
キを行う。FIG. 1 shows an example of a cathode electrode used for carrying out the method of the present invention. Here, 1 is a cathode electrode in the shape of a square frame, for example, a substantially square frame made of a conductor such as copper is an insulator resistant to the plating bath, for example, a silicone rubber having a thickness of 2 mm. And a plurality of, for example, four clips 2 are projected toward the inner space. The planar metal substrate 3 is sandwiched by these clips 2. Here, an insulator is not applied at the contact portion of the clip 2 and the conductor of the skeleton is exposed and electrically connected to the planar substrate 3. By sandwiching both sides of the planar metal substrate 3 by the two cathode electrodes 1 thus configured, both frames are fixed, and the contact portion of the clip 2 electrically connects to the planar metal substrate 3. At the same time, the substrate 3 is gripped. The cathode electrode 1 thus supporting the flat metal substrate 3 is immersed in the plating bath 4 to perform electrolytic plating between the cathode electrode 1 and the anode electrode (not shown).
ここで、カソード電極１は、図中にハッチングを付して
示す部分にシールを施してメッキ浴４に直接にさらされ
ないようにすると共に、クリップ２についても、特開昭
57−207393号に開示されているようにシールを施すのが
好適である。Here, the cathode electrode 1 is sealed at a portion shown by hatching in the drawing so as not to be directly exposed to the plating bath 4, and the clip 2 is also disclosed in Japanese Patent Laid-Open Publication No. Sho.
It is preferred to apply a seal as disclosed in 57-207393.
ここで、カソード電極１のうちクリップ２の接点部以外
のすべてをシールした場合に、１個の接点部に対する被
メッキ基板の表面積を300〜1200cm2にするのが好まし
い。Here, when all of the cathode electrode 1 except the contact portion of the clip 2 is sealed, it is preferable that the surface area of the substrate to be plated for one contact portion is 300 to 1200 cm 2 .
その理由について述べる。本発明者の研究によれば、接
点１個あたりの被メッキ基板の表面積Ｓ（dm2）は次式
で規定される。The reason will be described. According to the research by the present inventor, the surface area S (dm 2 ) of the substrate to be plated per contact is defined by the following equation.
ここで、t:基板の導電体の厚さ（cm） σ：基板の導電体の比抵抗（Ωcm） Vmin,Vmax:電圧の単位（Ｖ）をもつ係数であり、本発明
者によれば、 Vmin＝0.0023（Ｖ） Vmax＝0.0093（Ｖ） の値をとることが判った。 Where, t: thickness of conductor of substrate (cm) σ: specific resistance of conductor of substrate (Ωcm) Vmin, Vmax: Coefficients having a unit of voltage (V), and the present inventor has found that Vmin = 0.0023 (V) and Vmax = 0.0093 (V).
以下に示す実施例および比較例を通じて、ｔ＝160μm,
σ＝2.75×10-6Ωcm, としたとき、表面積Ｓは ３＜Ｓ＜12（dm2） となる。Throughout the following examples and comparative examples, t = 160 μm,
σ ＝ 2.75 × 10 -6 Ωcm, Then, the surface area S is 3 <S <12 (dm 2 ).
なお、電流密度 を4.5A/dm2を越えて大きくすると、電着の均一性が低下
するので、均一なメッキを行うために接点あたりの表面
積を大きくすることができなくなる。The current density If it exceeds 4.5 A / dm 2 , the uniformity of electrodeposition will be deteriorated, so that the surface area per contact cannot be increased for uniform plating.
１個の接点部の負担する被メッキ基板３の表面積が より大きくすると、膜厚のばらつきが大きくなり、他方 より小さくしても、膜厚の分布の均一性は余り変わらな
い。The surface area of the plated substrate 3 that one contact part bears is The larger the value, the greater the variation in the film thickness. Even if it is made smaller, the uniformity of the film thickness distribution does not change much.
なお、 の値は、通常のメッキの陰極電流密度（4,5A/dm2近傍）
とするのが好適である。In addition, The value of is the cathode current density of normal plating (near 4,5A / dm 2 )
Is preferred.
を余り高くしていくとメッキの均一性が損われていく。
また の値はＳと反比例関係にあるから、１個の接点あたりの
表面積を大きくして、すなわち接点数を減らして、装置
の簡素化を図るためにも、 の値を余り大きくしないことが望ましい。 If it is set too high, the uniformity of plating will be impaired.
Also Since the value of is inversely proportional to S, in order to increase the surface area per contact, that is, reduce the number of contacts, and to simplify the device, It is desirable that the value of is not too large.
本発明により得られた印刷回路基板は、そのパターンが
微細であり、しかも膜厚を厚くできるので、工業的に
は、抵抗値の小さい小型コイル、高密度コネクター、高
密度配線などを構成するのに特に好適である。Since the printed circuit board obtained by the present invention has a fine pattern and can be made thicker, it is industrially used to form a small coil having a small resistance value, a high-density connector, a high-density wiring, or the like. Is particularly suitable for.
以下に本発明の態様を一層明確にするために、実施例を
挙げて説明するが、本発明は以下の実施例に限定される
ものではなく、種々の変形が可能である。EXAMPLES In order to further clarify the aspects of the present invention, examples will be described below, but the present invention is not limited to the following examples, and various modifications can be made.
実施例１〜３ 膜厚ｔ＝160μｍのアルミニウム薄板（σ＝2.75×10-6
Ωcm）上に、イーストマンコダック社製ネガ型レジスト
「マイクロレジスト747−110cSt」を乾燥後、膜厚が５
μｍになるように塗布し、ついでプリベークしてから、
回路パターンマスクを通して高圧水銀ランプで露光し、
専用の現像液およびリンス液を用いて現像した。次に、
ポストベークして、回路部以外の部分にレジストを形成
した。Examples 1 to 3 Aluminum thin plate with film thickness t = 160 μm (σ = 2.75 × 10 −6
Ωcm), a negative resist "Microresist 747-110cSt" manufactured by Eastman Kodak Co., Ltd. was dried to give a film thickness of 5
Apply so that it becomes μm, then pre-bake,
Exposing with a high pressure mercury lamp through a circuit pattern mask,
Development was performed using a dedicated developer and rinse solution. next,
Post-baking was performed to form a resist on the portion other than the circuit portion.
次いで、メッキ液としてハーショウ村田社製ピロリン酸
銅メッキ液を用いた。メッキに使用した電極は、被メッ
キ基板との接触点以外はかかる絶縁性シリコーンにより
コーティングがなされていて40cm×50cmの平面状の基板
を接点数４点、つまり接点１個当り1000cm2として固定
した。メッキ電源からは耐メッキ液性のある絶縁被膜を
持つ電線を介してカソード電極１に給電した。この電極
を用いて電流密度 が、4.5A/dm2となるようにメッキ用定電流電源を調節
し、25枚の平面状印刷回路基板を形成した。その結果、
同一基板内での膜厚をランダムに30点測定したところ、
平均膜厚81.7μｍに対して、膜厚のばらつきは2.0μｍ
であった。また、各基板に対して同じ位置（たとえば基
板端から2cm×2cmの位置）である所を20点決め、それら
位置における各実測値を20個得、その平均値を当該基板
の膜厚となし、このような基板25枚についての平均膜厚
およびばらつきを算出したところ、平均の膜厚は81.3μ
ｍで、膜厚のばらつきは0.5μｍであった。Next, a copper pyrophosphate plating solution manufactured by Hersho Murata Co., Ltd. was used as a plating solution. The electrodes used for plating were coated with such insulating silicone except for the contact points with the substrate to be plated, and a 40 cm × 50 cm flat substrate was fixed with 4 points of contact points, that is, 1000 cm 2 per contact point. . Power was supplied from the plating power source to the cathode electrode 1 through an electric wire having an insulating coating having resistance to the plating solution. Current density using this electrode , The plating constant current power source was adjusted to be 4.5 A / dm 2 to form 25 planar printed circuit boards. as a result,
When the film thickness was randomly measured at 30 points in the same substrate,
The average film thickness is 81.7 μm, but the film thickness variation is 2.0 μm
Met. In addition, 20 points at the same position (for example, 2 cm x 2 cm from the edge of the substrate) are determined for each substrate, 20 measured values at those positions are obtained, and the average value is used as the film thickness of the substrate. The average film thickness and variation of 25 such substrates were calculated to be 81.3μ.
The thickness variation was 0.5 μm.
同様の方法で得た実施例２および３のデータを実施例１
と共に第１表に示す。The data of Examples 2 and 3 obtained by the same method are used in Example 1.
The results are shown in Table 1.
比較例１〜３ 60cm×50cmの平面状の基板に対して実施例１と同様の電
解メッキ処理を行ったが、ここでは、接点の個数を４個
とし、従って、接点１個の負担する基板面積を1500cm2
となし、25枚の平面状印刷回路基板を形成した。比較例
３は、接点部分をメッキ浴に対してシールしない場合で
あり、その他は、上述した比較例１と同様の電解メッキ
処理を行い、その場合の接点の個数を種々に変えた。そ
の結果は次の第２表の通りであり、実施例１〜３に比べ
て、膜の膜厚分布が均一でないことがわかる。 Comparative Examples 1 to 3 A flat plate substrate of 60 cm × 50 cm was subjected to the same electrolytic plating treatment as in Example 1, but in this case, the number of contacts is four, and therefore one substrate bears one contact. Area 1500 cm 2
Then, 25 flat printed circuit boards were formed. Comparative Example 3 is a case where the contact portion is not sealed with the plating bath, and otherwise the same electrolytic plating treatment as in Comparative Example 1 described above was performed, and the number of contacts in that case was variously changed. The results are shown in Table 2 below, which shows that the film thickness distribution of the film is not uniform as compared with Examples 1 to 3.
なお、上記各種実施例１〜３および比較例１〜３におけ
るメッキ膜厚の測定は、得られた基板を金型により切断
して1cm×1cmの試料片を形成し、その試料片の重量を測
定して算出した。 The measurement of the plating film thickness in each of the various Examples 1 to 3 and Comparative Examples 1 to 3 was performed by cutting the obtained substrate with a mold to form a 1 cm x 1 cm sample piece, and measuring the weight of the sample piece. It was measured and calculated.
［発明の効果］ 以上から明らかなように、本発明によれば、平面状金属
基板に対するメッキ膜厚の分布を均一にでき、基板面積
に見合った個数の接点をあらかじめカソード電極に設け
ておけば、平面状金属基板が大版であっても、そのメッ
キ膜厚の分布を均一にでき、平面状印刷回路基板を歩留
りよく量産するのに好適である。しかも、その印刷回路
が微細パターンを含んでいても、メッキ抵抗の分布は均
一になるので、再現性よくメッキ処理を行うことができ
る。[Advantages of the Invention] As is apparent from the above, according to the present invention, the distribution of the plating film thickness on the planar metal substrate can be made uniform, and if the number of contacts corresponding to the substrate area is provided in advance on the cathode electrode. Even if the planar metal substrate is a large plate, the distribution of the plating film thickness can be made uniform, which is suitable for mass-producing the planar printed circuit board with a good yield. Moreover, even if the printed circuit includes a fine pattern, the distribution of the plating resistance is uniform, so that the plating process can be performed with good reproducibility.
第１図は本発明において用いるカソード電極の一例を示
す図である。 １…カソード電極、 ２…接点部を有するクリップ、 ３…平面状金属基板、 ４…メッキ浴。FIG. 1 is a diagram showing an example of a cathode electrode used in the present invention. DESCRIPTION OF SYMBOLS 1 ... Cathode electrode, 2 ... Clip which has a contact part, 3 ... Planar metal substrate, 4 ... Plating bath.
Claims (1)
成後電解メッキにより回路パターンの導体膜を付着させ
て平面状金属基板に回路パターン状導電膜が付着したも
のを製造するにあたり、前記平面状金属基板にメッキ電
流を通電するための電極は、前記平面状金属基板と電気
的に接続される接点を有し、その接点の個数を、次式で
決まる前記平面状金属基板の面積Ｓ（dm2） ただし、 t:前記平面状金属基板の厚み（cm） σ：前記平面状金属基板の導電体の比抵抗（Ωcm） あたりに１個ずつ設け、前記電極のうち前記接点の部分
以外をシール材によりメッキ浴に対してシールし、前記
接点を前記平面状金属基板に電気的に接続した状態で前
記電極に取り付けた前記平面状金属基板を前記メッキ浴
に浸漬して電解メッキを行うことを特徴とする平面状金
属基板への回路パターン状導電膜形成方法。1. A flat metal substrate having a circuit pattern conductive film adhered thereto by forming a resist pattern on a flat metal substrate and then depositing a conductive film of a circuit pattern by electrolytic plating. The electrode for supplying a plating current to the metal substrate has contacts electrically connected to the planar metal substrate, and the number of the contacts is determined by the area S (dm 2 ) Where t: thickness of the planar metal substrate (cm) σ: specific resistance of the conductor of the planar metal substrate (Ωcm) One of the electrodes is attached to each of the electrodes, a portion other than the contact portion of the electrode is sealed against a plating bath with a sealing material, and the contact is attached to the electrode in a state of being electrically connected to the planar metal substrate. A method for forming a circuit pattern conductive film on a flat metal substrate, which comprises immersing the flat metal substrate in the plating bath for electrolytic plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22483685A JPH0732300B2 (en) | 1985-10-11 | 1985-10-11 | Method for forming a circuit pattern conductive film on a flat metal substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22483685A JPH0732300B2 (en) | 1985-10-11 | 1985-10-11 | Method for forming a circuit pattern conductive film on a flat metal substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6285487A JPS6285487A (en) | 1987-04-18 |
| JPH0732300B2 true JPH0732300B2 (en) | 1995-04-10 |
Family
ID=16819938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22483685A Expired - Lifetime JPH0732300B2 (en) | 1985-10-11 | 1985-10-11 | Method for forming a circuit pattern conductive film on a flat metal substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732300B2 (en) |
-
1985
- 1985-10-11 JP JP22483685A patent/JPH0732300B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6285487A (en) | 1987-04-18 |
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