JPH0732363B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and in particular, in a semiconductor integrated circuit having a function of observing a node at a predetermined position of a logic circuit, a region used for wiring or the like necessary for observing the node. Is intended to be reduced.

[0002]

2. Description of the Related Art Conventionally, for example, FPGA (Field Prog
In the case of highly versatile semiconductor integrated circuits where users can design and wire their own logic circuits according to usage conditions, such as a rammable gate array) In order to guarantee proper operation, manufacturers need to perform tests assuming many usage situations, but because it is not possible to perform sufficient tests with external pins that are usually easy, internal node observation By providing a dedicated wiring for, the internal nodes such as the wiring in the user area are directly observed.

Therefore, in such a semiconductor integrated circuit,
It is necessary to previously prepare wiring or the like for observing the internal node, and FIG. 2 is a circuit diagram showing an example of a semiconductor integrated circuit having a function of observing the internal node in the user area.

That is, in this semiconductor integrated circuit, the wiring of the logic circuit is performed using the memory cell 1 in which data can be freely rewritten, and the memory cell 1 restrains the flip-flops 2 from each other. Storage nodes Q ₁ , Q ₀
Can store 1-bit information.

Of the two storage nodes Q ₁ and Q ₀ , one storage node Q ₁ is connected to the bit line B via an NMOS transistor (N-channel MOS transistor) N ₁ and the gate of the NMOS transistor N ₁ is connected. Are connected to the word line W.

The other storage node Q ₀ is connected to the gate of an NMOS transistor N ₂ forming a logic circuit provided in the user area. Accordingly, the NMOS transistor N ₂ is turned on or off according to the information in the storage node Q ₀ is stored, also, information stored in the storage node Q ₀ is stored in the storage node Q ₁ Since the information is the inverted information and the state of the storage node Q ₁ can be freely changed by appropriately controlling the word line W and the bit line B by a word line driver or a bit line driver (not shown), The state of the logic circuit including the NMOS transistor N ₂ can be freely set by the user, and a desired logic circuit can be configured.

In order for such a logic circuit to operate normally, the NMOS transistor N ₂ should be accurately connected between the input side L _IN and the output side L _OUT of the individual NMOS transistors N ₂ constituting the logic circuit. It is indispensable that ₂ is conductive when turned on and disconnected when turned off.

Therefore, in order to confirm whether or not the NMOS transistor N ₂ is operating normally, the output side L _{OUT is connected} to the bit line B for confirming the internal node via the NMOS transistor N ₃ as a pass transistor. as well as connect to _t, the structure of connecting the gate of the NMOS transistor N ₃ to a word line W _t of the internal node for verification, are provided for each key point in the logic circuit.

During the test, the word line W _t is raised to transfer the potential of the output side L _OUT to the bit line B _t ,
The potential of the bit line B _t is measured by a sense amplifier and output side L
Recognize the potential of _OUT , and based on the recognized potential,
It was confirmed whether the NMOS transistor N ₂ was operating normally.

[0010]

However, in the conventional configuration as shown in FIG. 2, the word line W and the bit line W used for writing information to the memory cell 1 and reading information from the memory cell 1 are used. Separately from B, the word line W _t and the bit line B for confirming the internal node of the logic circuit
_Since it is necessary to wire _t , the wiring area in the integrated circuit becomes large, which is one of the factors that hinder high integration.

The present invention has been made by paying attention to the unsolved problem of the conventional technique, and a semiconductor integrated circuit having a function of directly confirming an internal node is provided.
The objective is to achieve this while keeping the increase in the wiring area low.

[0012]

In order to achieve the above object, the present invention has a structure in which a storage node of a storage cell is connected to a bit line through a switching transistor and a gate of the switching transistor is connected to a word line. In the semiconductor integrated circuit having: a source / drain, a pass transistor whose one side is connected to an arbitrary node, and the word line and the gate of the switching transistor are separated from each other when the internal node observation mode is selected, and the word line and the A word line conduction state switching means for conducting between the gate of the pass transistor and the bit line and the switching transistor when the internal node observation mode is selected, and the other of the bit line and the source / drain of the pass transistor. Bit line is not connected And means, the provided.

[0013]

When the internal node observation mode is not selected, the word line conduction state switching means and the bit line conduction state switching means do not perform a predetermined operation, so that the word line and the gate of the switching transistor are in a conduction state. The bit line and the switching transistor are in a conductive state.

Therefore, by appropriately controlling the word line and the bit line, information is written in the memory cell or information is read from the memory cell. And
When the internal node observation mode is selected, the word line conduction state switching means disconnects the word line from the gate of the switching transistor, and also establishes conduction between the word line and the gate of the pass transistor. The line conduction state switching means disconnects the bit line from the switching transistor and electrically connects the bit line to the other of the source and drain of the pass transistor.

In this state, since the potential of the word line is supplied to the gate of the pass transistor, the pass transistor is turned on or off by controlling the word line, and the bit line and the source / drain of the pass transistor are controlled. Since the other is conductive, if the pass transistor is on, the potential of any node connected to one of the source and drain of the pass transistor is transferred to the bit line via the pass transistor.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. In addition, the same reference numerals are given to the same parts as those in the configuration of FIG. 2 described in the above-mentioned conventional technique, and the duplicated description thereof will be omitted.

First, the structure will be described. In this embodiment,
A first switching circuit 3 is provided between the memory cell 1 and the word line W, and a second switching circuit 4 is provided between the memory cell 1 and the bit line B.

The first switching circuit 3 responds to the potential of the mode selection line S which rises when the internal node observation mode is selected.
The word line W, a circuit for conducting either one of the gates of the gate or the NMOS transistor N ₃ of the NMOS transistors N _1, NMOS transistor N ₄ which is interposed between the gate and the word line W of the NMOS transistor N ₁ And the gate of the NMOS transistor N ₃ and the word line W which are arranged in parallel with the NMOS transistor N _4.
And an NMOS transistor N ₅ interposed therebetween.

The potential of the mode selection line S changes to NMO.
It is supplied to the gate of the S transistor N ₄ through the inverter 5, and is directly supplied to the gate of the NMOS transistor N ₅ .

On the other hand, the second switching circuit 4 is a circuit for conducting the bit line B to either the NMOS transistor N ₁ or the NMOS transistor N ₃ according to the potential of the mode selection line S. An NMOS transistor N interposed between the transistor N ₁ and the bit line B
_6, and an NMOS transistor N ₇ interposed between the NMOS transistors N ₆ are arranged in parallel and an NMOS transistor N ₃ and the bit lines B.

Then, the potential of the mode selection line S changes to NMO.
It is supplied to the gate of the S transistor N ₆ through the inverter 6, and is directly supplied to the gate of the NMOS transistor N ₇ .

Next, the operation of this embodiment will be described. In the normal mode in which information is written in the memory cell 1 or information is read from the memory cell 1, the potential of the mode selection line S is kept at a low level.

Then, the potential of the mode selection line S is supplied through the inverter 5 or 6 to the NMOS transistor N.
_{Although 4} and N ₆ are turned on, the NMOS transistors N ₅ and N ₇ to which the potential of the mode selection line S is directly supplied are turned off. Therefore, between the word line W and the gate of the NMOS transistor N ₁ and the bit line. B and NMOS transistor N
While each between ₁ becomes conductive, the word line W
And the gate of the NMOS transistor N ₃ and the bit line B and the NMOS transistor N ₃ are disconnected from each other.

Therefore, since the NMOS transistor N ₁ is turned on or off according to the potential of the word line W, the memory cell is controlled by appropriately controlling the word line W and the bit line B as in a normal static RAM. Information is written to 1 or information is read from the memory cell 1.

When the potential of the storage node Q ₀ of the storage cell 1 is at a high level, the NMOS transistor N ₂ is turned on so that its input side L _IN and output side L _OUT become conductive, and the storage node If the potential of Q ₀ is low level, N
The MOS transistor N ₂ is turned off, and its input side L
_{Since the IN} and the output side L _OUT are separated, the memory cell 1
By appropriately rewriting the information stored in, the connection state of the wiring in the logic circuit is determined, and the desired logic circuit is configured.

On the other hand, when the internal node observation mode for checking whether or not the input side L _IN and the output side L _OUT are accurately connected or disconnected by turning on or off the NMOS transistor N ₂ is selected. Since the selection line S rises, the NMOS transistors N ₅ and N _{7 to} which the potential of the mode selection line S is directly supplied are turned on, and the potential of the mode selection line S is supplied via the inverter 5 or 6. The transistors N ₄ and N ₆ are turned off.

Then, the word line W and the gate of the NMOS transistor N ₃ and the bit line B and the NMOS transistor N ₃ are brought into conduction, while the word line W and the gate of the NMOS transistor N ₁ are brought into conduction. And the bit line B and the NMOS transistor N ₁ are separated from each other.

Therefore, although the memory cell 1 is separated from the word line W and the bit line B, the memory nodes Q ₁ and Q ₀ are locked to each other while the flip-flop 2 is powered on. In addition, since the stable state is maintained, the information stored in the memory cell 1 is never erased.

Therefore, the NMOS transistor N ₂ can hold the ON state or the OFF state according to the information stored in the memory cell 1. Since the NMOS transistor N ₃ is turned on or off according to the potential of the word line W, the output side L of the NMOS transistor N ₂ is
_{The OUT} node can be transferred to the bit line B by appropriately controlling the potential of the word line W.

That is, with the configuration of this embodiment, the internal node of the logic circuit can be read by using the word line W and the bit line B used for accessing the memory cell 1.

Therefore, unlike the prior art, it is not necessary to wire the word line and the bit line separately from the word line W and the bit line B, and the mode selection line S is wired and the first
It suffices to make the necessary transistors in the switching circuit 3 and the second switching circuit 4.

Since the mode selection line S is common to all the switching circuits (the first switching circuit 3 and the second switching circuit 4) built in this semiconductor integrated circuit, one type of wiring is used. However, since the area occupied by the transistors in the integrated circuit is much smaller than the area occupied by the wiring, the wiring required for observing the internal node is eventually adopted by adopting the configuration of this embodiment. The area used for etc. is reduced and the degree of integration is improved.

Since access to the memory cell 1 and reading of the internal node are not performed at the same time,
Even with the configuration of this embodiment, no particular problem occurs. Here, in this embodiment, the NMOS transistor N ₁
Corresponds to the switching transistor, the NMOS transistor N ₃ corresponds to the pass transistor, the first switching circuit 3 corresponds to the word line conduction state switching means, and the second switching circuit 4 corresponds to the bit line conduction state switching means. To do.

The configuration of the switching circuits 3 and 4 is not limited to the above-mentioned embodiment, and the point is that the switching circuits 3 and 4 need only have a function of switching the conduction state. For example, the inverter 5
And 6 can also be shared.

[0035]

As described above, according to the present invention,
Since the observation of the internal node can be performed by the word line and the bit line for accessing the memory cell, the area used for the wiring necessary for observing the internal node is reduced, and the integration degree of the semiconductor integrated circuit is reduced. The effect is to improve.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1 Storage Cell 3 First Switching Circuit (Word Line Conduction State Switching Means) 4 Second Switching Circuit (Bit Line Conduction State Switching Means) 5, 6 Inverter W Word Line B Bit Line S Mode Selection Line N ₁ NMOS Transistor ( Switching transistor) N ₃ NMOS transistor (pass transistor) Q ₁ , Q ₀ Storage node

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a structure in which a storage node of a storage cell is connected to a bit line via a switching transistor and a gate of the switching transistor is connected to a word line, one of a source and a drain is an arbitrary node. Word line conduction state switching means for disconnecting the word line and the gate of the switching transistor when the internal node observation mode is selected and for electrically connecting the word line and the gate of the pass transistor. And a bit line conduction state switching means for disconnecting the bit line and the switching transistor and electrically connecting the bit line and the other of the source and drain of the pass transistor when the internal node observation mode is selected. A semiconductor integrated circuit characterized by the above.