JPH0732377B2 - Channel selection method for data broadcasting programs - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data transmission / reception circuit, and in particular, unidirectional data communication to an unspecified number of receivers by multiplexing data of a plurality of channels on one transmission line. The receiver is concerned with a channel selection method of a data broadcast program in which the receiver selects and receives the necessary channel data when necessary.

[Conventional technology]

In the conventional channel selection method for data broadcasting programs, first a channel number is added to the data for each channel on the transmitting side, and then a list of channel numbers, that is, a directory table is added to form a series of data strings.
This is sequentially repeated on the receiving side for transmission. Then, the receiving side refers to the directory table, detects the channel number, determines whether or not the received data corresponding to the channel number is necessary, and takes in the received data.

[Problems to be Solved by the Invention]

However, in the conventional channel selection method for data broadcasting programs, when the receiving side selects a new channel from the channels currently receiving data and receives that channel data, the channel number is searched after referring to the directory table. However, since the number of directory tables is increased, the search time becomes longer because the data must be received.

Also, when updating the program, the transmitting side must create a new directory table each time, which is complicated.

[Means for Solving the Problems]

In order to solve such a problem, a channel selection method of a data broadcast program according to the present invention is performed by receiving data input from a plurality of channels in parallel and receiving data at different timings for each channel. A plurality of data output circuits that output, a circuit that adds channel information to this data output, and bit multiplexing that inputs the above data and this channel information and performs bit multiplexing for each channel and outputs as serial transmission data A circuit, a clock generation circuit for supplying the transmission clock controlled by the channel information to the bit multiplexing circuit, and an output of the frequency division clock controlled by the channel information and the transmission clock. A first frequency dividing circuit for inputting to the data output circuit; The data receiving circuit that extracts the specific channel data by identifying the channel from the serial transmission data, the circuit that extracts the additional channel information from the specific channel data, and the extracted channel information. And a channel selection input to control the opening and closing of the transmission clock in 1-clock units, and the clock output of this gate circuit and the frequency-divided clock controlled based on the channel information to the data receiving circuit. It is characterized by comprising a data receiving device including a second frequency dividing circuit for inputting.

[Action]

A plurality of parallel channel data inputs are sampled by the data output circuit at different timings for each channel and input to the bit multiplexing circuit. The bit multiplexing circuit bit-multiplexes this data, adds channel information to it, and transmits it to the receiving device together with the transmission clock as serial transmission data synchronized with the transmission clock.

On the other hand, in the receiving device, a predetermined channel is identified by the data receiving circuit and the data of the channel is received. When a new channel is selected from the channels currently being received, the gate circuit controls the opening / closing of the transmission clock based on the channel selection input and the channel information currently being received. Then, the frequency of the second frequency dividing circuit is controlled by the clock whose opening / closing is controlled, and the output of this frequency dividing clock becomes the timing for selecting the desired new channel data. Therefore, the data receiving circuit receives the channel data synchronized with this timing.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a channel selection system for a data broadcast program according to the present invention. In the figure, 1 is a transmitter, 2 to 5 are data transmission circuits which receive data of channels 1 to 4 and output data at different timings, and 6 multiplexes this data output and outputs serial transmission data to the receiving side. A bit dividing circuit, 7 is a first frequency dividing circuit (4 frequency dividing circuit) for supplying pulses of different timings to the data transmitting circuit, and 8 is a first frequency dividing circuit, a bit multiplexing circuit and a receiving side. A clock generating circuit for supplying a transmission clock, 9 detects a channel information input consisting of a channel number and total channel number information and supplies this information to the clock generating circuit, the first frequency dividing circuit and the bit multiplexing circuit. It is an additional circuit.

10 is a receiving device, 11 is a data receiving circuit for identifying the channel of serial transmission data and extracting specific channel data, 12 is a clock receiving circuit for receiving the transmission clock, and 13 is a transmission clock from the channel selection input and the channel information. A gate circuit that controls the opening and closing in units of one clock, 14 is a second frequency dividing circuit (4 frequency dividing circuit) that receives the control clock output of the gate circuit 13, and 15 is channel information that extracts further channel information from the received data. Detection circuits, D _{1 to} D ₄ are data input terminals from channels 1 to 4, CHI is a channel information input terminal, CHS is a channel selection input terminal, and OUT is an output terminal of received data.

FIG. 2 is a time chart showing the principle of data multiplexing on the transmitting side and data separation on the receiving side. In the figure, A is the transmitting side, B is the receiving side, and a is the channels 1 to 1.
The serial transmission data is obtained by bit-multiplexing the parallel data of 4 into serial data, b is the transmission clock, and c is the output of the transmission clock divided by four. In the figure, the numbers 3,2,1,4 ... in the serial transmission data a are channel numbers 3,2,1,4 ...
The input data corresponding to is shown.

Next, the operation will be described based on the block diagram and time chart as described above.

When the data arrives from the data input terminal D ₁ to D _4, the data transmission circuit outputs the bit data of different timings for each channel which receives it in parallel. The parallel bit data are multiplexed by the bit multiplexing circuit 6 for each channel and output as serial data. On the other hand, the channel information adding circuit 9 detects the channel information input and outputs the information to the bit multiplexing circuit 6 via the clock generating circuit 8 and the first frequency dividing circuit 7.
Give to. As a result, the bit multiplexing circuit 6 adds the channel information to the above serial data to form serial transmission data and transmits it to the receiving device 10 in synchronization with the transmission clock. In addition, the clock generation circuit 8 and the first frequency division circuit 7
Is controlled by this channel information. Then, the output of this clock generation circuit 8, that is, the transmission clock is
In addition to controlling the bit multiplexing circuit 6, the first frequency dividing circuit 7 is also controlled, and the respective outputs divided by the first frequency dividing circuit are input to the data transmitting circuits 2-5. As a result, the data transmission circuits 2 to 5 output sampled data in synchronization with this frequency division input.

In the receiving device 10, the data receiving circuit 11 extracts and receives a specific channel data from the serial transmission data transmitted in synchronization with the transmission clock.

FIG. 2 shows that the transmission side A transmits the serial transmission data a to the reception side B in synchronization with the transmission clock b, while the reception side B transmits the serial transmission data a from the transmission clock a. Output divided by 4 by dividing b by 4
It shows that the channel data synchronized with is extracted. In this example, the data of channel 3 is extracted. By simply dividing the transmission clock and extracting the channel data based on the frequency division output like the time chart shown in FIG. 2, it is not fixed which channel data is being extracted, and the switching of the channels is also possible. Can not.

In the transmitter 1 for solving this problem, it becomes necessary to add the channel information to the serial transmission data by the channel information adding circuit 9 as described above. On the other hand, in the receiving device 10, if the specific channel data is received from this serial transmission data and the channel information added to this channel data is taken out, it is determined which channel number data is currently being received. it can.

Next, the case where the receiving apparatus 10 switches from the channel number currently receiving data to a new channel number will be described based on the time charts of FIGS. 3 to 6. As common symbols in FIGS. 3 to 6, (a) is a transmission clock, (b) is a frequency division output output from the second frequency dividing circuit 14, and (c) is a timing of serial transmission data. It is the figure which has shown. FIG. 3 shows the case where the channel number 1 is switched to the channel number 4, and the transmission clock input from the output of the gate circuit 13 to the second frequency dividing circuit 14 at this time is (4-1) = 3 clock inhibition. Switch to the new channel number 4 by doing. In the figure, the part indicated by the dotted line on the frequency division output (b) indicates the prohibited clock, and the number on the serial transmission data (e) is the data corresponding to the channel number and is the circled channel. The number indicates the channel number data being received. Figure 4 shows the case of switching from channel number 3 to channel number 1, and the total number of channels is 4.
Therefore, the transmission clock input from the gate circuit 13 to the second frequency dividing circuit 14 is switched to the new channel number 1 by inhibiting {4- (3-1)} = 2 clocks. 5 to 6 show a general case where the number of channels is set to n channels, and FIG. 5 shows a case of switching from a small channel number (hereinafter referred to as xmin) to a large channel number (hereinafter referred to as xmax). By prohibiting the transmission clock at this time (xmax-xmin),
Switch to xmax. Figure 6 shows the case of switching from xmax to xmin. Since the total number of channels is n, the transmission clock is
{N- (xmax-xmin)} xm
Switch to in.

Next, the operation of the above-mentioned channel switching will be described based on the block diagram of FIG. In the receiving device 10, the channel information contained in the channel data received after the channel identification is extracted by the channel information detection circuit 15 and then input to the gate circuit 13 and the second frequency dividing circuit 14. It The gate circuit 13 performs the above-described clock open / close control on the transmission clock output from the transmission clock reception circuit 12 based on the channel information and the channel selection input, and the second frequency dividing circuit 14
To enter. As a result, the second frequency dividing circuit 14 gives a frequency division output for selecting a new channel number to the data receiving circuit 11, and the desired new channel data is output from the output of the data receiving circuit 11.

As is clear from the above, the data transmitting side bit-multiplexes a plurality of channel data, further adds channel information, and transmits it as serial transmission data together with the transmission clock to the receiving side. On the receiving side, first, a specific channel data is received, and when the channel is switched next, the transmission clock is controlled based on the channel information contained in this channel data, and the desired channel is selected.

〔The invention's effect〕

As described above, according to the channel selection method of the data broadcasting program according to the present invention, a plurality of channel data are bit-multiplexed on the data transmission side, and further channel information is added and transmitted as serial transmission data together with the transmission clock. On the receiving side, the above channel information is extracted, the transmission clock is controlled based on this channel information, and the channel is selected, so the configuration is simple and inexpensive, and it is also necessary to create a directory table when updating the program. Instead, there is an effect that the channel can be selected promptly.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a channel selection system for a data broadcast program according to the present invention, and FIG. 2 shows data multiplexing on the transmitting side and data separation on the receiving side. A time chart showing the principle, FIGS. 3 to 4 are time charts showing an embodiment of the channel switching when the number of channels is 4 in one embodiment of the present invention, and FIGS. 5 to 6 show that the number of channels is n. It is a time chart which shows the mode of channel switching at the time. 1 ... Transmitting device, 2-5 ... Data transmitting circuit, 6 ... Bit multiplexing circuit, 7 ... First frequency dividing circuit, 8 ... Clock generating circuit, 9 ... Channel information adding circuit, 10 ... … Reception device, 11 …… Data reception circuit, 12 …… Clock reception circuit, 13 …… Gate circuit, 14 …… Second frequency divider circuit, 15 ……
Channel information detection circuit, D _{1 to} D ₄ are channel data input terminals, CHI ... Channel information input terminal, CHS ... Channel selection input terminal, OUT ... Channel data output terminal.

Claims (1)

[Claims] 1. A plurality of data output means for respectively receiving data input in parallel from a plurality of channels and outputting the data at different timings for each channel, and the plurality of data output means. Means for adding channel information to the output data, and bit multiplexing means for bit-multiplexing the channel information and the data output by the plurality of data output means for each channel and outputting as serial transmission data. A clock generating means for supplying a transmission clock controlled by the channel information to the bit multiplexing means, and a frequency division clock controlled on the basis of the channel information and the transmission clock for outputting the plurality of data. Means for supplying the first frequency dividing means to the means, and the serial Data receiving means for identifying channels from the received signal data and extracting and outputting specific channel data, means for extracting the channel information from the specific channel data, and the extracted channel information and channel selection Gate means for controlling the opening and closing of the transmission clock in 1-clock units from the input, a clock controlled to be opened and closed by the gate means, and a frequency dividing clock controlled based on the channel information are supplied to the data receiving means. A data receiving device having a second frequency dividing means for selecting a channel based on the opening / closing control of the transmission clock in the data receiving device.