JPH0732494B2 - Time axis error signal generator for information recording / reproducing apparatus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-axis correction device for a reproduction signal in an information recording / reproduction device, and in particular, it corrects a time-axis error of a color video signal reproduced from a video disc or the like. The present invention relates to a so-called time base collector time axis error generator.

[Conventional technology]

As various time axis error generators in the conventional recorded information reproducing apparatus, as described in detail in JP-A-56-84091, JP-A-56-13886, etc., a reference signal and a reproduction horizontal synchronizing signal or a reproduction color burst are used. The phase difference is sampled and held for about 1H until the next sampling timing, which is used as the time axis error signal.

[Problems to be solved by the invention]

The above-mentioned prior art does not consider generation of false sync signal due to missing of reproduced water sync signal or reproduced color burst or noise caused by occurrence of dropout of reproduced signal caused by scratches or other causes of recording medium. ,
For this reason, there is a problem in that due to these omissions and the like, a correct phase comparison with the reference signal is not performed and an erroneous large phase error may occur. When such an erroneous error occurs, the time axis correction system operates due to the erroneous error signal, and the reproduced signal causes a phase shift, so that a hue shift and a synchronization disorder occur on the reproduced image.

It is an object of the present invention to provide a means for preventing an erroneous large phase error caused by a dropout of a reproduction signal and eliminating the above-mentioned adverse effect.

[Means for solving problems]

The purpose of the above is to sample the phase difference between the reference signal and the reproduced color burst or horizontal sync signal, hold it for about 1H, and use it as the time axis error signal for the first sample and hold circuit. A second sample and hold circuit that has a sampling pulse during the period and samples and holds the output of the first sample and hold circuit, and an upper and lower limit value according to the sample and hold output level is provided around this sample and hold circuit output. Every time the output of the first sample-hold circuit goes out of the range, the sampling operation of the second sample-hold circuit is prohibited for a predetermined time, and the output of the second sample-hold circuit is sampled to be larger than the upper and lower limit values. Set the second upper and lower limits according to the hold output level. When the output level of the first sample and hold circuit is within the bell range, the output of the first sample and hold circuit is used as a time axis error signal, and when it is out of the range, it is a predetermined time, and the output of the second sample and hold circuit is timed. This is achieved by using the axis error signal.

[Action]

When the time axis correction system operates normally without being affected by dropout in the normal mode, the time axis error signal becomes a smooth signal (sinusoidal waveform synchronized with the rotation frequency). (FIG. 6 (a)) When an erroneous error is output due to dropout or the like, a steep large error occurs in the time axis error signal as shown in FIG. 6 (b). It operates to detect the occurrence of this steep error and replace it with the error immediately before the occurrence of the steep error.

Specifically, the second sample-and-hold circuit operates so as to output an output that follows the output level of the first sample-and-hold circuit with a delay of 0 to 1H. Provide two. Every time the output of the first sample and hold circuit goes out of the range of the first upper and lower limit values, a predetermined time,
It operates so as to prohibit the sampling of the second sample hold circuit. As a result, a second sample-and-hold circuit output is obtained which has little level change suddenly, has a normal smooth level change, and follows the first sample-and-hold circuit with a slight delay. The lower limit is obtained. On the other hand, the output of the first sample-and-hold circuit is smoothed by the second upper
When it is out of the range of the lower limit value, it operates as a time axis error signal for a predetermined time, and when it is in the range, it operates so that the output of the first sample hold circuit becomes a time axis error signal. As a result, the error signal of 1H or several H ago can be compared with the current error level at all times, and an erroneous and abrupt error signal due to dropout or the like is not supplied to the time axis correction system, so that there is no synchronization disturbance. Good time axis correction is possible.

Further, since the upper and lower limit levels change in accordance with the residual time axis error (DC fluctuation amount in FIG. 6A), the upper and lower limit levels can be lowered to improve the detection accuracy.

〔Example〕

A block diagram of the embodiment of the present invention is shown in FIG. In the figure
101 is a first sample and hold circuit, 102 is a second sample and hold circuit, 103 is a first upper and lower limit value setting means, 104
Is a first comparing means, and 105 is a sample and hold prohibiting means, which has a smooth level fluctuation without abrupt level fluctuations at 103 to 105, and follows the output of the first sample and hold circuit with a slight delay. The sample hold circuit output of is obtained. On the other hand, 106 is a second upper / lower limit value setting means, 107 is a second comparing means, 108 is a timing generation circuit,
Reference numeral 109 is a switch circuit, and when the output of the first sample-hold circuit is out of the range of the second upper and lower limit levels created from the output of the second sample-hold circuit, the switch circuit is switched to the first sample-hold circuit for a predetermined time. Second from output
The output of the sample and hold circuit is switched to prevent the occurrence of erroneous and sudden large errors due to dropouts.

Next, an embodiment of the present invention will be described with reference to the circuit diagram of FIG. 2 and the operation waveform chart of each part of FIG.

In FIG. 2, the sample and hold circuit 1 has a switch S ₁ ,
It is composed of a capacitor C ₁ and a buffer A _1, and S ₁ is turned on / off by the sampling pulse A, and the sampling and holding operations are repeated. The sample and hold circuit 1 corresponds to, for example, the sample and hold circuit 13 shown in FIG. 6 of JP-A-56-84091. Sample and hold circuit 1
Output B is connected to one input of the sample hold circuit 2 and the switch circuit 3. Sample and hold circuit 2
Is composed of a switch S _{1, a} capacitor C ₂ , and a buffer A ₂ . Here, S ₂ is on / off controlled by the output D of the AND gate 8 to perform the sample and hold operation. The output E of the sample hold circuit 2 is the switch circuit 3
It is connected to one input and the resistor group 4. The resistor group 4 is composed of resistors R _{1 to} R ₆ . R ₁ and
R ₆ each sample and hold circuit output 1 is connected to a considerably higher supply + V _CC and a low supply -V _CC than the level that can be taken normally. Also, set the constants such that R ₁ >> R ₂ + R ₃ and R ₆ >> R ₄ + R ₅ . The window comparator 5 consists of two comparators, the voltage level at the connection point of R ₂ and R ₃ is the upper reference voltage + V _TH1, and the voltage level at the connection point of R ₄ and R ₅ is the lower reference voltage −V. The output level of the sample hold circuit 1 is compared with _TH1 . The output F of the window comparator 5 is input to the logic circuit 6 together with the sampling pulse of the sample and hold circuit 1, and the output G of the logic circuit 6 is a retriggerable mono-multivibrator (hereinafter abbreviated as retriggerable mono-multi or mono-multi) 7 Connected to. Input pulse H of retriggerable mono-multi 7
An AND gate 8 is provided, and the sampling pulse C of the sample hold circuit 2 is input to the other gate input. This sampling pulse is sample hold circuit 1
A pulse is generated during the hold period of
The switch S ₂ of the sample and hold circuit ₂ is turned on via the gate, and the hold level of the sample and hold circuit 1 becomes a timing pulse for sample and hold. The window comparator 9 consists of two comparators,
The voltage level of the connection point of R ₁ and R ₂ of the resistor group 4 is the upper reference voltage + V _TH2 , and the voltage level of the connection point of R ₅ and R ₆ is the lower reference voltage −V _TH2 . Compared to the output. The output I of the window comparator 9 is connected to a non-triggerable mono-multi vibrator (hereinafter, abbreviated as non-triggerable mono-multi or mono-multi) 10.
The output J of the non-triggerable mono-multi 10 is connected to the switch circuit 3 and controlled so as to select and output two inputs. The output K of the switch 3 is used as a time axis error signal. In the retriggerable mono-multi 7 and the non-retriggerable mono-multi 10, a prohibition timing signal is connected to a reset terminal or the like.

Next, the circuit operation of FIG. 2 will be described with reference to FIG. The same signal waveforms in the figures are indicated by the same reference numerals. In FIG. 3, the sampling pulse A has a horizontal synchronizing period, and the output B of the sample hold circuit 1 is obtained by sampling the phase difference of this pulse from the high period reference signal and holding the sampling level in the low period. (In the past, the output B of the sample and hold circuit 1 was used as a time axis error signal.) The sample and hold circuit 2 is provided to sample and hold the level of the hold period of the sample and hold circuit 1, and is normally AND. The sampling timing is determined by the sampling pulse C via the gate 8. That is, when the other input of the AND gate 8 is high, the sampling pulse C passes through the AND gate 8 and becomes D. Therefore, the sampling pulse C has a horizontal synchronizing cycle like the sampling pulse A, and generates a pulse during the low period of the sampling pulse A. Sample and hold circuit 2
The output E of the signal changes its level later than the output B of the sample hold circuit 1 by the amount of deviation of the generation timing of the sampling pulses A and B. Output E of sample hold circuit 2
Is connected to the resistor group 4, and from the connection point of each resistor, the output of the sample hold circuit 2 is DC
A level-shifted voltage is obtained. From the upper side of the resistor group, set this level to + V _TH2 (connection point of R ₁ and R ₂ ) and + V _TH1 (R ₂ and R ₃
Connection point), −V _TH1 (connection point between R ₄ and R ₅ ) and −V _TH2 (R ₅
And the connection point of R ₆ ). On the other hand, the comparator 5 is + V
_TH1 and -V _TH1 are used as reference voltages to compare the level with the output B of the sample and hold circuit 1. When the output B of the sample and hold circuit 1 is outside the reference voltage range, it is low level, and when it is within the reference voltage range, it is high level. Is output F. Comparator 5
Of the output F of the sampling pulse A has a logic circuit 6
The sampling pulse A passes and is output only when the comparator output is at a low level. The retriggerable mono-multi 8 is triggered by the rising edge of the output G of the logic circuit 6 and outputs a low-level pulse H for a predetermined time. The output H of the retriggerable monomulti 7 is ANDed with the sampling pulse C by the AND circuit 8 to control the switch S ₂ of the sample hold circuit 2. Therefore, while the output of the retriggerable mono-multi 7 is at the low level, the AND gate 8 prohibits the sampling pulse C from passing and becomes the AND gate output D. Therefore, the output of the sample and hold circuit 2 is
The output H of the retriggerable mono-multi 7 is in the low level period,
The level before the main output H becomes low level is the hold output E.

On the other hand, the window comparator 9 outputs a low level when the output B of the sample hold circuit 1 is out of the reference voltage range, and a high level when the output B of the sample hold circuit 1 is within the reference voltage, using + V _TH2 and -V _TH2 as reference voltages. I will. That is, the window comparator 9 detects that the difference between the time axis error signal of 1H before and the time axis error to be newly sampled becomes a certain value or more. At the trailing edge of this output I, the non-retriggerable monomulti 10 is triggered and outputs a high-level pulse J for a predetermined time. The switch circuit 3 is provided to select the outputs B and E of the sample and hold circuits 1 and 2, and is controlled by the output J of the non-retriggerable monomulti 10 and when the J is at a low level, the output B of the sample and hold circuit 1 is output. However, when J is high level, the sample and hold circuit 2
Output E is selected and output. The output K of the switch circuit 3 is added to the time axis correction system as a time axis error signal. Output B of sample hold circuit 1 is reference voltage + V
When it goes out of the range of _TH2 to -V _TH2 , the output E of the sample hold circuit 2 which is the error voltage level immediately before that becomes the time axis error signal. In this way, when an erroneous and sudden large error occurs due to dropout or the like, the error signal of 1H or several H before is replaced. In addition, the prohibition signal causes the output of the switch circuit 3 to select the sample hold circuit 1 when a rapid time axis error occurs which is generated at the time of a still jump as shown in the conventional example. And is connected to the reset terminals of the monomultis 7 and 10. As a result, the output H of the retriggerable mono-multi 7 is kept at a high level and the output J of the non-retriggerable mono-multi 10 is kept at a low level while the inhibition signal is coming.

Next, in order to describe the necessity of the window comparator 5, a description will be added with reference to the circuit diagram of FIG. 4 and the waveform chart of each part of FIG. Here, FIG. 4 is a diagram in which the output J of the non-retriggerable monomulti 10 is inverted by the inverter 20 as one input of the AND gate without the window comparator 5, the logic circuit 6 and the retriggerable monomulti 7 in FIG. To use.

Other than that, the same parts as those in FIG. 2 have the same functions. Therefore, the main difference between the circuit diagrams of FIGS. 2 and 4 is whether the additional blocking of the sampling pulse C is performed by the H output or the J output.

The waveforms of the respective parts when the output B of the sample hold circuit 1 takes the locus shown in FIG. 5 are shown. In this example, even when a relatively large time axis error occurred suddenly due to dropout (time t _{1 in} Fig. 4), it did not reach outside the range of + V _TH2 , -V _TH2 produced from the error level 1H ago. It is about thinking about the case. In such a case, the erroneous error signal causes the time axis correction system to operate. Therefore, when the sample-hold circuit 1 samples a time-axis error at a regular timing that is not affected by dropout at the next sampling time (time t ₂ ), the time-axis correction system moves due to the erroneous error. In many cases, a time axis error on the opposite side that cancels it occurs. (Waveform in FIG. 5) The + V _TH2 and -V _TH2 waveforms in FIG. 5 show the upper and lower limit values of the window comparator 9. Here, the + B _TH2 and -V _TH2 waveforms are respectively + V at the center of the output B waveform of the sample hold circuit 1. _TH2 , -V _{TH2 is} shifted and delayed by about 1 / 2H. Here, it can be seen that the B waveform is out of the range of −V _TH2 (hatched portion) at time t ₂ . Therefore, the window comparator output I becomes a low level output from the time t ₂ , and the output J of the non-retriggerable monomulti 10 outputs a high level for a certain period of time. Therefore, the output K of the switch circuit 3 becomes the output E (not shown) of the sample and hold circuit ₂ from the time t _2, so that an erroneous error is maintained. As a result, since the erroneous time axis error due to dropout or the like which was originally 1H is added to the time axis correction system continuously for 2H, the adverse effect of the addition of this circuit becomes large. In order to eliminate such an adverse effect, the window comparator 5 shown in FIG. 2 is provided in the present invention. In the circuit diagram shown in FIG. 2, the reference voltage of the window comparator 5+
The range of V _TH1 , -V _TH1 is set sufficiently smaller than + V _TH2 , -V _TH2 . Therefore, with respect to the output B of the sample hold circuit 1 at time t ₁ in FIG. 5, the output of the window comparator 5 becomes low level and the sample hold circuit 2 at time t ₃
Is prohibited and the voltage level of the reference value + V _TH2 , -V _TH2 of the window comparator 9 does not change and the voltage before t ₃ is held. Therefore, the state change of the output of the window comparator 9 at time t ₂ is also prevented, and the output of the switch circuit 3 continues to be in the state in which the output of the sample hold circuit 1 is selected, and the above adverse effect is eliminated. Note that ± V _TH1 may be selected as an appropriate value by the subsequent time axis correction system.

As described above, according to the present embodiment, it is possible to accurately detect an erroneous large error due to dropout or the like (± V _TH2 and ± V _TH1 follow the sample hold circuit 1). When a large error occurs due to the detection result, it can be replaced with the error signal of 1H (or several H) closest to the original error level. This has the effect of preventing the disturbance of

In addition, for residual time axis error, the window comparator
Since the reference voltages of 5 and 9 change following each other, the reference voltage level can be reduced to detect a steep change in the error level, and a better time-axis error signal can be obtained.

In FIG. 2, the output pulse widths of the monomultis 7 and 10 are each set to a predetermined time, but it is clear that this predetermined time may be set according to the expected continuous dropout amount.

〔The invention's effect〕

According to the present invention, an erroneous error signal generated due to a dropout of a reproduction signal or the like can be replaced with a previous error signal level closest to the original error signal level and output as a time axis error signal. Since the disturbance of the time axis correction system due to etc. can be removed,
There is an effect that a good reproduction signal with little disturbance of the time axis can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, FIG. 3 is an operation waveform chart of each part shown in FIG. 2, and FIG. 4 is from FIG. FIG. 5 is a circuit diagram considered when the window comparator 5 and the like are deleted, FIG. 5 is an operation waveform diagram of each part shown in FIG. 4, and FIG. 6 is a diagram showing an example of a time axis error signal. 1,2,101,102 …… Sample hold circuit, 3,109 …… Switch circuit, 5,6 …… Wind comparator, 7 …… Retriggerable mono multi, 10 …… Non-retriggerable mono multi.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Junichi Ikoma 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Yokohama factory of Hitachi Ltd. (56) Reference JP-A-63-316982 (JP, A) JP 61-79384 (JP, A) Actual development 59-180577 (JP, U) Japanese Patent Sho 56-26184 (JP, B2)

Claims (1)

[Claims] 1. A phase difference between a reference signal and a burst signal of a reproduced color video signal or a horizontal synchronizing signal is detected, a voltage level corresponding to the phase difference is sample-held for 1H period, and the sample-hold operation is repeated every 1H. A first sample-and-hold circuit, a second sample-and-hold circuit that samples the output of the first sample-and-hold circuit after the first sample-and-hold circuit finishes sampling and before the next sampling is started; A first upper and lower limit level setting means for setting an upper limit and a lower limit value according to the output level of the second sample and hold circuit, and a second level higher than the first upper and lower limit level setting means. Centering on the output level of the sample and hold circuit of the second upper and lower limit value for setting the upper limit value and the lower limit value according to this output level. The output level of the bell setting means, the output level of the first sample and hold circuit and the output level of the first upper and lower limit level setting means are compared, and the output of the first sample and hold circuit sets the first upper and lower limit level. A prohibiting means for prohibiting the sampling of the second sample-hold circuit for a predetermined time each time the output of the means is out of the range, and a switch circuit having two inputs of the outputs of the first and second sample-hold circuits. When the output of the first sample and hold circuit is out of the range of the output of the second upper and lower limit level setting means, the switch circuit selectively outputs the output of the second sample and hold circuit, The time axis error signal generation of the information recording / reproducing apparatus is characterized in that the output of the first sample hold circuit is selectively output as a time axis error signal when apparatus.