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JPH0732534B2 - Rectifier load abnormality detection method - Google Patents
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JPH0732534B2 - Rectifier load abnormality detection method - Google Patents

Rectifier load abnormality detection method

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Publication number
JPH0732534B2
JPH0732534B2 JP61239495A JP23949586A JPH0732534B2 JP H0732534 B2 JPH0732534 B2 JP H0732534B2 JP 61239495 A JP61239495 A JP 61239495A JP 23949586 A JP23949586 A JP 23949586A JP H0732534 B2 JPH0732534 B2 JP H0732534B2
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JP
Japan
Prior art keywords
load
current
rectifier
voltage
abnormality detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP61239495A
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Japanese (ja)
Other versions
JPS6395812A (en
Inventor
一成 湯浅
Original Assignee
川崎製鉄株式会社
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Priority to JP61239495A priority Critical patent/JPH0732534B2/en
Publication of JPS6395812A publication Critical patent/JPS6395812A/en
Publication of JPH0732534B2 publication Critical patent/JPH0732534B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Rectifiers (AREA)
  • Control Of Voltage And Current In General (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、整流器の負荷異常検出方法に関し、特に負
荷短絡と負荷開放の両異常を検知して負荷の事故を防止
できるものである。
Description: TECHNICAL FIELD The present invention relates to a load abnormality detection method for a rectifier, and more particularly to a load abnormality detection method that detects both load short-circuit and load open abnormalities.

〔従来の技術〕[Conventional technology]

例えば、電気分解或いは鋼帯の電気めっきその他、直流
電力を利用する多くの分野で、直流電源装置として交流
電力を直流電力に変換するための整流器が、一般的に広
く使われている。
For example, a rectifier for converting AC power into DC power is generally widely used as a DC power supply device in many fields utilizing DC power such as electrolysis or electroplating of steel strips.

第4図は、その代表例としての六相半波整流式半導体形
整流器の基本的な構成を示すものであり、過電流遮断器
1を介し入力された三相交流が、サイリスタ2を有する
開閉器S,三相交流を六相交流に変換する例えば2重Y結
線された整流器用変圧器3,半波整流用ダイオード4を経
て半波整流され、例えば電気メッキであれば10000アン
ペア(A)程度の直流大電流としてメッキ装置に供給さ
れる。また、この整流器には、直流電力を供給すべき負
荷に短絡事故が発生したとき、これをいち早く検知して
事故拡大を防ぐために、負荷異常検出回路が設けられて
いる。すなわち、前記整流器用変圧器3の一次側には電
流検出器5が、二次側には電圧検出器6がそれぞれ介挿
されていて、前者で検知された電流検出信号SIと後者で
検知された電圧検出信号SVとが、演算器7に入力され
る。そして、この演算器7には、更に図示しない負荷短
絡異常検出レート設定装置で予め設定された負荷異常検
出の上限電圧Vaと下限電流Iaとが入力されている。
FIG. 4 shows a basic configuration of a six-phase half-wave rectifying semiconductor type rectifier as a typical example, in which a three-phase alternating current input through an overcurrent breaker 1 has a thyristor 2. Device S, for converting a three-phase alternating current into a six-phase alternating current, for example, a double Y-connected rectifier transformer 3, a half-wave rectifying diode 4, and half-wave rectified. For example, if electroplating, 10,000 amperes (A) It is supplied to the plating equipment as a direct current of a high level. In addition, this rectifier is provided with a load abnormality detection circuit in order to detect a short circuit accident in a load to which direct current power should be supplied and to prevent the accident from spreading in a short time. That is, a current detector 5 is inserted in the primary side of the rectifier transformer 3 and a voltage detector 6 is inserted in the secondary side, and the current detection signal SI detected by the former and the current detection signal SI detected by the latter are inserted. The detected voltage detection signal SV is input to the calculator 7. Then, the upper limit voltage Va and the lower limit current Ia for load abnormality detection, which are preset by a load short-circuit abnormality detection rate setting device (not shown), are input to the calculator 7.

第5図は上記整流器における負荷異常検出回路の動作特
性を示すものであり、図中、In,Vnはそれぞれ定格電流
値と定格電圧値を表し、鎖線L1は整流器運転における最
低電圧−電流特性を表している。
FIG. 5 shows the operation characteristics of the load abnormality detection circuit in the rectifier. In the figure, In and Vn represent the rated current value and the rated voltage value, respectively, and the chain line L 1 represents the minimum voltage-current characteristic in the rectifier operation. Is represented.

いまメッキ装置等の負荷側に短絡事故(外部短絡)が発
生すると、電流が急激に増大する。その結果、整流器か
ら出力される電圧SV,電流SIは前記の最低電圧−電流特
性の範囲をはずれて、例えばVaボルトと言う低い電圧で
Iaアンペア以上の大電流が出力されることとなる。そこ
で、負荷異常の判定条件として、負荷異常検知の上限電
圧Vaと負荷異常検出の下限電流Iaとを前以って設定して
おき、演算器7でそれらの判定条件値と実測された検出
電圧値SVおよび検出電流値SIとを絶えず比較し、SI>Ia
で、かつSV<Vaのとき負荷異常有りと判断して、サイリ
スタ2に対して消弧信号GOFFを出力する。
When a short-circuit accident (external short-circuit) occurs on the load side of a plating device or the like, the current rapidly increases. As a result, the voltage SV and the current SI output from the rectifier are out of the range of the above-mentioned minimum voltage-current characteristic, and at a low voltage such as Va volt, for example.
A large current of Ia amperes or more will be output. Therefore, as the load abnormality determination condition, the upper limit voltage Va for load abnormality detection and the lower limit current Ia for load abnormality detection are set in advance, and the determination condition values and the detected voltage measured by the calculator 7 are set in advance. The value SV and the detected current value SI are constantly compared, and SI> Ia
When SV <Va, it is determined that there is a load abnormality, and the arc extinguishing signal G OFF is output to the thyristor 2.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしながら、このような従来の整流器(例えば、特開
昭58-154322号公報)の負荷異常検出方法にあっては、
上記短絡異常時の出力電圧Vaの上限は整流器の内部短絡
電圧で規制されてしまう。すると、負荷異常検出下限電
流Iaも、整流器運転における最低電圧−電流特性に従い
必然的に規定される(第5図参照)。
However, in the load abnormality detection method of such a conventional rectifier (for example, Japanese Patent Laid-Open No. 58-154322),
The upper limit of the output voltage Va when the short circuit is abnormal is regulated by the internal short circuit voltage of the rectifier. Then, the load abnormality detection lower limit current Ia is also inevitably specified according to the minimum voltage-current characteristic in the rectifier operation (see FIG. 5).

そのため、(1)負荷電流SIが、整流器内部短絡電圧で
規定される負荷異常検出下限電流Iaより小さい範囲では
異常が検出できない。しかも、(2)負荷電流SIが負荷
異常検出下限電流Iaより大きくなるにつれて、異常検出
の感度が鈍くなり、結局第5図に斜線で示す極めて限ら
れた範囲の負荷短絡しか対応できないという問題点があ
った。
Therefore, (1) the abnormality cannot be detected in the range where the load current SI is smaller than the load abnormality detection lower limit current Ia specified by the rectifier internal short-circuit voltage. Moreover, (2) as the load current SI becomes larger than the load abnormality detection lower limit current Ia, the sensitivity of abnormality detection becomes dull, and as a result, only a very short range of load short circuit shown in FIG. 5 can be dealt with. was there.

この発明は、負荷異常の検出可能範囲を従来より大幅に
拡大させるとともに、短絡異常のみならず開放異常につ
いても対応できる負荷異常検出方法を提供することをそ
の目的としている。
It is an object of the present invention to provide a load abnormality detecting method capable of significantly expanding the detectable range of load abnormality as compared with the prior art, and being capable of handling not only short circuit abnormality but also open abnormality.

〔問題点を解決するための手段〕[Means for solving problems]

上記の目的を達成するこの発明は、整流器の入力電流と
出力電圧とから負荷抵抗を演算手段で演算し、その演算
結果が、予め定格電流とこれに対応する短絡上限電圧と
から設定した短絡上限抵抗より小さいとき、または予め
定格電圧とこれに対応する開放上限電流とから設定した
開放下限抵抗より大きいときに、負荷異常と判断して前
記整流器出力を零にすることを特徴とする。
According to the present invention, which achieves the above-mentioned object, a load resistance is calculated from an input current and an output voltage of a rectifier by a calculation means, and the calculation result is a short circuit upper limit set in advance from a rated current and a short circuit upper limit voltage corresponding to the rated current. When it is smaller than the resistance or when it is larger than the open lower limit resistance set in advance from the rated voltage and the corresponding open upper limit current, it is judged that the load is abnormal and the rectifier output is made zero.

〔作用〕[Action]

整流器の入力電流と出力電圧とから演算手段で負荷抵抗
Rを演算する。一方、負荷短絡異常検出の上限電圧と定
格電流とから負荷短絡上限抵抗Ruを設定すると共に、負
荷開放異常検出の上限電流と定格電圧とから負荷開放下
限抵抗Rlを設定する。しかして、上記各抵抗を整流器運
転中常時比較し、負荷抵抗Rが短絡上限抵抗Ru以下のと
きは負荷短絡で所定以上の大電流が流れたと判断し、一
方、負荷抵抗Rが開放下限抵抗Rl以上のときは負荷開放
で所定以下の電流しか流れないものと判断し、いずれも
直ちに整流器出力を零にして事故の拡大を未然に防止す
る。
The load resistance R is calculated by the calculating means from the input current and the output voltage of the rectifier. On the other hand, the load short-circuit upper limit resistance Ru is set from the upper limit voltage of the load short-circuit abnormality detection and the rated current, and the load open lower limit resistance Rl is set from the upper limit current and the rated voltage of the load open abnormality detection. Then, the above resistors are constantly compared during the operation of the rectifier, and when the load resistance R is equal to or less than the short circuit upper limit resistance Ru, it is determined that a large current of a predetermined value or more has flowed due to the load short circuit, while the load resistance R is the open lower limit resistance Rl. In the above cases, it is determined that only a current equal to or less than a predetermined value will flow when the load is released, and in any case, the rectifier output is immediately set to zero to prevent the accident from spreading.

〔実施例〕〔Example〕

以下、この発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は、この発明を適用する整流器の負荷異常検出回
路の一例を示すブロック図である。なお、図中、従来と
同一または相当部分には同一符号を付してある。
FIG. 1 is a block diagram showing an example of a load abnormality detection circuit for a rectifier to which the present invention is applied. In the figure, the same or corresponding parts as in the conventional case are designated by the same reference numerals.

コントローラ10は、入出力ポート、演算処理装置(CP
U)、RAM,ROM等の記憶装置を具えるマイクロコンピュー
タを有し、その入力側ポートに、電流検出器5により得
られた電流検出信号SIと電圧検出器6により得られた電
圧検出信号VIとが、サイリスタ2が点弧している間中、
常時入力される。また、負荷の特性と整流器の仕様に合
わせて、図外の負荷異常検出レート設定装置で予め設定
された負荷短絡異常検出の上限電圧信号V1と、負荷開放
異常検出の上限電流I1とが入力される。更に、定格電圧
Vnと、定格電流Inと、電流検出器5および電圧検出器6
の各検出器誤差並びに演算誤差による誤動作を防止する
ため設定された負荷開放異常検出の下限電圧V0と、負荷
短絡異常検出の下限電流I0とが、負荷異常検知情報とし
て入力される。
The controller 10 includes an input / output port, an arithmetic processing unit (CP
U), a RAM, a microcomputer having a storage device such as a ROM, and a current detection signal SI obtained by the current detector 5 and a voltage detection signal VI obtained by the voltage detector 6 at its input port. While the thyristor 2 is firing,
It is always input. In addition, in accordance with the characteristics of the load and the specifications of the rectifier, the upper limit voltage signal V 1 for load short circuit abnormality detection and the upper limit current I 1 for load open abnormality detection that are preset by the load abnormality detection rate setting device (not shown) are Is entered. Furthermore, the rated voltage
Vn, rated current In, current detector 5 and voltage detector 6
The lower limit voltage V 0 for load open abnormality detection and the lower limit current I 0 for load short circuit abnormality detection, which are set to prevent malfunction due to each detector error and calculation error, are input as load abnormality detection information.

これらの負荷異常検知情報に基づき、コントローラ10
は、負荷異常の有無を判断し、出力側ポートから論理値
“1"又は論理値“0"の制御信号を、サイリスタ2の点
弧,消弧指令信号として出力する。すなわち例えば、異
常有りと判断すればサイリスタ2に論理値“1"の消弧信
号を出力し、これにより例えばサイリスタをそのカソー
ド及びアノード間を短絡することによって消弧し、負荷
への電力の供給が遮断される。
Based on the load abnormality detection information, the controller 10
Determines whether or not there is a load abnormality, and outputs a control signal having a logical value "1" or a logical value "0" from the output side port as a firing / extinguishing command signal of the thyristor 2. That is, for example, if it is judged that there is an abnormality, an arc-extinguishing signal having a logical value of "1" is output to the thyristor 2, whereby, for example, the thyristor is extinguished by short-circuiting its cathode and anode, and power is supplied to the load. Is cut off.

以下、第1図に示す負荷異常検出装置の構成に従って行
われるこの発明の負荷異常検出方法の手順を、上記マイ
クロコンピュータの記憶装置のROMに予め記憶された、
第2図に示すプログラムに基づいて説明する。
Hereinafter, the procedure of the load abnormality detecting method of the present invention performed according to the configuration of the load abnormality detecting device shown in FIG. 1 is stored in advance in the ROM of the storage device of the microcomputer.
Description will be made based on the program shown in FIG.

今、コントローラ10から論理値“0"の制御信号が出力さ
れており、従ってサイリスタ2のゲートにゲート信号が
供給されて点弧状態にあり、図外の負荷(例えば電気メ
ッキ装置)には、整流器を介して所定の直流電力が供給
されつつあるものとする。
Now, the control signal of logical value "0" is output from the controller 10, so that the gate signal is supplied to the gate of the thyristor 2 and is in the ignition state, and a load (for example, an electroplating device) not shown in the drawing is It is assumed that a predetermined DC power is being supplied via the rectifier.

まずステップで初期設定を実行し、次いでステップ
に移行して、電流検出器5で検出された電流信号SIと、
電圧検出器6で検出された電圧信号SVのアナログ信号を
A/D変換器でデジタル信号に変換して読み込み、ステッ
プに移行する。ステップでは、これらの検出値に基
づいて抵抗R=SV/SIを算出し、それを負荷抵抗値とし
て記憶装置の所定の領域に一時記憶する。
First, the initial setting is executed in step, and then the process proceeds to step, in which the current signal SI detected by the current detector 5 and
The analog signal of the voltage signal SV detected by the voltage detector 6
Convert to a digital signal with the A / D converter, read it, and move to the step. In step, the resistance R = SV / SI is calculated based on these detected values, and the calculated resistance R = SV / SI is temporarily stored in a predetermined area of the storage device.

次にステップに移行して、負荷の特性と整流器仕様に
応じて定められた定格電流値Inと、この定格電流Inを流
したときの許容最低電圧で表される負荷短絡異常検出上
限電圧V1とを読み込み(第3図参照)、これに基づいて
ステップで抵抗Ru=V1/Inを算出し、その結果を負荷
短絡上限抵抗値Ruとして所定の記憶領域に一時記憶す
る。
Next, move to the step, and the rated current value In determined according to the characteristics of the load and the rectifier specifications, and the load short-circuit abnormality detection upper limit voltage V 1 represented by the allowable minimum voltage when the rated current In flows Are read (see FIG. 3), and based on this, the resistance Ru = V 1 / In is calculated, and the result is temporarily stored in a predetermined storage area as the load short-circuit upper limit resistance value Ru.

次にステップに移行し、上記ステップで算出した現
負荷抵抗値Rとステップで算出した負荷短絡上限抵抗
値Ruとを比較することにより、負荷の短絡異常の有無を
判断する。すなわち、負荷に短絡があれば、正常な状態
におけるより低電圧で大電流が流れる故、負荷短絡上限
抵抗値Ruは小さい値を示す筈である。よって現負荷抵抗
値R>Ruならば負荷短絡無しと判断してステップに移
行する。一方R<Ruであれば短絡事故発生の可能性が大
きいと考えられるが、電流,電圧の検出誤差の可能性も
あり得る。そこでステップに移行し、検出電流値SIが
負荷短絡異常検出下限電流設定値I0を上回るか否かを判
断する。その結果がSI>I0であれば上記誤差の範囲外
故、、負荷短絡異常有りと判定され、ステップへ移行
して、コントローラ10の出力ポートからサイリスタ2
へ、サイリスタ消弧信号GOFFが出力されて、その結果負
荷への電流が零になり、事故拡大が防止される。
Next, the process proceeds to step, and the presence or absence of load short circuit abnormality is determined by comparing the current load resistance value R calculated in the above step with the load short circuit upper limit resistance value Ru calculated in step. That is, if there is a short circuit in the load, a large current flows at a lower voltage than in the normal state, so the load short circuit upper limit resistance value Ru should show a small value. Therefore, if the current load resistance value R> Ru, it is determined that there is no load short circuit, and the process proceeds to step. On the other hand, if R <Ru, it is considered that there is a high possibility that a short-circuit accident will occur, but there is also the possibility of current and voltage detection errors. Therefore, the process shifts to step, and it is determined whether or not the detected current value SI exceeds the load short circuit abnormality detection lower limit current set value I 0 . If the result is SI> I 0 , it is determined that there is a load short circuit abnormality because it is outside the above error range, and the process proceeds to the step, and the output port of the controller 10 is connected to the thyristor 2
The thyristor arc extinguishing signal G OFF is output to, and as a result, the current to the load becomes zero, and the accident spread is prevented.

すなわち、この実施例によれば、第3図の電圧−電流特
性が台形I0,In,V1,v0の範囲内にあるとき短絡異常有り
と判断できる。
That is, according to this embodiment, when the voltage-current characteristic of FIG. 3 is within the range of trapezoid I 0 , In, V 1 , v 0 , it can be determined that there is a short circuit abnormality.

一方、ステップで反対にSI<I0であれば、先に述べた
誤差の範囲内であるから負荷短絡異常は無いものと判定
して、ステップ以降の負荷開放異常判定に移る。
On the other hand, if SI <I 0 in the step, on the other hand, it is determined that there is no load short circuit abnormality because it is within the above-described error range, and the load release abnormality determination in the step and subsequent steps is performed.

ステップでは、負荷の特性と整流器仕様に応じて定め
られた定格電圧値Vnを読み込むと共に、負荷開放と判断
すべき限度状態でこの定格電圧Vnを加えたとき流れ得る
最大電流値を、負荷開放異常検出の上限電流I1として読
み込み(第3図参照)、これに基づいてステップで抵
抗Rl=Vn/I1を算出し、その結果を負荷開放下限抵抗値R
lとして所定の記憶領域に一時記憶する。
In the step, the rated voltage value Vn determined according to the characteristics of the load and the rectifier specifications is read, and the maximum current value that can flow when this rated voltage Vn is applied in the limit state where it should be judged that the load is released is the load release abnormality. Read as detection upper limit current I 1 (see Fig. 3), and based on this, calculate resistance Rl = Vn / I 1 in steps, and load the result as load release lower limit resistance value R
It is temporarily stored as l in a predetermined storage area.

次にステップに移行し、上記ステップで算出した現
負荷抵抗値Rとステップで算出した負荷開放下限抵抗
値Rlとを比較することにより、負荷の開放異常の有無を
判断する。すなわち、負荷に開放があれば、抵抗値は上
記負荷開放下限抵抗値Rlより大きい値を示す筈である。
よって現負荷抵抗値R<Rlならば負荷開放無しと判断し
てステップに戻る。一方R>Rlであれば負荷開放の可
能性が大きいと考えられるが、検出誤差の可能性もあり
得る。そこでステップに移行し、検出電圧値SVが負荷
開放異常検出下限電圧設定値V0を上回るか否かを判断す
る。その結果がSV>V0であれば、負荷開放異常有りと判
定され、ステップへ移行して、コントローラ10の出力
ポートからサイリスタ2へ、サイリスタ消弧信号GOFF
出力されて、負荷への電流が遮断される。その結果、負
荷開放時の電流不足によるメッキ不足などの事故を未然
に防止することができる。
Next, the process proceeds to step, and the presence or absence of load release abnormality is determined by comparing the current load resistance value R calculated in the above step with the load release lower limit resistance value Rl calculated in step. That is, if the load is open, the resistance value should be larger than the load open lower limit resistance value Rl.
Therefore, if the current load resistance value R <Rl, it is determined that the load is not released and the process returns to the step. On the other hand, if R> Rl, it is considered that there is a high possibility that the load will be released, but there is a possibility that there is a detection error. Therefore, the process proceeds to step, and it is determined whether or not the detected voltage value SV exceeds the load release abnormality detection lower limit voltage set value V 0 . If the result is SV> V 0 , it is determined that there is a load release abnormality, the process moves to step, the thyristor arc extinguishing signal G OFF is output from the output port of the controller 10 to the thyristor 2, and the current to the load is increased. Is cut off. As a result, it is possible to prevent accidents such as insufficient plating due to insufficient current when the load is released.

すなわち、この実施例によれば、第3図に示す電圧−電
流特性が台形V0,Vn,I1,i0の範囲内にあるとき開放異常
有りと判断できる。
That is, according to this embodiment, when the voltage-current characteristic shown in FIG. 3 is within the range of the trapezoids V 0 , Vn, I 1 , i 0 , it can be determined that there is an open abnormality.

これに対してSV<V0ならば、検出誤差の範囲内であり、
開放異常無しと判断されてステップに戻る。かくして
上記ステップ〜ステップを整流器の運転中繰り返し
実行することにより、負荷の短絡異常と開放異常に起因
する事故を防止する。
On the other hand, if SV <V 0 , it is within the detection error range,
It is determined that there is no opening abnormality and the process returns to the step. Thus, by repeatedly executing the above steps to steps during the operation of the rectifier, the accidents caused by the short circuit abnormality and the open abnormality of the load are prevented.

この実施例によれば、電気メッキ時の負荷短絡によるト
ランス焼損時の事故のみならず、負荷開放によるメッキ
不足などのトラブルをも未然に防止できて、しかもそれ
らの負荷異常の検知範囲を拡げ且つ検出感度も良好に保
つことができる。
According to this embodiment, not only an accident at the time of transformer burnout due to a load short circuit at the time of electroplating but also troubles such as insufficient plating due to load release can be prevented, and the detection range of these load abnormalities can be expanded. The detection sensitivity can also be kept good.

なお、上記実施例では、負荷として電気メッキ装置に適
用する場合につき述べたが、これに限らずその他例えば
電気分解、電気透析、充電等、整流器を使用する各種の
装置に適用可能である。
In the above embodiment, the case where the load is applied to the electroplating apparatus has been described, but the present invention is not limited to this and can be applied to various apparatuses using a rectifier such as electrolysis, electrodialysis, and charging.

また、六相半波整流に限定されるものではなく、単相,
三相交流や全波整流等の整流器にも適用できる。
Also, the present invention is not limited to the six-phase half-wave rectification, and the single-phase,
It can also be applied to rectifiers such as three-phase AC and full-wave rectification.

更にまた、電流検出器5の設定位置については,整流器
用変圧器3の二次側であっても良い。
Furthermore, the set position of the current detector 5 may be on the secondary side of the rectifier transformer 3.

〔発明の効果〕〔The invention's effect〕

以上説明したように、この発明によれば、整流器の入力
電流,出力電圧から負荷抵抗を演算手段で演算し、その
結果に応じて負荷異常の有無を判断して整流器出力を制
御するものとしたため、負荷異常の検出可能範囲を従来
より大幅に拡大させると共に、短絡異常のみならず開放
異常をも容易かつ確実に検出することが可能となり、整
流器における負荷異常対策の内容と範囲を著しく拡張す
るという効果が得られる。
As described above, according to the present invention, the load resistance is calculated by the calculating means from the input current and the output voltage of the rectifier, and the rectifier output is controlled by judging the presence or absence of the load abnormality according to the result. In addition to significantly expanding the load abnormality detection range, it is possible to easily and reliably detect not only short circuit faults but also open faults, and the content and range of load fault countermeasures for rectifiers will be significantly expanded. The effect is obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明を適用する装置の一例を示すブロック
図、第2図はこの発明の負荷異常検出手順を説明するフ
ローチャート、第3図はこの発明を適用する負荷異常検
出回路の動作特性図、第4図は従来の整流器の負荷異常
検出装置のブロック図、第5図は従来の負荷異常検出回
路の動作特性図である。 2はサイリスタ、3は整流器用変圧器、4はダイオー
ド、5は電流検出器、6は電圧検出器、10は演算手段
(マイクロコンピュータ)である。
FIG. 1 is a block diagram showing an example of an apparatus to which the present invention is applied, FIG. 2 is a flowchart explaining a load abnormality detecting procedure of the present invention, and FIG. 3 is an operation characteristic diagram of a load abnormality detecting circuit to which the present invention is applied. FIG. 4 is a block diagram of a conventional load abnormality detection device for a rectifier, and FIG. 5 is an operation characteristic diagram of a conventional load abnormality detection circuit. 2 is a thyristor, 3 is a rectifier transformer, 4 is a diode, 5 is a current detector, 6 is a voltage detector, and 10 is an arithmetic means (microcomputer).

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】整流器の入力電流と出力電圧とから負荷抵
抗を演算手段で演算し、その演算結果が、予め定格電流
とこれに対応する短絡上限電圧とから設定した短絡上限
抵抗より小さいとき、または予め定格電圧とこれに対応
する開放上限電流とから設定した開放下限抵抗より大き
いときに、負荷異常と判断して前記整流器出力を零にす
ることを特徴とする整流器の負荷異常検出方法。
1. A load resistance is calculated by a calculation means from an input current and an output voltage of a rectifier, and when the calculation result is smaller than a short circuit upper limit resistance preset from a rated current and a corresponding short circuit upper limit voltage, Alternatively, a load abnormality detection method for a rectifier, which determines that the load is abnormal when the open lower limit resistance set in advance from a rated voltage and an open upper limit current corresponding to the rated voltage is exceeded, and sets the rectifier output to zero.
JP61239495A 1986-10-08 1986-10-08 Rectifier load abnormality detection method Expired - Lifetime JPH0732534B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61239495A JPH0732534B2 (en) 1986-10-08 1986-10-08 Rectifier load abnormality detection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61239495A JPH0732534B2 (en) 1986-10-08 1986-10-08 Rectifier load abnormality detection method

Publications (2)

Publication Number Publication Date
JPS6395812A JPS6395812A (en) 1988-04-26
JPH0732534B2 true JPH0732534B2 (en) 1995-04-10

Family

ID=17045629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61239495A Expired - Lifetime JPH0732534B2 (en) 1986-10-08 1986-10-08 Rectifier load abnormality detection method

Country Status (1)

Country Link
JP (1) JPH0732534B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2542618Y2 (en) * 1988-08-30 1997-07-30 アルプス電気株式会社 In-vehicle load condition detection drive
JP5523297B2 (en) * 2010-12-17 2014-06-18 東芝三菱電機産業システム株式会社 Power converter
JP7577547B2 (en) 2021-01-20 2024-11-05 株式会社荏原製作所 METHOD FOR DETECTING SHORT CIRCUIT IN PLATING APPARATUS, METHOD FOR CONTROLLING PLATING APPARATUS, AND PLATING APPARATUS

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154322A (en) * 1982-03-08 1983-09-13 三菱電機株式会社 Shortcircuit detector

Also Published As

Publication number Publication date
JPS6395812A (en) 1988-04-26

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