JPH0732615B2 - Motor control device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control device for phase-locking a rotation signal of a motor with a reference signal.

Conventional technology Conventionally, when controlling the rotation of a DC motor in phase synchronization with an external reference signal, an FG signal, which is a frequency signal corresponding to the rotation speed of the motor, is obtained and the reference signal and the FG signal are compared by a phase comparator. In addition to obtaining the phase comparison signal, the period detector also detects the period of the FG signal to obtain the rotation speed signal of the motor and controls the noise power of the motor by this phase comparison signal and the rotation speed signal. The motor rotation is stably controlled by. (For example, Japanese Examined Patent Publication No. 54-31164) Problems to be Solved by the Invention In such a conventional control device, when the phase comparison signal is obtained by the phase comparator, the start-up time or the synchronizing speed is changed. In order to stably accelerate or decelerate the motor to near the synchronous speed and to stabilize the response of the control system (predetermined damping characteristic), it is necessary to detect the rotational speed by the frequency detector, and the control device is complicated. Further, since the speed signal needs a DC component for acceleration and deceleration, if an error of the DC component occurs in the speed detector, it may deviate from the sync pull-in range and phase synchronization control may not be possible.

The present invention has been made in view of the above point, and does not require a means for detecting the rotation speed of the motor and has a simple configuration. When the motor is started or when the synchronization speed is changed, the motor is stably accelerated to near the synchronization speed. (EN) Provided is a motor control device capable of decelerating and obtaining a good response (damping) characteristic during control.

Means for Solving the Problems A motor control device of the present invention is a motor having a frequency generator, and according to Table 1, based on a rotation direction command signal of the motor and a rotation direction detection signal of the motor, the frequency generator. The mode control circuit that outputs the FG signal obtained by the above and the reference signal generated by the reference pulse generator as an output pulse, and the output value is prohibited from being added above the specified upper limit and subtracted below the specified lower limit. And a phase comparator including an addition / subtraction counter that performs addition each time the output pulse is input to the up terminal of the counter and subtracts each time the output pulse is input to the down terminal of the counter; A phase compensation circuit for compensating the phase of a signal corresponding to the output, and a drive for supplying electric power corresponding to the signal phase-compensated by the phase compensation circuit to the motor Those constructed from the road.

Effect of the Invention The present invention has the above-described configuration, and when the motor rotation speed is different from the synchronous speed in an asynchronous state (the frequency of the FG pulse signal and the reference pulse signal is different), for example, when the motor is started or when the synchronous speed is changed, the addition / subtraction counter Error accumulates in the addition or subtraction direction, and since the error is limited by the above upper limit value or lower limit value, the motor is accelerated or decelerated to a predetermined synchronous speed, and the output of the addition / subtraction counter is Since the control system is phase-compensated so as to give a predetermined response, the motor is stably controlled in synchronization.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of essential parts in one embodiment, FIG. 2 is a detailed view of the phase comparator 6 in FIG. 1, FIG. 3 is a transmission block diagram of the control system shown in FIG. 1, and FIG. FIG. 3 is a detailed view of the mode control circuit in FIG.

In FIG. 1, 1 is a DC motor, 2 is a frequency generator that generates a frequency signal (FG signal) corresponding to the rotation speed of the DC motor 1, and 4 is a pulse signal that amplifies the FG signal obtained from the frequency generator 2. It is a waveform shaper that performs waveform shaping on the output terminal 41 and outputs it as an FG pulse signal to the output terminal 41. In this embodiment, the frequency generator 2 is designed to output Z pulses to the output terminal 41 for each rotation of the motor 1. Three
Is a reference pulse generator and outputs a reference pulse signal to the output terminal 31.

Reference numeral 5 is a mode control circuit, and a reference pulse signal is input to the input terminal 51 and an FG pulse signal is input to the input terminal 52. A rotation direction command signal (ED), which is a high level signal when the rotation direction command is clockwise (normal rotation) and a low level when the rotation direction command is counterclockwise (reverse rotation), is input to the input terminal 55. A rotation direction detection signal (MD), which is a high level signal when the rotation direction of the motor is clockwise (forward rotation) and a low level when the rotation direction of the motor is counterclockwise (reverse rotation), is input to the input terminal 56.

The mode control circuit 5 is constructed as shown in FIG. In FIG. 4, 501 and 502 are differentiators, 503 is a 2-input OR gate circuit, and 504 and 505 are 4-input multiplexers.

A reference pulse signal is input to the differentiating circuit 501 from the input terminal 51 and an FG pulse signal is input to the differentiating circuit 502 from the input terminal 52, and a pulse signal of a minute width is output at each rising edge of the input pulse signal. The outputs of the differentiating circuits 501 and 502 are input to the OR gate circuit 503, and the outputs thereof output pulses corresponding to the rising edges of the reference pulse signal and the FG pulse signal.

The multiplexers 504 and 505 input D0 when select terminals A and B are both at high level, input D1 when terminal A is at high level and terminal B is at low level, and input D1 when terminal A is at low level and terminal B is at high level. When it is, the input D2 is output, and when both terminals A and B are at the low level, the input D3 is output. Multiplexer
Rotation direction command signal (ED) is applied to select terminal A of 504 and 505.
However, the rotation direction detection signal (MD) is input to the select terminal B.

The output of the differentiator 501 is connected to the input D0 of the multiplexer 504 by D1.
The output of the OR gate 503 is input to, the output of the differentiator 502 is input to D3, the D2 is grounded, and the low level is input. Further, the output of the differentiator 502 is input to the input D0 of the multiplexer 505, the output of the OR gate 503 is input to D2, the output of the differentiator 501 is input to D3, and D1 is grounded and the low level is input.

By configuring the mode control circuit as shown in Fig. 4, signals corresponding to the rising edges of the reference pulse and FG pulse are output to the output terminals 53 and 54 according to the ED and MD signals as shown in Table 1. To be done.

Reference numeral 6 is a phase comparator, and input terminals 61 and 62 are connected to output terminals 53 and 54 of the mode control circuit 5, respectively.

The phase comparator 6 is constructed as shown in FIG. In FIG. 2, reference numeral 6-1 is a 4-bit binary addition / subtraction counter having output terminals Qa, Qb, Qc, Qd, where Qa is the least significant bit, Qb is the second bit, Qc is the third bit, and Qd. Is an output terminal for the most significant bit, and each output is output to the output terminal 63 as 4-bit output data (D ₀ , D ₁ , D ₂ , D ₃ ).
6-2 is a 4-bit switch circuit whose output terminals a, b, c
Is a logic level (0) and the output terminal d is a logic level (1)
The output terminals a, b, and
c and d are connected to the data input terminals A, B, C and D of the addition / subtraction counter 6-1. 6-3 is a 4-input AND gate circuit,
The input terminal is the output terminal Qa, Qb, Qc, Q of the addition / subtraction counter 6-1.
Each connected to d. Reference numeral 6-4 is a 4-input NOR gate circuit, which is a gate circuit, whose input terminals are addition / subtraction counters 6-, respectively.
It is connected to one output terminal Qa, Qb, Qc, Qd. 6-5, 6-
Reference numeral 6 is a 2-input OR gate circuit. One input terminal of the gate circuit 6-5 is connected to the output terminal of the gate circuit 6-3, and the other input terminal is connected to the input terminal 61 of the phase comparator 6.
One input terminal of the gate circuit 6-6 has a gate circuit 6-4.
, And the other input terminal is connected to the input terminal 62 of the phase comparator 6. The output terminals of the gate circuits 6-5 and 6-6 are connected to the UP and DOWN terminals which are the clock input terminals of the addition / subtraction counter 6-1. A switch 6-7 has one terminal grounded and the other terminal connected to the LOAD terminal of the addition / subtraction counter 6-1.

The addition / subtraction counter 6-1 performs addition for each rising edge of the pulse input to the UP terminal and subtracts for each rising edge of the pulse input to the DOWN terminal. In the initial state when the power is turned on, the LOAD terminal is grounded via the switch 6-7 and each data input to the data terminals A, B, C, D is loaded and output terminals Qa, Qb, Qc, Output to Qd.

Numeral 7 is a 4-bit D / A converter, which is input data (D ₀ , D ₁ , D ₂ , D ₃ )
And it outputs the analog voltage _{E 0 = E * (D 0} * 2 0 + D 1 * 2 1 + D 2 * 2 2 + D 3 * 2 3) / 2 4 output terminals 72 corresponding to.

Reference numeral 8 is a phase compensating circuit for compensating the phase advance in the high frequency region, the input terminal 81 is connected to the output terminal 72 of the D / A converter 7, and the phase-compensated signal EP is output to the output terminal 82. Its transfer function is 1 + T * S (S: Laplacian). The output terminal 82 of the phase compensation circuit 8 is connected to the input terminal 91 of the drive circuit 9. The drive circuit 9 has a reference voltage E
A current proportional to the difference voltage between _R (E _R = E / 2) and the voltage E _P input to the input terminal 91 is supplied to the motor 1 via the output terminal 92.

The operation when the motor 1 is started by giving the normal rotation direction command in the above-described configuration will be described.

In the initial state, the LOAD terminal of the addition / subtraction counter 6-1 is grounded via the switch 6-7, and the addition / subtraction counter 6
The 4-bit output data of -1 is (D ₃ , D ₂ , D ₁ , D ₀ ) = (1,
0,0,0), and the voltage of E / 2 is output to the output terminal 82. Therefore, no current is supplied to the motor 1. The output levels of the gate circuits 6-3 and 6-4 are maintained at (0). When the switch 6-7 is opened, the load state of the addition / subtraction counter 6-1 is released and the addition is performed at each rising edge of the reference pulse input to the reference input terminal 61. As a result, a voltage of E _R or higher is output to the output terminal 82, and the motor 1
Generates acceleration torque and starts to rotate, and FG pulse is input terminal 62
, And the counter 6-1 will subtract every rising edge of the FG pulse. Generally, ff during acceleration such as startup
g <fref (ffg: frequency of FG pulse, fref: frequency of reference pulse), and the value of the output data of the addition / subtraction counter 6-1 increases for a while, but the output data (D ₃ , D ₂ , D ₁ , D ₀ ) Is (1,1,
When it becomes 1,1), the output level of the gate circuit 6-3 becomes (1)
Therefore, it is prohibited to input additional pulse to UP terminal. Therefore, the motor 1 is accelerated to near the synchronous speed, and finally the motor 1 is controlled to rotate in a synchronous state, that is, the frequency of the FG pulse becomes equal to the frequency of the reference pulse.

The operation at startup has been described above, but when changing the synchronous speed to a higher synchronous speed, it can be achieved by setting the frequency of the reference pulse to a higher value, and the behavior of the system at the time of acceleration at that time is the same as that at startup described above. Then, it becomes a synchronized state at a higher speed. Next, if the frequency of the reference pulse signal is set to a low value from a certain synchronization state, ffg> fref, and the addition / subtraction counter 6-1 is temporarily subtracted, and its output data (D ₃ , D ₂ , D ₁ , D ₀ ) becomes (1, Motor 1 becomes smaller than 0,0,0)
A deceleration torque is generated in the motor 1 and the motor 1 starts decelerating. During deceleration, the output data (D ₃ , D
₂ , D ₁ , D ₀ ) may reach (0,0,0,0), but when all the 4-bit output data becomes (0), the output of the gate circuit 6-4 becomes (1) and the counter 6 Since the pulse for subtraction is not input to the DOWN terminal of -1, the motor 1 is decelerated to the vicinity of the set synchronous speed, and thereafter the rotation is controlled to the synchronous state.

A transfer block diagram of the control system in the synchronized state is shown in FIG. In FIG. 3, J is the moment of inertia of the rotating portion of the motor 1, Kθ (S) is the transfer characteristic of the phase comparator 6 and the D / A converter 7, (1 + T * S) is the transfer characteristic of the phase compensation circuit 8, and 1 In the transfer characteristics of the low-pass filter for noise removal of the / (1 + T _F * S) circuit, its time constant T _F is made sufficiently small so as not to affect the system response. gm is the transfer characteristic of the drive circuit 9, and K _T is the torque constant of the motor 1. or,
S is Laplacian, T _L is the load torque of the motor 1, and θm is the rotation angle of the motor 1.

Further, if the natural angular frequency ωn of this system exists in the frequency region where the phase rotation of Kθ (S) is small, the transfer function from the load torque to the rotation angle in the vicinity of the frequency region is as shown in equation (1). It becomes a secondary resonance system.

here Incidentally, by appropriately selecting the time constant of the filter of the phase compensation circuit 8 according to ωn << 1 / T _{F, the} control system can be stabilized.

Effects of the Invention As described above, the motor control device of the present invention generates the FG signal and the reference pulse generator obtained from the frequency generator based on the motor rotation direction command signal and the motor rotation direction detection signal. Output the reference signal as an output pulse,
The output value is prohibited from being added above a predetermined upper limit value and subtracted below a predetermined lower limit value, and addition is performed each time the output pulse is input to the up terminal of the addition / subtraction counter,
By performing phase compensation on the phase signal obtained from the phase comparator that performs the subtraction each time the output pulse is input to the down terminal of the adder / subtractor counter, and supplying power to the motor by the phase compensated signal. With a very simple structure, stable acceleration and deceleration can be performed at the time of starting the motor and changing the synchronous speed, and more stable control characteristics can be obtained.

In the embodiment, the output value of the counter is D / A converted and then the phase is compensated in an analog manner. However, the counter output is phase-compensated by a digital filter, and then the D / A converter is used. It goes without saying that the same effect can be obtained even with an analog value.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts in a motor control device according to an embodiment of the present invention, FIG. 2 is a detailed view of a phase comparator, FIG. 3 is a transmission block diagram of a control system in the present embodiment, and FIG. FIG. 3 is a detailed view of the mode control circuit in FIG. 1 ... Motor, 2 ... Frequency generator, 3 ... Reference pulse generator, 4 ... Waveform shaper, 5 ... Mode control circuit, 6
...... Phase comparator, 7 …… D / A converter, 8 …… Phase compensation circuit, 9 …… Driving circuit, 6-1 …… Addition / subtraction counter, 6-
3 ... 4-input AND gate circuit, 6-4 ... 4-input NOR gate circuit, 6-5, 6-6 ... 2-input OR gate circuit.

Claims (1)

[Claims] 1. A motor having a frequency generator, and an FG obtained from the frequency generator based on a motor rotation direction command signal and a motor rotation direction detection signal according to the following table.
A signal and a reference signal generated by a reference pulse generator as an output pulse, a mode control circuit for prohibiting addition and subtraction of an output value above a predetermined upper limit value and below a predetermined lower limit value, and a counter Corresponding to the output of the addition / subtraction counter and a phase comparator consisting of an addition / subtraction counter that performs addition each time the output pulse is input to the up terminal of the counter and subtracts each time the output pulse is input to the down terminal of the counter. A motor control device comprising a phase compensation circuit for compensating for the phase of a signal, and a drive circuit for supplying electric power corresponding to the signal phase-compensated by the phase compensation circuit to the motor.