JPH0732638B2 - Driving device for stepping motor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a driving device for a stepping motor that is rotationally driven by the number of step pulses input from the outside, and particularly, in a driving period for the number of step pulses. The present invention relates to a drive device for a stepping motor that controls the rotation speed to be accelerated, fixed, or decelerated.

[Prior Art] For example, a stepping motor is generally used as a carriage motor for moving and controlling a carriage having a print head in an electronic typewriter or a printing device, a carrier motor for moving a magnetic bed in a magnetic recording device, and the like. The stepping motor is rotationally driven by the number of step pulses input from the outside by the driving device.

Among such drive devices for rotationally driving a stepping motor, there is one in which the rotational speed is changed according to the number of steps as shown in FIG. 7 in order to shorten the time required for the motor to rotationally drive. . That is, for example, when rotating by the number of C step pulses, the rotational speed is accelerated from the start of rotation to the A step, is driven at a constant speed from the A step to the B step, and is decelerated from the B step to the last C step. . Generally, the speed control changes the pulse interval of the step pulse applied to the stepping motor. For example, when accelerating, the pulse interval is gradually decreased, and when decelerating, the pulse interval is gradually increased.

FIG. 8 shows a circuit for implementing the speed control shown in FIG. The count value (speed data) corresponding to the pulse interval at each step number X in FIG. 7 is set in the ROM1. The ROM1 and RAM2 are connected to the CPU 6 via the data bus 3, address bus 4, and control bus 5. The count value indicating the speed read from the ROM 1 is latched by the latch circuit 7 and then set in the counter 8. The count value set in the counter 8 is subtracted by the clock signal output from the clock generator 9. When the count value reaches 0, one drive pulse is sent to the motor drive circuit 11 that drives the stepping motor 10.
At the same time, an interrupt signal is sent to the CPU 6 via the OR gate 12.

The CPU 6 to which the interrupt signal is input executes the interrupt processing shown in FIG. That is, when the count value for counting the number of input step pulses is X, it is set to 1 each time an interrupt signal is input.
Only increase. If the count value X after the increase is less than the A step shown in FIG.
The count value (speed data) corresponding to the number of corresponding steps stored in is read out and set in the latch circuit 7, and when it is equal to or more than A step and less than B step, a predetermined constant count value is set in the latch circuit 7 and is set in C step. If it reaches, stop the motor. In some cases, when the constant speed is reached, the data of the constant count value is first set in the latch circuit 7.

[Problems to be Solved by the Invention] However, with the above configuration, an interrupt signal is input to the CPU 6 every time the stepping motor 10 rotates by one step pulse, and the CPU 6 outputs the interrupt signal. Each time an input is made, it is necessary to carry out the interrupt processing shown in FIG. 9 including the reading of data and setting to the latch circuit 7. Thus, in a device that executes a predetermined interrupt process every time the stepping motor 10 is rotated by one step pulse, if the pulse gap is set to be short in order to increase the rotation speed at the time of acceleration, the CPU6 interrupts the interrupt process. The required time becomes longer than the count-up time of the counter 8, resulting in a problem that the speed cannot be set above a certain allowable limit value. Therefore, it is difficult to reduce the time required to drive the entire motor rotation.

The present invention has been made based on such a situation, and an object thereof is to sequentially output each pulse interval value during acceleration / deceleration stored in a storage unit to a data bus via a DMA control unit. By doing so, acceleration, constant speed, and deceleration control of the stepping motor can be performed without performing an interrupt operation for each step of the CPU, the time required for rotational driving of the motor can be shortened, and the margin time in the CPU increases. It is an object of the present invention to provide a stepping motor drive device that can improve the processing efficiency of other processes simultaneously performed.

[Means for Solving Problems] In the present invention, whether the data of each pulse interval at the time of acceleration, the pulse interval at a constant speed, and the pulse interval at the time of deceleration is the data of the pulse interval at the time of acceleration and deceleration is used. The speed memory that stores both the shift flag indicating the number and the final pulse interval data during deceleration in the order of address numbers, and the number of pulse interval data during deceleration in the speed memory from the number of step pulses input from the outside. A pulse number latch circuit for latching the step pulse number obtained by subtracting, and a DMA control unit for sequentially outputting the data of the pulse interval stored in the speed memory to the data bus in order of address number together with the shift flag and the final flag corresponding to the data. , The shift flag output to the data bus is the pulse at acceleration and deceleration A first logic circuit which sends a DMA request signal to the DMA control unit for reading the data of the next address number when indicating the data of the interval, and a data latch circuit which latches the data of the pulse interval sent to the data bus, A data counter that counts the pulse interval of the data latched in this data latch circuit, a motor drive circuit that receives the drive pulse output from the data counter each time the timing ends, and drives the stepping motor to rotate. A pulse counter that counts the number of pulses, and DMA when the count value of this pulse counter matches the number of pulses latched in the pulse latch circuit.
A pulse number matching circuit that sends a request signal to the DMA control unit,
And a second logic circuit that outputs an interrupt signal for stopping the stepping motor drive when the final flag output to the data bus indicates data of the final pulse interval during deceleration.

[Operation] With the stepping motor drive device configured as described above, when an arbitrary number of step pulses are input from the outside, the number of data of the pulse interval at the time of deceleration of the speed memory is subtracted from the number of step pulses. The step number is latched in the pulse number latch circuit. Next, under the control of the DMA controller, first, the pulse interval data of the leading address number, the shift flag and the final flag are output from the speed memory to the data bus. Then, the pulse interval data is latched by the data latch circuit. As a result, the data counter measures the latched pulse interval, and when the time measurement ends, the drive pulse is sent to the motor drive circuit,
The stepping motor rotates one step. At this time, since the shift flag output to the data bus indicates that the data is data at the time of acceleration, a DMA request signal is sent from the first logic circuit to the DMA control unit. As a result, the pulse interval data of the next address number, the shift flag and the final flag are output from the speed memory to the data bus, and the drive pulses are sent out at the pulse intervals of the output data as described above. In this way, drive pulses are sequentially sent to the motor drive circuit based on each pulse interval data at the time of acceleration stored in the speed memory, and the stepping motor is accelerated.

After that, when the pulse interval data at a constant speed is output to the data bus, the shift flag output together with the data indicates that the data is not data during acceleration and deceleration, and therefore a DMA request signal is sent to the DMA control unit. Disappear. As a result, the data of the data latch circuit does not change from the pulse interval data at the constant speed, so that drive pulses are sent at constant intervals and the stepping motor is driven at a constant speed.

After that, when the number of drive pulses to be sent to the motor drive circuit matches the number of pulses latched in the pulse number latch circuit, a DMA request signal is sent from the pulse number matching circuit to the DMA controller. As a result, the next pulse interval data in the speed memory and the corresponding shift flag and final flag are output to the data bus. Then, the pulse interval data is latched by the data latch circuit, and the drive pulse is transmitted at the latched pulse interval. At this time, since the shift flag output to the data bus indicates that the data is for deceleration, a DMA request signal is sent from the first logic circuit to the DMA control unit. As a result, the pulse interval data of the next address number, the shift flag and the final flag are further output from the speed memory to the data bus, and the drive pulse is transmitted at the pulse interval. In this way, drive pulses are sequentially sent to the motor drive circuit based on the pulse interval data at the time of deceleration stored in the speed memory, and the stepping motor is decelerated.

When the final flag output to the data bus indicates the final data at the time of deceleration, the stepping motor drive stop interrupt signal is output from the second logic circuit, and the stepping motor is stopped.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a driving device of a stepping motor according to an embodiment. In the figure, 20 is a CPU (central processing unit), and this CPU 20 has a speed memory and a ROM 24 storing various control programs via a data bus 21, an address bus 22 and a control bus 23, a speed memory transferred from this ROM 24, etc. It controls the RAM 25, which temporarily stores variable data, and the DMA controller 26, which directly outputs the count value of each pulse interval of the speed memory stored in the RAM 25 to the data bus 21 without passing through the CPU 20.
Connected to the data bus 21 is a pulse number latch circuit 27 that latches a value obtained by subtracting the number of data of pulse intervals during deceleration described later from the number of step pulses input from the outside, and the output signal of this pulse number latch circuit 27 is It is inputted to one input terminal of a pulse number matching circuit 28 composed of a plurality of exclusive OR gates or the like.

The D ₀ signal of the data bus 21 is input to the D input terminal of a D-type flip-flop 29 as the second logic circuit, and the D ₁ signal is input to the D-type flip-flop 30 as the first logic circuit. Input to the D input terminal. Also, the data bus
The D _{2 to} Dn ₊₂ signals of 21 are input to the data terminal of the data latch circuit 31 in which each pulse interval (count value) of the speed memory is latched. The count value of the pulse interval latched by the data latch circuit 31 is set in the data counter 32.

When the H level DMA request signal is input to the DMA request terminal REQ, the DMA control unit 26 sends a hold request signal to the CPU 20, and the CPU 20 returns a hold response signal.
The H-level DMA response signal ACK output from the DMA control unit 26 is input to the load terminal of the data latch circuit 31 via one input terminal of the AND gate 33 and triggers the flip-flops 29 and 30. Input to the terminal T. Further, the DMA response signal ACK is the R / S flip-flop 34
Input to the clear terminal of. The output signal of the Q output terminal of the flip-flop 30 is input to the DMA request terminal REQ of the DMA control unit 26 via the AND gate 35 together with the output signal of the Q output terminal of the R / S flip-flop 34. The output signal from the Q output terminal of the flip-flop 29 is input as an interrupt signal to the interrupt terminal INT of the CPU 20 via one input terminal of the AND gate 36.

The pulse signal output from the P1 output port of the CPU 20 is input to the preset input terminal of the R / S flip-flop 34 and the preset input terminal of the flip-flop 30 via the OR gate 37. The gate signal output from the P2 output port of the CPU 20 is input to the gate terminal G of the clock oscillator 38. The clock oscillator 38 sends a clock signal of a predetermined frequency CLK to the clock terminal of the data counter 32 while the gate signal of H level is applied to the gate terminal G. The pulse signal output from the P3 output port of the CPU 20 is applied to the load terminal of the data counter 32 via the OR gate 39. When a pulse signal is input to the load terminal of the data counter 32, the count value indicating the pulse interval latched by the data latch circuit 31 is fetched in a register, and this count value is subtracted each time the clock signal is input to the clock terminal. Then, when the count value reaches 0, a drive pulse is applied from the CY output terminal to its own load terminal via one input terminal of the OR gate 39, and a stepping motor 41 is rotationally driven via the OR gate 40. Drive circuit
Apply to 42. The pulse signal output from the P4 output port of the CPU 20 is input to the other input terminal of the OR gate 40. The output signal of the OR gate 40 is input to the motor drive circuit 42 and the pulse number counter 43
Input to the clock terminal of. The output signal of the pulse number counter 43 is input to the other input terminal of the pulse number matching circuit 28. The output signal of the pulse number counter 43 is sent to the outside as a monitor signal as information indicating the actual rotational position of the stepping motor 41. Pulse number matching circuit
28 is a preset terminal of the flip-flop 30 via the OR gate 37 from the output terminal when the number of pulses transmitted from the pulse number counter 43 matches the number of pulses transmitted from the pulse number latch circuit 27. Is input to.

Also, the system reset signal SR input from the outside is CP
U20, input to reset terminal of DMA control unit 26 and R / S
It is input to the clear terminal of the flip-flop 34.

A speed memory 44 shown in FIG. 2 is formed in the ROM 24. The speed memory 44 stores data for embodying the speed control shown in FIG. That is, the horizontal axis of FIG. 3 shows the number of steps of the drive pulse applied to the motor drive circuit 42. Normally, this numerical value indicates the physical position of the object moved by the stepping motor 41. X is the number of steps to the stop position of the stepping motor 41. The vertical axis represents the pulse transmission interval of the drive pulse transmitted to the motor drive circuit 42, that is, the speed CL of the clock signal output from the clock oscillator 38 to the speed of the stepping motor 41.
The pulse ratio of CLK / 3 to CLK / 8 is 1/3 to 1/8 of CLK. In Fig. 3, acceleration is carried out in 5 steps from the low speed of CLK / 8, and CLK is executed in the 6th step.
When it becomes / 3, the speed becomes constant, the deceleration is started at the position of the (X-3) th step, the deceleration is carried out in three stages, and then stopped at the position X.

In the speed memory 44 shown in FIG. 2, bits 2 to n + 2 of the start address number A ₀ to the address number _AE-1 have count values indicating pulse intervals at the time of accelerating in five stages of 8, 7, 6, 5, and 4. , 3 at a constant speed and 6, 4 and 8 deceleration at three stages are stored. Also, 2n-1 is stored in the final address number A _E. Then, in bit 1, a shift flag 45 of 1 is stored in addition to the address number of 3 at a constant speed and 2n-1 at the final stop. Furthermore, at bit 0, the final address number A _E is 1
The final flag 46 of is stored.

Then, when a step pulse having an arbitrary number is input from the outside, the CPU 20 executes the initialization process of FIG. That is, when the flow chart is started, the second
Each data in the speed memory 44 shown in the figure is transferred into the RAM 25. Next, the DMA control unit 26 is initialized. Then, the start address number A ₀ is set as the DMA start address, and the final address number A _E is set as the DMA end address. The step number obtained by subtracting the value obtained by subtracting one step from the deceleration start position from the next input step pulse number is used as the pulse number latch circuit 27
Set to. In the example, it is (X-4).

When the above processing is completed, one pulse of H level is output from the P1 output port. Then, the flip-flop 30 and the R / S flip-flop 34 are set, and the AND gate 3
A DMA request signal of H level from 5 is applied to the DMA control unit 26. The DMA control unit 26 sends a hold request signal to the CPU 20,
The CPU 20 returns the hold response signal to the DMA control unit 26, and the DM
The A control unit 26 starts the DMA processing. That is, the start address number A ₀ of the RAM 25 is designated and the read signal RD, the write signal WR, and the DMA response signal ACK are transmitted. Then And Gate
33 is established, and the pulse signal is input to the trigger terminals of the flip-flops 29 and 30 and the load terminal of the data latch circuit 31. Then, the data 0, 1, 8 of bit 0, bit 1, bit 2 to n + 2 of the start address A ₀ of the speed memory 44 of FIG. 2 output to the data bus 21 are set. Also, R / S
The flip-flop 34 is cleared. As a result, the output signal of the Q output terminal of the R / S flip-flop 34 becomes L level, and the DMA request terminal REQ of the DMA control unit 26 becomes L level. Therefore, the DMA control unit 26 releases the hold signal sent to the CPU 20, so that the CPU 20 restarts the execution of the flowchart of FIG.

When the flow chart is restarted, the CPU 20 outputs one H level pulse from the P3 output port. Then, since this pulse is input to the load terminal of the data counter 32 via the OR gate 39, the count value latched by the data latch circuit 31, that is, the count value 8 corresponding to the pulse interval of the start address A ₀ of the speed memory 44 is set. Is initialized to the register of the data counter 32.

Next, the CPU 20 outputs one pulse again from the P1 output port. Then R / S flip-flop 34, flip-flop
30 is preset again, and the DMA request signal is input to the DMA control unit 26 again. Then, since the read address in the DMA control unit 26 is incremented by ₁ , the data 0 and 1.7 at the next address number A _{1 in} the speed memory 44 are respectively flip-flop 2
9, 30, set in the data latch circuit 31.

Next, the CPU 20 sends out one pulse of H level from the P4 output port. Then, this pulse is applied as a drive pulse to the motor drive circuit 42 via the OR gate 40.
The stepping motor 41 rotates by one step pulse. At the same time, the pulse number counter 43 increments by one pulse.

Further, when the CPU 20 changes the P2 output port to the H level, this initialization process ends. When the above initial setting processing is completed, each circuit of FIG. 1 operates without the program intervention of the CPU 20, and the stepping motor 41 performs acceleration, constant speed, and deceleration operations according to the setting data of the speed memory 44. To do.

That is, when the P2 output port becomes H level, the gate terminal G of the clock oscillator 38 becomes H level, so that the clock oscillator 38 inputs the clock signal of the predetermined frequency CLK to the data counter 32. Then, the data counter 32 subtracts and counts the count value set in the register. Then, when the count value reaches 0, the output terminal
A drive pulse from CY is applied to the motor drive circuit 42 via the OR gate 40. Then, the stepping motor 41 rotates by one pulse. At the same time, the count value of the pulse number counter 43 is incremented by 1. Further, since the drive pulse is input to its own load terminal via the OR gate 39, the data counter 32 corresponds to the next count value from the data latch circuit 31, that is, the pulse interval of the address number A ₁ of the speed memory 44. At the same time that the count value 7 is set, it is subtracted by the clock signal. The drive pulse is R / S
Since this is input to the preset terminal of the flip-flop 34, this R / S flip-flop 34 is established and the DMA control unit 26
The next DMA request signal is sent to. Although this drive pulse is also input to the AND gate 36, since the output signal of the flip-flop 29 at this time is at L level, no interrupt signal is applied to the CPU 20.

As described above, the data counter 32 sequentially sets and subtracts the pulse interval (count value) set in the speed memory 44, and accelerates the rotation speed of the stepping motor 41.
Then, when the address number A reaches A ₅ , 0 is input to the flip-flop 30, so that the AND gate 35 becomes R / S.
It does not hold regardless of the output level of the flip-flop 34. Therefore, from the next time, even if the drive pulse is output from the data counter 32, the DMA control unit 26 does not operate. Then, during this period, the count value 3 corresponding to the constant speed of the address number A ₅ remains set in the data latch circuit 31, so that the data counter 32 drives the drive pulse every time the count value of the constant speed is counted up. To the motor drive circuit 42 and the pulse number counter 43. Then, the stepping motor 41 rotates at a constant speed.

When the count value of the pulse number counter 43 matches the pulse number of the pulse number latch circuit 27, the stepping motor 41 has reached the deceleration start position (X-4) in FIG. A pulse is sent to the preset terminal of the flip-flop 30. Then, the AND gate 35 is established and the DMA request signal is applied to the DMA control unit 26. Then, the DMA control unit 26 sets each data 0, 1, ₄ of the next address number A ₆ of the speed memory 44 in the flip-flops 29, 30, and the data latch circuit 31, respectively. Since the shift flag 1 is set in bit 1 thereafter, the count value of each pulse interval of the speed memory 44 is sequentially set in the data latch circuit 31 as in the acceleration. Therefore, the transmission intervals of the drive pulses output from the data counter 32 are sequentially shortened. When the address number A reaches the final address number A _E , the flip-flop 29 is established, and at the timing when the drive pulse is sent from the data counter 32, the interrupt terminal I of the CPU 20 is passed through the AND gate 36.
An interrupt signal for stopping the stepping motor drive is input to NT.

When the interrupt signal is input to the interrupt terminal INT, the CPU20
Run the flowchart in the figure. That is, the output level of the P2 output port is returned to the original L level. Then the clock oscillator
Since the gate terminal G of 38 returns to the L level, the data counter 32 stops the counting operation and the output of the drive pulse is stopped. As a result, the stepping motor 41 stops rotating.

At this time, an execution time is required to implement the flowchart of FIG. 6, and if the data counter 32 finishes counting the count value during this execution time, the motor drive circuit 42
An extra drive pulse is applied to the. In order to avoid this situation, assuming that the number of digits of the data latch circuit 31 and the data counter 32 is n, the maximum value (2n-1) that can be set in the data latch circuit 31 and the data counter 32 is set. Therefore, it is always possible to end the process of FIG. 6 before the end of the countdown of the maximum value.

Note that FIG. 4 shows the output ports P1, P2, P3,
6 is a time chart showing the output state of P4, the generation timing of a DMA request signal REQ of the DMA control unit 26, and the generation timing of an interrupt signal for the CPU 20.

In the case of the stepping motor driving device configured as described above, the CPU 20 only performs the initialization process shown in FIG. 5 when the stepping motor 41 starts rotating, and the stepping motor 41 performs acceleration, constant speed, and deceleration operations. To execute.
Then, the CPU 20 need only perform the stepping motor stop processing shown in FIG. 6 when the interrupt signal is input.

Therefore, the motor drive circuit 42 of the stepping motor 41 is
The acceleration, constant speed, and deceleration control of the stepping motor 41 can be performed without sending an interrupt signal to the CPU 20 for each drive pulse (step pulse) applied to the. As a result, the count value corresponding to the pulse interval indicating the rotation speed set in the speed memory 44 can be set small regardless of the processing speed of the CPU 20, so that the time required for the acceleration and deceleration of the stepping motor 41 can be reduced. Therefore, it is possible to shorten the time required to drive the entire motor.

Moreover, since the processing amount of the CPU 20 is significantly reduced, other processing can be performed during that time. For example, in a printing device or the like, a process of reading out a character pattern corresponding to a character code input from the outside from a character generator and editing it can be performed.

[Effect of the Invention] As described above, according to the present invention, the data of each pulse interval at the time of acceleration, the pulse interval at a constant speed, and the pulse interval at the time of deceleration are the data of the pulse interval at the time of acceleration and deceleration. A speed memory that stores in order of address number together with a speed change flag indicating whether or not and a final flag indicating whether or not the final pulse interval during deceleration is provided, and the pulse interval data, speed change flag and final flag of this speed memory A DMA controller that reads sequentially is provided. When an arbitrary step pulse number is input from the outside, the pulse number latch circuit latches the step pulse number obtained by subtracting the pulse interval data number during deceleration in the speed memory from the step pulse number. At the same time, the DMA controller uses the speed memory to output the pulse interval data and The lag and the final flag are read out, and a driving pulse is output each time the timing of the pulse interval is completed to drive the stepping motor to rotate. Further, when the read shift flag indicates that it is pulse interval data during acceleration and deceleration, and the count value of the pulse number counter that counts the number of drive pulses matches the number of pulses latched in the pulse number latch circuit. In this case, the DMA request signal for reading the pulse interval of the next address number is sent to the DMA control unit, and if the read final flag indicates the final data of the pulse interval during deceleration, stop the stepping motor drive. The interrupt signal of is output.
Therefore, the acceleration, constant speed, and deceleration control of the stepping motor can be performed without performing the interrupt operation for each step to the CPU, and the time required for rotational driving of the motor can be shortened and the margin time in the CPU is increased. It is possible to improve the processing efficiency of other processing simultaneously performed. Moreover, since the shift flag read from the deceleration memory together with the pulse interval data can automatically cause a state change from acceleration to constant speed, it is not necessary to be aware of the number of steps from the start to the end of acceleration. Also, the pulse number latch circuit latches the step pulse number obtained by subtracting the data number of the pulse interval during deceleration from the step pulse number input from the outside, and detects the match between this latched step pulse number and the drive pulse number. By doing so, it is possible to automatically cause a state change from constant speed to deceleration, so it is not necessary to be aware of the number of steps from startup to deceleration start. Therefore, it becomes possible to easily cope with various slow-up or slow-down patterns.

[Brief description of drawings]

FIG. 1 is a block diagram showing a stepping motor drive device according to an embodiment of the present invention, FIG. 2 is a diagram showing a speed memory of the same embodiment, and FIG. 3 is a speed control of the stepping motor of the same embodiment. FIG. 4, FIG. 4 is a time chart showing the operation of the embodiment, FIGS. 5 and 6 are flow charts showing the operation of the embodiment, and FIG. 7 is a view showing the speed control of the stepping motor of the conventional apparatus, FIG. 8 is a block diagram showing a conventional device, and FIG. 9 is a flow chart showing the operation of the conventional device. 20 …… CPU, 21 …… Data bus, 22 …… Address bus, 2
3 ... Control bus, 24 ... ROM, 25 ... RAM, 26 ... DMA control unit, 27 ... Pulse number latch circuit, 28 ... Pulse number matching circuit, 29 ... Flip-flop (second logic Circuit), 30 ...
… Flip-flop (first logic circuit), 31 …… Data latch circuit, 32 …… Data counter, 34 …… R / S flip-flop, 38 …… Clock oscillator, 41 …… Stepping motor, 42 …… Motor drive Circuit, 43 ... pulse number counter, 44 ... speed memory, 45 ... shift flag, 45 ... end flag.

Claims (1)

[Claims] 1. A pulse transmission interval of a step pulse signal applied to a stepping motor at the time of acceleration is sequentially decreased, and the pulse transmission interval is maintained at a constant value after reaching a predetermined speed,
In a stepping motor driving device that rotationally drives the stepping motor by the number of step pulses input from the outside by sequentially increasing the pulse transmission interval during deceleration, each pulse interval during the acceleration and the pulse interval during the constant speed And the data of each pulse interval at the time of deceleration are stored in the order of address numbers together with the shift flag indicating whether it is the data of the pulse interval at the time of acceleration and deceleration and the final flag indicating the data of the final pulse interval at the time of deceleration. A speed memory, a pulse number latch circuit for latching a step pulse number obtained by subtracting the number of pulse interval data during deceleration of the speed memory from the step pulse number input from the outside, and a pulse interval stored in the speed memory Of the data corresponding to that data A DMA control unit that sequentially outputs to the data bus in the order of the address number together with a flag and a final flag, and when the shift flag output to the data bus indicates the data of the pulse interval during acceleration and deceleration, the data of the next address number A first logic circuit for sending out a DMA request signal for reading out to the DMA control section, a data latch circuit for latching the data of the pulse interval sent out to the data bus, and a data latch circuit for latching the data latched in the data latch circuit. A data counter for counting the pulse intervals, a motor drive circuit for driving the stepping motor in rotation upon receipt of a drive pulse output from the data counter each time the timing of the time is completed, and a pulse number counter for counting the number of the drive pulses. When,
A pulse number matching circuit that sends the DMA request signal to the DMA control unit when the count value of the pulse number counter matches the number of pulses latched in the pulse number latch circuit,
A second logic circuit that outputs an interrupt signal for stopping the stepping motor drive when the final flag output to the data bus indicates data of the final pulse interval during deceleration. Drive.