JPH0734189B2 - Multiple data input / output control circuit - Google Patents

Description

The present invention relates to data input / output between central processing circuits (hereinafter referred to as “CPU”).

[Conventional technology]

To perform data input / output between CPUs, use a shared memory or use a parallel data input / output method that directly connects the buses, or convert parallel data to serial data on the transmission side and convert serial data to parallel data on the reception side. There is a serial data input / output method to convert to. It is widely known that the serial data I / O method is effective when the CPU processor and the system are separated from each other or when it is difficult to connect the bus due to the structural limitation of the system. ing. When performing data input / output that exceeds the processing capacity of the CPU processor, the communication control circuit (hereinafter referred to as "PCC") that executes the procedure for communication control and the exchange of data between the memory and PCC do not go through the CPU. Connect to the control circuit (hereinafter referred to as "DMAC")
A serial data input / output method is used in which continuous parallel data is serially converted without inputting and data is input / output.

Since the data input / output circuit connecting the above DMAC and PCC directly exchanges data with the memory, while the DMAC exchanges data with the PCC, the CPU does not have the right to use the bus. Cannot be done. Most of the CPUs suspend the execution of the program during this period and perform processing intermittently.

When performing data input / output with multiple PCCs at the same time, if each data input / output speed is sufficiently slower than the CPU processing speed, the CPU transfers data to / from each PCC in a time-sharing manner and synchronizes the PCCs with a program. Or, the DMAC is configured in a tree shape, the terminal DMAC and the PCC are connected, and a means for synchronizing by the DMAC is used.

[Problems to be solved by the invention]

In the conventional method, it is necessary to control synchronization between PCCs during data input / output by a program or a DMAC.

When the right to use the bus is changed to another input / output circuit for each data transfer and the data is input / output by multiple PCCs at the same time, the number of circuits that can perform the data input / output is inversely proportional to the data input / output speed.

When the bus usage right is changed to another input / output circuit for each data input / output, only one circuit can simultaneously perform data input / output, and the other must wait for the bus usage right. .

As described above, only a limited number of data can be input and output at the same time, and there is a drawback that control for synchronizing PCCs is required. Furthermore, when multiple PCCs simultaneously perform data input / output using the DMAC, the CPU remains in a halted state, reducing the processing capacity.

[Means for solving problems]

In order to solve such a problem, the present invention provides a bus cutoff means for disconnecting each communication control circuit from a bus, and each address has a different address, and each address is sequentially assigned following the address of the main memory and each communication is performed. A plurality of sub memories each connected to each bus on the control circuit side, and a control means for controlling the communication control circuit so that the sub memories can be accessed without being controlled by the central processing circuit when accessing the sub memories, The multiple data input / output control circuit is provided with a synchronous control means for individually controlling the bus cutoff means provided for each communication control circuit so as to synchronize with the processing operation of the central processing circuit.

[Action]

In the present invention, at the time of data transfer of the communication control circuit, the control means transfers data between the communication control circuit and the sub memory by using the occupied bus on the communication control circuit side of the bus cutoff means.

〔Example〕

An embodiment of the multiplex data input / output control circuit according to the present invention is shown in FIG. FIG. 2 is a memory map view seen from the CPU 1.

First, the configuration of this circuit will be described with reference to FIGS. 1 and 2.
In this circuit, as shown in FIG. 2, the memory is the main memory 3
And the sub memories 7 to 9 having addresses following the main memory 3. That is, the plurality of sub memories 7 to 9 have different addresses, and the addresses of the sub memories are, for example, the sub memory 7, the sub memory 8, and the sub memory 9 after the main memory 3.
The respective addresses are sequentially and successively assigned. In addition, this circuit is a PCC1 that inputs / outputs data to / from the data communication lines 20-22.
3 to 15, DMACs 10 to 12 as control means for controlling data exchange between the PCCs 13 to 15 and the sub memories 7 to 9 without going through the CPU 1, CPU 1
Bus disconnection circuits 4 to 6 as bus disconnection means for disconnecting the bus 16 from the PCCs 13 to 15 on the buses 17 to 19 on the PCC 13 to 15 side, DMAC
CPU with data input / output execution synchronization signals a, b, c from 10 to 12
It is composed of a bus cutoff control circuit 2 as a synchronous control means for outputting the bus cutoff control signals e, f, g to the bus cutoff circuits 4 to 6 in synchronization with the processing of 1.

Next, the operation of this circuit will be described with reference to FIG. Normal
CPU1 can access all memories and circuits through buses 16-19. When PCC13 ~ 15 start input / output of data, data input / output execution synchronization signals a, b, c
Is output to the bus cutoff control circuit 2 from.

The bus cutoff control circuit 2 is connected to the DMACs 10 to 12 and the bus 17 to
Since the CPU 1 may access the sub memories 4 to 6 of 19 in some cases, the bus 17 to 19 which is synchronized with the processing of the CPU 1 and which is connected to the DMACs 10 to 12 which output the data input / output execution synchronization signals a, b, and c
Bus shutoff circuit 4 between the bus 16 and the CPU 16
The bus cutoff control signals e, f, and g are output to (6) to (6).

The bus cutoff circuits 4 to 6 bring the buses 17 to 19 on the PCC 13 to 15 side into high impedance by the bus cutoff control signals e, f, and g. Then, by controlling the DMACs 10 to 12, the high impedance buses 17 to 19 are used, and the sub memories 7 to 9 and the PC are used.
Data is exchanged with the C13-15, and the PCC13-15 inputs / outputs data to / from the data communication lines 20-22.

On the other hand, the CPU 1 receives the data from the bus cutoff control circuit 2, knows the memory and the circuit that is performing the data input / output, and sets the data input / output so as not to access the memory and the circuit.

At the end of data input / output, the bus cutoff control circuit 2 receives the data input / output execution synchronization signals a, b, c from the DMACs 10 to 12,
The bus cutoff control signals e, f, g are output to the bus cutoff circuits 4 to 6 to release the cutoff, and the CPU 1 is notified of the release data.

〔The invention's effect〕

As described above, according to the present invention, bus disconnection means for disconnecting each communication control circuit from the bus, each address having a different address, each address is sequentially allocated following the address of the main memory, and each communication control circuit side has Each of the plurality of sub memories connected to the bus, the control means for controlling the communication control circuit so that the sub memory can be accessed without being controlled by the central processing circuit, and each communication control circuit. The central processing circuit can normally access all the circuits and the memory by providing the bus shut-off means provided in the central processing circuit and the synchronous control means for individually controlling the individual circuits so as to synchronize with the processing operation of the central processing circuit. When the data transfer of the communication control circuit is started, the bus can be disconnected from the central processing circuit by the bus interruption means in synchronization with the processing of the central processing circuit. At the time of data transfer, since the data can be transferred between the communication control circuit and the sub memory by the control means by using the occupied bus on the side of the communication control circuit of the bus cutoff means, the central processing circuit only when starting the data input / output. The effect of being able to perform data input / output up to the maximum data input / output speed at which the control means and communication control circuit can perform data input / output without having to synchronize with other circuits at all for subsequent data input / output. There is. Further, since the central processing circuit cannot be stopped by the control means, it is possible to access the circuits and memories other than the circuit for inputting / outputting data and the memory, and there is an effect that the reduction of the processing capacity does not occur. Further, since the other communication control circuits perform the same operation, there is an effect that data input / output can be performed simultaneously without being synchronized with the other communication control circuits.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of a multiplex data input / output control circuit according to the present invention, and FIG. 2 is a memory map view of a memory constituting the circuit as seen from a central processing circuit. 1 ... CPU, 2 ... Bus cutoff control circuit, 3 ... Main memory, 4-6 ... Bus cutoff circuit, 7-9 ... Sub memory, 10
〜12 …… DMAC, 13〜15 …… PCC, 16〜19 …… Bus, 20〜2
2 …… Data communication line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Miwa 3-20-4 Nishishinbashi, Minato-ku, Tokyo Inside Nippon Electric Engineering Co., Ltd. (56) References JP-A-56-153422 (JP, A)

Claims (1)

[Claims] 1. A multiple data input / output control circuit in which a central processing circuit, a main memory, and a communication control circuit connected to each communication line are connected by a bus to function as a unit, wherein each communication control circuit is separated from the bus. Shutting off means, a plurality of sub memories each having a different address, each address being sequentially allocated following the address of the main memory, and each being connected to each bus on the side of each communication control circuit, the communication control When each circuit accesses the sub memory, each control unit connected to each bus for controlling the sub memory so that the sub memory can be accessed without being controlled by the central processing circuit, and output from each of the control units. Based on the data input / output execution synchronization signal, the bus cutoff means provided for each communication control circuit is synchronized with the processing operation of the central processing circuit to connect the buses. A synchronous control means for controlling each of them to cut off is provided, and parallel processing is possible even when the plurality of communication control circuits simultaneously receive a data reception request from the line or simultaneously receive a data transmission request to the line. A multiple data input / output control circuit characterized by the above.