JPH0734213B2 - IC card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial field of application) The present invention has a built-in CPU, data memory, and the like, and is used as a single card for a calculator, time display, or inserted into a terminal. Regarding the IC card used by that.

(Conventional technology) Conventionally, a CPU, data memory, etc. were built in, a keyboard,
A multi-function IC card that has a display unit and is used by itself as a calculator, time display, etc. or by being inserted into a terminal has been developed.

In such an IC card, when inserting it into the terminal,
Input from the IC card keyboard is not considered,
Input / output is performed by the terminal.

However, in the multifunction card as described above, it is possible to input to the IC card from the keyboard of the IC card itself. Therefore, when inserted into the terminal, in a normal state, there is a possibility that the input from the keyboard may be incorrect by the input from the keyboard.

That is, there is no idea that the IC card itself has an input function, and therefore, when the IC card with a keyboard is inserted into the terminal, there is a drawback that an erroneous input is made from the keyboard.

(Problems to be Solved by the Invention) As described above, when the card is inserted into an external device, it eliminates the drawback of erroneous input and malfunction due to the input function of the card itself. It is to provide an IC card that can prevent input and malfunction.

[Structure of the Invention] (Means for Solving the Problems) The IC card of the present invention has a function of communicating with an external device via a contact portion by being inserted into the external device, and directly transmits data. In a keyboard having a plurality of keys for input and a control element for controlling each of the above parts, a specifying means for specifying the prohibition of the input by the keyboard when the keyboard is inserted into the external device, By the designation, a prohibiting unit that locks the keyboard unit to prohibit data input by the keyboard unit, and a first releasing unit that releases the locked state of the keyboard unit by the prohibiting unit when returned from the external device. , A timer which is activated when the input prohibition is designated by the designation means, and without being inserted into the external device. It comprises second releasing means for releasing the locked state of the keyboard portion by the prohibiting means when the timer measures a certain time.

(Operation) The present invention has a function of communicating with an external device via a contact part when inserted into an external device, and controls a keyboard part including a plurality of keys for directly inputting data and the above-mentioned parts. A control element for controlling the input of the keyboard by the specifying means when the keyboard is inserted into the external device, and by this specification, the keyboard is locked so that the input of data by the keyboard is prohibited. The lock state of the keyboard part by the prohibition means is released with the return from the external device, and it is activated when the input prohibition is specified by the specifying means without being inserted into the external device. When the timer counts a certain time, the locked state of the keyboard part by the above prohibition means is released. It is a thing.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, 10 is an IC card as a portable medium, which is a multi-function card having various functions. For example, the online function that is used with the terminal described later,
The IC card 10 has an offline function that operates independently and a waiting state in which only the clock is counted.

The offline function includes a calculator mode that can be used as a calculator, a time display mode that displays the time according to the clock used by the user, a time change mode that changes the time of the clock used by the user, an address, and a name. ,
There are an electronic book mode in which a telephone number or the like is registered or read out, or a shopping mode in which the IC card 10 is used as a credit card or a cash card.

On the surface of the IC card 10, a contact portion 11 arranged at a position conforming to the card standard, a keyboard portion 12 including 20 keys, and a display portion formed on the upper surface of the keyboard portion 12 and formed of a liquid crystal display element. 13, and a magnetism generating member 14 are provided.

The contact portion 11 is composed of, for example, a plurality of terminals 11a to 11h. The terminal 11a is for operating power supply voltage (+ 5V, Vcc), the terminal 11b is for grounding, the terminal 11c is for clock signal, the terminal 11d is for reset signal, and the terminals 11e to 11h are for data input / output.

The keyboard section 12 is composed of mode keys (M1, M2, M3, M4) 12a for designating a processing mode, a numeric keypad 12b, and four arithmetic operation keys (function keys) 12c.

The mode key 12a is for offline, that is, IC card 1
When processing is performed only by 0, processing for calculator mode (M1), time display mode (M2), electronic book mode (M3), or shopping mode (M4) is selected. Further, in the shopping mode, the processing corresponding to the type of card, that is, various credit cards, cash cards, etc., is selected in accordance with the combination of the M4 key and the numeric keypad 12b.

Also, by turning on the M2 and M3 keys at the same time,
The key lock state is selected. This key lock is performed when the IC card 10 is inserted into the terminal device 16, and prevents various modes from being selected by inserting a key in the keyboard unit 12 after the IC card 10 is inserted into the terminal device 16 and causing a malfunction. It is like this.

In the locked state, the locked state is released when the IC card 10 is not inserted into the terminal device 16 and a predetermined time has elapsed by the timer 32. As a result, the lock state is automatically released after a certain period of time elapses.Therefore, even if the lock command is erroneously input or the command is not inserted into the terminal device 16 after the command is input, the normal state is maintained. You can go back to.

Also, if inserted into the terminal 16 within the locked time, it continues the locked state regardless of the timer 32, the locked state in this case, when the IC card 10 is returned from the terminal 16, It is supposed to be released.

The display unit 13 is a 5 × 7 dot matrix with one digit
16-digit display.

The magnetism generating member 14 is embedded inside the IC card 10 in accordance with the track position of a magnetic card reader (magnetic head) on the reading side (not shown).

FIG. 3 shows the external appearance of the IC card reading / writing unit 16 used in a terminal that handles the IC card 10, such as a personal computer. That is, by connecting to the contact portion 11 of the IC card 10 inserted from the card insertion port 17, the data of the memory in the IC card 10 is read or the data is written in the memory.

The IC card reading / writing unit 16 is connected to the main body (not shown) of the personal computer by a cable.

The electric circuit of the IC card 10 is constructed as shown in FIG. That is, the contact portion 11, the communication control circuit 21, the reset control circuit 22, the power supply control circuit 23,
For example, a 3-volt internal battery (built-in power supply) 25, a battery check circuit 24 that checks whether the voltage value of the internal battery 25 is above a specified value, a clock control circuit 2
6, Oscillator 27 that outputs a signal with an oscillation frequency of 1 MHz, CPU for control (central processing unit) 2
8. A program ROM as a mask ROM that is composed of a read-only memory, stores a program that operates the CPU, and stores a load program that loads an externally supplied self-diagnosis program into the data memory 31.
(Memory unit) 29, program working memory 30, a non-volatile memory such as RAM, a data memory 31 for storing data, that is, a self-diagnosis program supplied from the external terminal 16 in a non-volatile state, processing operation A timer 32 used for clocking, a calendar circuit 33, a crystal oscillator for oscillation of a basic clock, and an oscillator 34 that constantly outputs a signal with an oscillation frequency (low frequency) of 32.768 KHZ, a display control circuit 35, Display driver 3 for driving the display 13
6, a keyboard interface 38 as a key input circuit of the keyboard section 12, and a magnetic field generating member control circuit 40 for controlling the magnetic field generating member 14.

Magnetic field generating member control for controlling the communication control circuit 21, the CPU 28, the ROM 29, the program working memory 30, the data memory 31, the timer 32, the calendar circuit 33, the display control circuit 35, the keyboard interface 38, and the magnetic field generating member 14. The circuit 40 is adapted to be connected by the data bus 20.

The communication control circuit 21 converts a serial input / output signal supplied from the terminal device 16 through the contact portion 11 into parallel data and outputs the parallel data to the data bus 20 during transmission, and the transmission data bus 20 during transmission. The parallel data supplied from the
It is designed to be output to the terminal device 16 via. In this case, the format contents of the conversion are the above-mentioned terminal 16 and
It is defined as the IC card 10.

The reset control circuit 22 is adapted to generate a reset signal and activate the CPU 28 when it comes online.

The power supply control circuit 23 is switched to drive from the internal battery 25 to drive to an external power supply after a predetermined time has passed after a predetermined time has passed when the power supply control circuit 23 is turned on, and when it is offline, that is, the external voltage. When the battery power drops, the drive from the external power supply is switched to the drive by the internal battery 25.

In the offline mode in which the card operation is performed by the internal battery 25, the clock control circuit 26 stops the oscillation circuit 67 that outputs a signal of 1 MHz oscillation frequency (high frequency), which will be described later, during standby, that is, during key input standby, and CPU28
The supply of the clock to is also stopped, and the system stands by in a completely stopped state. Further, the clock control circuit 26 outputs the clock clock as the clock for the CPU 28 during 500 to 600 msec until stable oscillation is performed when the oscillation circuit 67 is restarted from the stopped state, and the first input key The processing of is performed.

Information corresponding to a plurality of contracted credit cards (company) and information corresponding to a cash card are recorded in the data memory 31, and the M4 key and the numeric keypad are used.
It is designed to be read according to the type of card by the combination of 12b. The above information has the same contents as the information recorded on the conventional magnetic stripe for each card.

The calendar circuit 33 has a display clock whose setting can be freely changed by the card holder, and a transaction clock which is set to the world standard time when the card is issued and cannot be changed thereafter. ing.

Further, in the data memory 31, data such as a personal identification number for a manufacturer, an issuer, a user, etc. is recorded in an area which is not erased.

The display unit control circuit 35 converts the display data supplied from the CPU 28 into a character pattern by using a character generator (not shown) configured by an internal ROM, and a display unit 36 by using a display driver 36. It is something to display.

The keyboard interface 38 is the keyboard unit 12
Convert to a key input signal corresponding to the key input in
It is output to U28 and is key-locked when it is inserted into the terminal 16. As a result, the locked state is not released until a fixed time has passed or the terminal 16 returns the locked state.

When the shopping mode and the card type are designated, the magnetic field generating member control circuit 40 is configured so that the data and the reading device supplied from the data memory 31 via the data bus 20 correspond to the card type. According to the drive rate corresponding to manual reading or automatic reading, by controlling the drive of the magnetic generation member 14 to output magnetic information,
It is in the same state as a conventional magnetic stripe exists.

The power supply control circuit 23 will be described in detail with reference to FIG. That is, inverter circuits 51, 54, 55, counter 52, D-type flip-flop circuit (FF circuit) 53, MOSFET
The semiconductor switches 56 and 58, the diode 57, and the internal battery 25.

The count value of the counter 52 is a value that is not affected by chattering of the external power supply. The diode 57 is
Power supply voltage Vout protection, external power supply voltage Vcc
When the power supply voltage drops before the semiconductor switch 56 turns on,
Even if Vcc drops below the drive voltage of the memory, the internal battery 25 protects the power supply voltage Vout from dropping.

With such a configuration, the operation will be described with reference to the timing chart shown in FIG. That is, IC card 10
Is not connected to the terminal 16 at the contact portion 11, the semiconductor switch 56 is turned on, so that the power supply voltage of the internal battery 25 is applied to each portion as the output Vout of the power supply control circuit 22 via the semiconductor switch 56. To be done.

When the IC card 10 is connected to the terminal 16 through the contact section 11, the power supply voltage Vcc from the outside is supplied to the gate of the semiconductor switch 58 and the clock signal CLK is supplied.
Is the clock terminal of the counter 52 via the inverter circuit 51
supplied to ck. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the output terminal Qn
The FF circuit 53 is set by the output of. The set output Q of the FF circuit 53 causes the gate of the semiconductor switch 58 to "0".
A signal is supplied, a "1" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 56 is turned off. Therefore, the external power supply voltage Vcc
Outputs Vout of the power supply control circuit 22 via the semiconductor switch 58.
Is applied to each part.

In addition, when the power supply voltage Vcc drops from the outside when returning from the online state to the offline state, the reset control circuit 2
The reset signal is output from 2. Thus, the reset signal resets the counter 52 and the FF circuit 53. Then, the "1" signal is supplied to the gate of the semiconductor switch 58, the "0" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned off, and the semiconductor switch 56 is turned on. Therefore, the power supply voltage of the internal battery 25 is applied to each part as the output Vout of the power supply control circuit 22 via the semiconductor switch 56.

The clock control circuit 26 will be described in detail with reference to FIG. That is, the stop signal HALT from the above CPU 28
Is supplied to the clock input terminal ck of the FF circuit 62. The set output of the FF circuit 62 is supplied to the data input terminal D of the FF circuit 63, and the CPU 28 is connected to the clock input terminal ck of the FF circuit 63.
Is supplied with the machine cycle signal M1. Above FF circuit
62 and 63 are for stop mode timing. FF above
The set output of the circuit 63 is supplied to the data input terminal D of the FF circuit 64, and the clock input terminal ck of the FF circuit 64 is supplied with the 32.763 KHZ clock clock from the calendar circuit 33. The reset output of the FF circuit 64 is supplied to the data input terminal D of the FF circuit 65, and the clock input terminal ck of the FF circuit 65 is supplied with the 32.763 KHZ clock clock from the calendar circuit 33. The FF circuit 65 is for stopping clock oscillation. The set output of the FF circuit 65 is supplied to one end of a NAND circuit 66, and an oscillation circuit 67 is connected between the output end of the NAND circuit 66 and the other end.

Further, the key input interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are OR circuits.
It is supplied to the reset input terminal R of the FF circuits 62, 63 and 64 via 61 and to the set input terminal S of the FF circuit 65.

The oscillation circuit 67 is composed of the oscillator 27 having the oscillation frequency of 1 MHz, the resistor 68, and the capacitors 70 and 71.

The output of the NAND circuit 66 is output via the inverter circuit 72.
It is supplied to the clock input terminal ck of the FF circuit 74 and also supplied to one end of the NAND circuit 75 via the inverter circuits 72 and 73.

The reset signal from the reset control circuit 22 is FF.
It is supplied to the set input terminal S of the circuit 76, and the output of the OR circuit 84 described later is supplied to the clock input terminal ck of the FF circuit 76. A clock selection signal from the CPU 28 is supplied to the data input terminal D and the reset input terminal R of the FF circuit 76. The set output of the FF circuit 76 is the FF circuit.
The clock input terminal ck of the FF circuit 77 is supplied with a clock clock of 32.763 KHZ from the calendar circuit 33. The set output of the FF circuit 77 is supplied to one end of a NAND circuit 79.
A clock for 32.763 KHZ clock from the calendar circuit 33 is supplied to the other end of 79 via an inverter circuit 78. The output of the NAND circuit 79 is supplied to one end of the NAND circuit 80.

The reset output of the FF circuit 77 is supplied to the data input terminal D of the FF circuit 74, and the set output of the FF circuit 74 is supplied to the other end of the NAND circuit 75. The FF circuit 74 is for clock switching.

The outputs of the NAND circuits 75 and 79 are supplied to the NAND circuit 80, the output of the NAND circuit 80 is supplied to the clock input terminals ck of the FF circuits 81 and 83, and the FF circuit 81 is connected to the data input terminals of the FF circuit 81. The set output of 63 is supplied via the inverter circuit 82.

The set output of the FF circuit 81 and the reset output of the FF circuit 83 are output to the clock input terminal ck of the FF circuit 76 via the OR circuit 84.

The set output of the FF circuit 83 is supplied to one end of a NAND circuit 86, and the output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85. The output of the NAND circuit 86 is used as a clock signal by the CPU2.
It is designed to be output to 8.

The operation in such a configuration will be described. First, the stopped state will be described. That is, "1" is supplied from the CPU 28 as a clock selection signal. This allows
FF circuits 76 and 77 are set. As a result, the clock for clock (32.768KHZ) is output from the inverter circuit 78 and NAND circuit 7
FF circuits 81, 82 and inverter circuit 8 via 9, 80
Guided by 5.

Next, the restart from the stopped state will be described. That is, a key input interrupt signal is supplied from the CPU 28.
Then, the FF circuits 62, 63 and 64 are reset and the FF circuit 65 is set. The set output of the FF circuit 65 enables the oscillation circuit 67. As a result, the oscillation circuit 67 restarts oscillation.

Further, due to the reset of the FF circuit 63, “1” is supplied to the data input terminal D of the FF circuit 81. As a result, the FF circuits 81 and 83 are set by the output of the NAND circuit 80, and the gate of the NAND circuit 86 is opened. Therefore, the clock clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86.

At this time, until the oscillation circuit 67 stably oscillates, it is usually 500 to 6
00msec is required. As a result, the CPU 28 outputs “0” as the clock selection signal 500 to 600 msec after the key input interrupt signal is output, and the data input terminal D of the FF circuit 76.
Supply to. This resets the FF circuits 76 and 77,
The reset output of the FF circuit 77, that is, the “1” signal is supplied to the data input terminal D of the FF circuit 74.

At this time, the clock (1 MHz) from the oscillator circuit 67 is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 sets, and the gate of the NAND circuit 75 is opened by this set output. As a result, the oscillator circuit 67
The clock (1MHZ) by the inverter circuit 72, 73, NAND circuit 75, 80, inverter circuit 85, and NAND circuit
The data is output to the CPU 28 through the 86.

Thus, by setting the clock selection signal to "0", the FF circuit 74 is synchronized and the clock clock is switched to the high-speed processing clock.

Next, a case in which the processing is terminated and brought into a stopped state (standby state) will be described. That is, by setting the clock selection signal to "1", the FF circuits 76 and 77 set and
The set output of the circuit 77, that is, the "1" signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is open. Therefore, the clock for the clock is the inverter circuit 78 and the NAND circuit.
The data is output to the CPU 28 through the 79, 80, the inverter circuit 85, and the NAND circuit 86 in order.

As a result, the clock for clock is output to the CPU 28 again.

Then, a stop signal is supplied from the CPU 28 to the data input terminal D of the FF circuit 62. Then, the FF circuit 62 sets, and the set output is supplied to the data input terminal D of the FF circuit 63. Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and the "0" signal is supplied to the data input terminal D of the FF circuit 81. As a result, the set output of the FF circuit 63
After sending two pulses by the circuits 81 and 83, the gate of the NAND circuit 86 is closed to stop the output of the clock to the CPU 28. As a result, the CPU 28 is stopped.

Further, the set output of the FF circuit 63 is sent by the FF circuits 64 and 65 for two pulses, and then the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

As a result, the oscillator circuit 67 is stopped after the output of the clock to the CPU 28 is stopped.

As described above, the clock control circuit 26 effectively switches between the clock clock and the 1 MHz clock in order to cover the rise of the crystal oscillation by the oscillator 27.

The calendar circuit 33 will be described in detail with reference to FIG. That is, by dividing the oscillation output of the 32.768 KHZ oscillator 34, a frequency dividing circuit 91 that outputs a signal every second from the output terminals a and b, and a signal from the output terminal a of this frequency dividing circuit 91 is counted. By doing so, a counter 92 that outputs a signal every 10 seconds, a counter 93 that outputs a signal from this counter 92, and a counter 93 that outputs a signal every 60 seconds, that is, one minute, and a signal from this counter 93 are counted. Therefore, the counter 94 that outputs a signal every 10 minutes, the counter 95 that outputs a signal from this counter 94, and the counter 95 that outputs a signal every 60 minutes, that is, an hour, the counter 95 that outputs a signal Thus, a counter 96 that outputs a signal every 24 hours, that is, a day, a counter 97 that outputs a signal every 10 seconds by counting the signal from the output terminal b of the frequency dividing circuit 91, signal By counting, a counter 98 that outputs a signal every 60 seconds, that is, every minute, a counter 99 that outputs a signal from this counter 98 every 10 minutes, and a signal from this counter 99 The counter 100 outputs a signal every 60 minutes, that is, every hour, and the counter 101 outputs a signal every 24 hours, that is, every day by counting the signal from the counter 100.

Here, the counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 101 configure a display clock that counts seconds, minutes, and hours. The contents of the counters 97 to 101, that is, the count value can be changed by the keyboard unit 12, and the contents of the counters 92 to 96, that is, the count value, can be changed.
It cannot be changed by 12.

In addition, the date and day of the week, the counter 96 every 24 hours,
An interrupt request is output to the CPU 28 in response to a signal from 101. As a result, the CPU 28 uses the data memory 31 to change the date and the day of the week in the corresponding area. Further, as shown in FIG. 9, the two clocks have the phase of the reference clock of 1 second shifted, so that the interrupts are not generated at the same time.

As shown in FIG. 1, the keyboard interface 38 is composed of a row selector 120, a column selector 121, and a keyboard controller 122.

That is, when the key lock signal is supplied from the CPU 28 to the keyboard control unit 122, the lock signal is sent to the row selector 120.
Supply to. As a result, the row selector 120 is fixed to “0”, that is, the row side and the column side are set to the same signal level, so that the keyboard section 12 is locked.

Alternatively, the keyboard 12 may be locked by fixing the column selector 121 to “0”.

The magnetism generating member control circuit 40 will be described in detail with reference to FIG. That is, from the CPU 28 to the data bus 2
Command data supplied via 0 is FF for command
It is supplied to the circuit 110. The FF circuit 110 is composed of four FF circuits, and according to the command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track from the output end 110a, a start signal from the output end 110b, or The output terminal 110c outputs a clock selection signal corresponding to the drive rate for the second track, and the output terminal 110d outputs a start signal. FF circuit 110 above
A command write start signal from the CPU 28 is supplied to the clock input terminal cp of. The clock selection signal corresponding to the driving rate indicates whether the type of terminal is manual reading or automatic reading.

The clock selection signal output from the output end 110a of the FF circuit 110 is supplied to the input end s of the selection circuit 111. A signal with a frequency of 8 KHZ is supplied from an oscillator (not shown) to the input terminal A of the selection circuit 111, and a signal with a frequency of 4 KHZ is supplied from an oscillator (not shown) to the input terminal B. The selection circuit 111 is responsive to the clock selection signal from the FF circuit 110 to input terminal A when the type of the terminal is manual reading.
Is selected and output from the output terminal Y. When the type of the terminal is automatic reading, the signal at the input terminal B is selected and output from the output terminal Y.

The start signal output from the output terminal 110b of the FF circuit 110 and the output of the selection circuit 111 are the timing circuit 1
Supplied to 12. The timing circuit 112 generates a 7-ary clock and supplies it to the clock input terminal cp of the parallel / serial conversion circuit 115, and uses the first clock as a load signal for the load input terminal L of the parallel / serial conversion circuit 115.
Supply to. Further, the timing circuit 112 selects the data “0” clock and the data “1” clock by the selection circuit 116.
Is being supplied to.

The magnetic data supplied from the CPU 28 via the data bus 20 (depending on the type of card selected) is supplied to the data latch circuit 113. The data latch circuit 113 is supplied to the data write start signal from the CPU 28. Is being supplied. The data latch circuit 113 is the CPU 28
When a data write start signal is supplied from the device, the 7-bit magnetic data supplied from the data bus 20 is latched.

The data latched by the data latch circuit 113 is supplied to the data input terminal IN of the 7-bit parallel / serial conversion circuit 115. Parallel / serial conversion circuit 11
The reference numeral 5 loads the data from the data latch circuit 113 by the supplied load signal, shifts the loaded data in order, and converts the data into 1-bit signals (“1” signal or “0” signal). And output it.

The output of the parallel / serial conversion circuit 115 is supplied to the input terminal s of the selection circuit 116. When the "1" signal is supplied to the input terminal s, the selection circuit 116 selects and outputs the data "1" clock supplied from the timing circuit 112, and the "0" signal is input to the input terminal s. When supplied, the data "0" clock supplied from the timing circuit 112 is selected and output. Selection circuit 11 above
The output of 6 is supplied to the J-KFF circuit 117.
The set output and reset output of 117 are supplied to the driver 118.

The driver 118 generates a magnetic field by driving the magnetic field generating member 41a according to the signal from the FF circuit 117. For example, when the FF circuit 117 is set, a magnetic field as shown by an arrow c is generated, and when it is reset, a magnetic field as shown by an arrow d is generated.

The timing chart of the main part of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG. 12, the clock cycle has a ratio of 1: 2 with respect to the data “1” and “0”. By operating the J-KFF circuit 117 in the inversion mode with this clock, the "1" and "0" signals of the format required as magnetic data are obtained, and the magnetic generation member is obtained.
It is designed to drive 41a.

The data write start signal from the CPU 28 is inverted and supplied to the set input terminal of the FF circuit 114 for sky detection, and the reset input terminal of the FF circuit 114 is supplied with the first clock from the timing circuit 112. Inverted and supplied. As a result, when the data of the data latch circuit 113 is loaded into 115, the FF circuit 114
Is set, and the set output of the FF circuit 114, that is, the buffer empty signal is supplied to the CPU 28.

As a result, the CPU 28 determines that the next data can be set and outputs the next data to the data latch circuit 113. As described above, the CPU 28 senses the output of the empty detection FF circuit 114, sequentially sets the data, outputs all the data, and then turns off the command write start signal and the data write start signal. There is. As a result, the generation of signals by the timing circuit 112 is stopped, and the operation ends.

Each of the circuits 111 to 118 is a circuit for the first track, and the circuit for the second track is also the selection circuit 11 in the same manner as above.
9, a timing circuit 120, a data latch circuit 121, an empty detection FF circuit 122, a parallel / serial conversion circuit 123, a selection circuit 124, a J-KFF circuit 125, and a driver 126. However, the points where the timing circuit 120 operates in the quinary system are different.

As described above, the magnetism generating member control circuit 40 generates the magnetic field in accordance with the magnetic data of the predetermined credit card or cash card selectively read from the data memory 31 to generate the magnetic field on the reader side. The head (not shown) is supplied with the same signal as when the conventional magnetic stripe is read.

Next, the operation in such a configuration will be described. First, the offline function used by the card alone will be described. That is, when the calculator mode is specified by the mode key 12a, that is, the M1 key, the numeric keypad 12b and the four arithmetic keys 1
Can be used as a calculator with 2c.

When the time display mode is specified by pressing the mode key 12a, that is, the M2 key, the CPU 28 causes the calendar circuit 3
Seconds from the counter 97, ~ 101 in 3 to the display clock,
The minutes and hours are read out, and the year, month, day, and day of the week for the display clock are read out from the data memory 31, converted into the specified format, and output to the display control circuit 35. As a result, the display control circuit 35 converts it into a character pattern using an internal character generator (not shown) and displays it on the display 13 using the display driver 36.

When the electronic book mode is designated by the mode key 12a, that is, the M3 key, the CPU 28 reads out the address, name, telephone number, etc. stored in the data memory 31, and displays the display section 13
Display with. Moreover, when the above-mentioned address, name, etc. are registered in the electronic book, for example, the ten keys 12b are used. That is, "A" is "1, 1", "B" is "1, 2",
By inputting "1, 3" for "C", "2, 1", etc. for "D", designation is possible.

Further, when the shopping mode is designated by the mode key 12a, that is, the M4 key, the type of the contract credit card or the cash card and the type of the output terminal, that is, the manual reading or the automatic reading are selected by the ten key 12b. Then, the CPU 28 reads the data (72 characters) corresponding to the selected credit card or cash card from the data memory 31, and outputs it to the magnetism generating member control circuit 40. Further, the CPU 28 outputs a drive rate corresponding to the selection of the manual type or the automatic type to the magnetic field generation member control circuit 40. Further, the CPU 28 outputs command data, a command write start signal, and a data write start signal to the magnetism generating member control circuit 40.

As a result, the magnetism generating member control circuit 40 generates a magnetic field corresponding to the magnetic data of the credit from the magnetism generating member 41a to read the conventional magnetic stripe on the magnetic head (not shown) on the reader side. The same signal is supplied as in the case. As a result, it can be used as a conventional credit card in the shopping mode.

Next, the online function used by inserting the IC card 10 into the terminal 16 will be described with reference to the flowchart shown in FIG. That is, first, the M2 key and the M3 key are turned on at the same time (ST1). Then, the CPU 28 determines that the key is locked, and sends the key lock signal to the keyboard control unit.
Output to 122. As a result, the keyboard control unit 122 supplies the lock signal to the row selector 120. Row selector 1
20 is fixed to "0", the signal levels on the low side and the serum side become the same, and the keyboard section 12 is locked. At this time, the CPU 28 also starts the timer 32 (ST2).

Then, the IC card 10 is inserted into the insertion slot 17 of the terminal 16 (ST3). If the IC card 10 is not properly inserted and returned at the time of this insertion, or if the IC card 10 is not inserted (ST4), the CPU 28 outputs an unlock signal to the keyboard control unit 122 due to the time up of the timer 32. As a result, the keyboard control unit 122 causes the row selector to output "1" and unlocks the keyboard unit 12 (ST9).

When the IC card 10 is successfully inserted into the terminal device 16 (ST4), the connection part inside the terminal device 16 and the contact part 11 of the IC card 10 are connected. As a result, when the power supply voltage from the outside is supplied via the contact portion 11, the power supply control circuit 23 switches the driving from the internal battery 25 to the driving of the power supply voltage from the outside, as described above. Further, the reset control circuit 22 generates a reset signal and activates the CPU 28. After this startup, if the CPU 28 confirms that it is operating online, it stops the timer 32 operation (ST
5) Perform online processing according to the contents of program ROM 29 (ST6). As the online processing, data is updated between the terminal 16 and the IC card 10 to exchange data or write new data in the IC card 10. After the completion of this online processing, the terminal device 16 returns the IC card 10 from the insertion slot 17. At this time, the CPU 28 outputs a lock release signal to the keyboard control unit 122. As a result, the keyboard control unit 122
Causes the row selector to output "1" and unlocks the keyboard section 12 (ST8).

As mentioned above, when inserting the IC card into the terminal,
By inputting a command from the keyboard to bring the keyboard into a locked state, the key is locked, and the locked state is not released after a certain period of time has passed or until the terminal returns. As a result, it is possible to prevent an erroneous input on the keyboard when the device is inserted into the terminal device, or prevent an erroneous operation due to the erroneous input, resulting in stable operation.

In the above embodiment, the key lock is designated by turning on the M2 key and the M3 key at the same time, but the key lock may be designated by one or a plurality of other keys. Further, although the IC card is used, the present invention is not limited to this, as long as it has a data memory and a control element and selectively inputs / outputs from the outside, the shape is not a card shape, but another shape such as a bar shape. It may have a shape.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide an IC card capable of preventing erroneous input and erroneous operation when the card is inserted into an external device.

[Brief description of drawings]

The drawings are for explaining one embodiment of the present invention. FIG. 1 is a diagram showing a configuration of a keyboard interface, FIG. 2 is a plan view showing a configuration of an IC card, and FIG. 3 is a terminal handling an IC card. FIG. 4 is a diagram showing a general configuration of an electric circuit of an IC card, FIG. 5 is a diagram showing a configuration example of a power supply control circuit, and FIG. 6 is a diagram showing an operation of a main part in FIG. 7 is a diagram showing the configuration of the clock control circuit, FIG. 8 is a schematic configuration block diagram of the calendar circuit, FIG. 9 is a diagram showing the output timing of the signal from the frequency dividing circuit, and FIG. Shows a configuration example of the magnetic generation member control circuit, FIGS. 11 and 12 are timing charts for explaining the operation of the main parts in FIG. 10, and FIG. 13 is a case where an IC card is inserted into the terminal. 5 is a flowchart for explaining the operation of FIG. 10 …… IC card (portable medium), 11 …… contact part, 12 …… keyboard part (input means), 13 …… display part (display means), 14 …… magnetism generating member, 16 …… terminal ( External device), 21 ... communication control circuit, 23 ... power supply control circuit,
25 …… Internal battery, 26 …… Clock control circuit, 27 ……
Oscillator, 28 ... CPU (control element), 31 ... Data memory, 33 ... Calendar circuit, 34 ... Oscillator, 38 ... Keyboard interface, 40 ... Magnetic generation member control circuit (driving means), 67 ... Oscillation circuit, 120 ... Row selector, 121 ... Column selector, 122 ... Keyboard control unit.

Claims (1)

[Claims] 1. A keyboard part having a function of communicating with the external device via a contact part when inserted into an external device, and a keyboard part consisting of a plurality of keys for directly inputting data, and a control for controlling each part. Have elements
In the IC card, when it is inserted into the external device, a specifying means for specifying prohibition of input by the keyboard part, and by specifying this specifying means, the keyboard part is locked and data input by the keyboard part is prohibited. Prohibiting means, a first releasing means for releasing the locked state of the keyboard portion by the prohibiting means upon being returned from the external device, and a timer activated when the input prohibition is designated by the designating means. And an second release means for releasing the locked state of the keyboard portion by the prohibiting means when the timer measures a certain time without being inserted into the external device.