JPH0734440B2 - Wiring forming method in semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method in a semiconductor device, and more particularly to a method for forming wiring on a substrate by a lift-off method.

<Prior Art> Conventionally, a so-called lift-off method is used, in which a wiring metal is vapor-deposited using a resist pattern and then the metal on the upper surface thereof is removed together with the resist pattern to leave the wiring metal in a desired shape on the substrate. The wiring forming method is frequently used.

Conventionally, as the wiring forming method by the lift-off method, the wiring metal (13) is vapor-deposited to a predetermined thickness in a state where the resist pattern (12) is formed on the surface of the substrate (11), and then, together with the resist pattern (12) A method of removing the wiring metal (13) on the upper surface (see FIG. 2), the wiring metal (23) having a predetermined thickness while the resist pattern (22) having an inverted trapezoidal cross section is formed on the surface of the substrate (21). A method of depositing and then removing the resist pattern (22) as well as the wiring metal (23) on the top surface (Fig. 3 and December 1985, Semiconductor & Integrated Circuit Technology, 29th Symposium Proceedings "LMR-UV Exposure characteristics of reflective aligners "
After the spacer layer (34) is formed on the surface of the substrate (31), the resist pattern (32) is formed, and the spacer layer (34) is etched corresponding to the resist pattern (32). A method of side-etching the layer (34), vapor-depositing the wiring metal (33) to a predetermined thickness in this state, and then removing the wiring metal (33) on the upper surface thereof together with the resist pattern (32) (Fig. 4, and 1981 National Conference on Electronics and Communications, Semiconductor and Materials Division, p. 130 "GaAs IC
Double-layer wiring technology ”) and the first resist pattern (4
2), the SiO ₂ film (45), and the second resist pattern (4
6) is formed in this order to form a second resist pattern (46)
Then, the first resist pattern (42) is side-etched, the wiring metal (43) is vapor-deposited to a predetermined thickness in this state, and then the resist pattern (42) and the upper layer portion thereof are formed. A method of removal (see Figure 5) was provided.

<Problems to be Solved by the Invention> In the above-described wiring forming method, burrs are generated on the upper side of the wiring due to the influence of resist sag (see FIG. 2B), and then interlayer insulation is performed. In this case, there is a problem that it may cause a dielectric breakdown, resulting in a decrease in the yield of the semiconductor device, and a problem that it is difficult to planarize in a state where interlayer insulation is applied.

In the above-mentioned wiring forming method, since the dimensional accuracy of the inverted trapezoidal resist pattern (22) cannot be improved so much, there is a problem that the wiring forming accuracy is lowered. When forming the wiring for the electrodes, it becomes difficult to secure an accurate relative position with respect to the source electrode and the drain electrode. In addition, there is a problem that planarization is difficult when the interlayer insulation is applied.

In the above-mentioned wiring forming method, since the side etching causes a considerably wide and deep groove to be formed between the wiring metal (33) and the spacer layer (34), interlayer insulation is performed. There is a problem that it becomes difficult to flatten in the state.

The above-described wiring forming method has a problem in that not only the wiring forming process is complicated, but also planarization is difficult in a state where interlayer insulation is performed.

Further, in any of the above cases, there is a problem that it is difficult to planarize in a state where the interlayer insulation is applied. This problem is that the multilayer structure is adopted in order to improve the integration degree of the semiconductor device in the future. In that case, it can cause a wire break or a short circuit, and cannot be ignored.

<Object of Invention> The present invention has been made in view of the above problems,
An object of the present invention is to provide a wiring forming method for a semiconductor device, which can form an accurate wiring pattern without being affected by resist sagging and can easily achieve planarization in a state where interlayer insulation is applied. I am trying.

<Means for Solving the Problems> In order to achieve the above object, the wiring forming method of the present invention has a first spacer layer that is difficult to be wet-etched and a second spacer that is easily wet-etched on a substrate. After the layers are formed in this order, dry etching is performed based on a predetermined resist pattern to vertically etch the above two layers, and then wet etching is performed to side etch the second spacer layer, and then wiring is performed. A desired wiring pattern is obtained by depositing metal and removing the resist pattern.

However, both spacer layers may be SiN films formed under mutually different forming conditions.

<Operation> According to the above wiring forming method, the first spacer layer formed on the substrate that is not easily wet-etched and the second spacer layer that is easily wet-etched are formed based on a predetermined resist pattern. The above two layers can be vertically etched by performing dry etching, and then only the second spacer layer can be side-etched by performing wet etching, and then a wiring metal can be deposited to obtain a desired wiring pattern. ,As a result,
Since a narrow groove and a shallow groove are formed only between the second spacer layer and the wiring metal, a highly accurate wiring pattern can be formed without being affected by the sagging of the resist.

Further, even when both spacer layers are SiN films formed under mutually different forming conditions, the same operation as described above can be performed.

<Examples> Hereinafter, detailed description will be given with reference to the accompanying drawings illustrating examples.

FIG. 1 is a process drawing showing an embodiment of the wiring forming method of the present invention.

First, on the surface of the substrate [1], a first spacer layer [2] that is difficult to be wet-etched, a second spacer layer [3] that is easily wet-etched, and a resist pattern [2] are formed in this order (first (See Fig. 1A).

Then, dry etching is performed using the resist pattern [4] as a mask to vertically etch both spacer layers [2] and [3], and both spacers are placed in a region corresponding to the opening of the resist pattern [4]. The layers [2] and [3] are removed (see FIG. 1B).

Then, wet etching is performed to perform side etching only on the second spacer layer [3] (see FIG. 1C).

Then, the wiring metal is deposited to a predetermined thickness (thickness approximately equal to the sum of the thicknesses of the two spacer layers) to form the wiring pattern [5] in the opening of the first spacer layer [2], and to leave the remainder. A wiring metal layer [6] having a predetermined thickness is formed on the upper surface of the resist pattern [4] in the area (1) (see FIG. 1D).

Therefore, after that, by removing the wiring metal [6] together with the resist pattern [4], as shown in FIG. 1E, a width is formed between the second spacer layer [3] and the wiring pattern [5]. A narrow and shallow groove [7] is to be formed, and in the state where the interlayer insulation (8) is applied, FIG.
The surface can be almost planarized as shown in FIG.

Explaining in more detail based on a specific example, a first spacer layer [2] is formed on the surface of the substrate [1] by forming a SiN film with a thickness of 3,000 Å by a plasma CVD method,
Then, plasma CV is formed on the surface of the first spacer layer [2].
A second spacer layer [3] is formed by forming a SiN film with a thickness of 2,000 Å by the D method. However, both of the above SiN
In forming the film, the first spacer layer [2] which is different in resistance to HF (hydrofluoric acid) by changing the forming conditions to each other and which is not easily wet-etched by HF
And a second spacer layer [3] that is susceptible to HF wet etching (“Characteri
zation of Plasma Silicon Nitride Layers "WAPClaa
ssen, WGJN Valkenburg, FHPMHabraken, and Y.Ta
mminga; J.El; ectrochem.Soc.: SOLID-STATESCIENCE AND
TECHNOLOGY vol.130, No.12 December 1983).

Then, in a state where the resist pattern [4] is formed on the surface of the second spacer layer [3], both spacer layers [2] [3] are formed by reactive ion etching using CF ₄ gas.
Is vertically etched to expose the substrate [1] at a portion corresponding to the opening of the resist pattern [4].

Then, wet etching is performed for several tens of seconds using buffered hydrofluoric acid (HF: H ₂ O = 1: 10) to side etch only the second spacer layer [3] by a predetermined amount. However, the side etching amount is determined based on the buffering degree of buffered hydrofluoric acid, the time required for wet etching, and the resistance of the second spacer layer [3], and can be controlled with high accuracy.

Then, Au was deposited as a wiring metal to a thickness of 4,000 liters, and then the resist pattern [4] and the Au layer thereon were removed, whereby wiring could be formed on the surface of the substrate [1].

Then, by performing interlayer insulation on the semiconductor device obtained as described above, the surface of the interlayer insulation layer could be flattened.

The present invention is not limited to the above-described embodiment, and for example, the first spacer layer [2] and the second spacer layer [3] can be formed of different materials. The wet etching conditions can be different from those in the above-described embodiment, and various design changes can be made within the range not changing the gist of the present invention.

<Effects of the Invention> As described above, according to the present invention, the spacer layer has a two-layer structure, and when both spacer layers are masked with a resist pattern, dry etching is performed, and then only the upper spacer layer is subjected to wet etching. After that, since the wiring metal is vapor-deposited, an accurate wiring pattern can be formed without being affected by the sagging of the resist, and the surface can be flattened in the state where the interlayer insulation is applied. It has the unique effect of being able to do it.

[Brief description of drawings]

FIG. 1 is a process drawing for explaining an embodiment of the wiring forming method of the present invention, and FIGS. 2 to 5 are intermediate process drawings showing a conventional example. [1] ... substrate, [2] ... first spacer layer, [3] ... second spacer layer, [4] ... resist pattern, [5] ...
Wiring pattern

Claims (2)

[Claims] 1. A first spacer layer that is not easily wet-etched and a second spacer layer that is easily wet-etched are formed in this order on a substrate, and then dry etching is performed based on a predetermined resist pattern. A method of forming a wiring in a semiconductor device, which comprises vertically etching the above-mentioned two layers, then side-etching the second spacer layer by performing wet etching, and then vapor-depositing a wiring metal to remove the resist pattern. . 2. A wiring forming method in a semiconductor device according to claim 1, wherein both spacer layers are SiN films formed under mutually different forming conditions.