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JPH0734448B2 - Semiconductor device mounting method - Google Patents
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JPH0734448B2 - Semiconductor device mounting method - Google Patents

Semiconductor device mounting method

Info

Publication number
JPH0734448B2
JPH0734448B2 JP61306924A JP30692486A JPH0734448B2 JP H0734448 B2 JPH0734448 B2 JP H0734448B2 JP 61306924 A JP61306924 A JP 61306924A JP 30692486 A JP30692486 A JP 30692486A JP H0734448 B2 JPH0734448 B2 JP H0734448B2
Authority
JP
Japan
Prior art keywords
semiconductor device
fine particles
circuit board
solder fine
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61306924A
Other languages
Japanese (ja)
Other versions
JPS63158845A (en
Inventor
幸男 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61306924A priority Critical patent/JPH0734448B2/en
Publication of JPS63158845A publication Critical patent/JPS63158845A/en
Publication of JPH0734448B2 publication Critical patent/JPH0734448B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の実装方法に関するものであり特
にフェースダウン実装法に係るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting method, and more particularly to a face-down mounting method.

従来の技術 従来、回路基板に半導体装置を実装する方法は、プラス
チックで封止成形されたデュアル・インライン・パッケ
ージの半導体装置を回路基板に挿入し、半田付けする方
法、半導体装置に予め形成しておいた金バンプを利用し
てフレキシブル回路基板に半導体装置を一括ボンディン
グするTAB法、などがある。またさらに高密度に実装す
るためには第4図示すように、保護膜103を有する半導
体装置101のアルミ電極102に予め半田バンプ106を形成
しておき、この半導体装置101を第5図に示すようにレ
ジスト膜113を有する基板111に形成された銅電極112に
半田バンプ106が一致するようにフェースダウンで重ね
合わせ、半田の融点以上の加熱と圧力により半田バンプ
106を溶融し銅配線膜112に半田付けするフリップチップ
・ボンディング法もある。
2. Description of the Related Art Conventionally, a method of mounting a semiconductor device on a circuit board is a method of inserting a semiconductor device in a dual in-line package molded with plastic into a circuit board and soldering it, or forming a semiconductor device in advance. There is a TAB method, etc., in which semiconductor devices are collectively bonded to a flexible circuit board using the gold bumps that have been placed. In order to mount at higher density, solder bumps 106 are previously formed on the aluminum electrodes 102 of the semiconductor device 101 having the protective film 103 as shown in FIG. 4, and the semiconductor device 101 is shown in FIG. As described above, the copper bumps 112 are placed face down so that the solder bumps 106 are aligned with the copper electrodes 112 formed on the substrate 111 having the resist film 113, and the solder bumps are heated and pressured above the melting point of the solder.
There is also a flip chip bonding method in which 106 is melted and soldered to the copper wiring film 112.

発明が解決しようとする問題点 しかしながら従来のフリップチップ・ボンディング法で
は半田バンプを形成する際に、真空蒸着とフォトリング
ラフィによりクロムと銅の2層の下地処理を行ない、そ
の後電解メッキ,真空蒸着等の方法と熱処理で半田バン
プを形成していたため、バンプ形成の工程が複雑でコス
トが高くつく、半田付け時に基板にフラックス塗布が必
要であるという問題点があった。
Problems to be Solved by the Invention However, in the conventional flip-chip bonding method, when solder bumps are formed, two layers of chromium and copper are subjected to an underlying treatment by vacuum deposition and photolinography, and then electrolytic plating and vacuum deposition are performed. Since the solder bumps are formed by the above method and the heat treatment, there are problems that the bump forming process is complicated and the cost is high, and it is necessary to apply flux to the substrate during soldering.

問題点を解決するための手段 以上のような従来の問題点を解決するため本発明は、半
導体装置の電極に、半田付け可能な金属膜を形成する工
程と、回路基板の電極に半田付け可能な金属膜を形成す
る工程と、前記回路基板の電極に対し前記半導体装置の
電極が互いに対向しフェースダウンとなるように配置す
る際に前記回路基板と前記半導体装置の間に半田微粒子
を分散した熱可塑性樹脂フィルムを挟む工程と、前記回
路基板と前記半導体装置とを、前記半田微粒子の融点よ
り3ないし20度低い温度となるように熱圧着し、前記回
路基板の電極と、前記半導体装置の電極とを金属接合さ
せる工程とからなる半導体装置の実装方法にしている。
Means for Solving the Problems In order to solve the above-mentioned conventional problems, the present invention provides a step of forming a solderable metal film on an electrode of a semiconductor device and a method of soldering on an electrode of a circuit board. And a step of forming a metal film, and solder fine particles are dispersed between the circuit board and the semiconductor device when the electrodes of the semiconductor device are arranged face down with respect to the electrodes of the circuit board. The step of sandwiching the thermoplastic resin film, and the circuit board and the semiconductor device are thermocompression-bonded to each other at a temperature which is 3 to 20 degrees lower than the melting point of the solder fine particles, and the electrodes of the circuit board and the semiconductor device. The method of mounting a semiconductor device includes a step of metal-bonding with an electrode.

作用 次に本発明の構成要素の作用を述べる。Action Next, the action of the components of the present invention will be described.

半導体装置の電極は通常はアルミニウム薄膜となってい
るが、本発明では、半田微粒子と金属接合しやすいよう
に半導体装置のアルミ電極上に半田付け可能な金属膜を
形成している。半田付け可能な金属膜の例としては、
銅,ニッケル,金,錫などがある。なお、半田付け可能
な金属膜のアルミニウムへの密着力改善のため、下地に
クロム,チタン等を付けても良い。また回路基板の電極
も同様の理由により半田付け可能な金属膜を形成してい
るが、半導体装置の電極と必ずしも同一の金属膜である
必要はない。
The electrode of the semiconductor device is usually an aluminum thin film, but in the present invention, a solderable metal film is formed on the aluminum electrode of the semiconductor device to facilitate metal bonding with the solder fine particles. Examples of solderable metal films include:
There are copper, nickel, gold, tin, etc. In order to improve the adhesion of the solderable metal film to aluminum, chromium, titanium or the like may be attached to the base. Further, the electrodes of the circuit board are formed with solderable metal films for the same reason, but they are not necessarily the same metal film as the electrodes of the semiconductor device.

半田微粒子は半導体装置の電極と、回路基板の電極を接
合し、強固な接合力と確実な電気接続とを可能にするも
のである。熱可塑性樹脂フィルムは半田微粒子を均一に
分散させ、半田微粒子の取り扱いを容易にするための媒
体で、弱い加熱と圧力で半導体装置または回路基板に仮
固定できるもので腐食性のないものであれば、良く特別
強固な接着力は必要としないが、半田微粒子の融点より
も20度低い温度でも軟化するものでなければ熱圧着が都
合よく行なわれない。
The solder fine particles bond the electrodes of the semiconductor device and the electrodes of the circuit board to enable a strong bonding force and reliable electrical connection. The thermoplastic resin film is a medium for uniformly dispersing the solder fine particles and facilitating the handling of the solder fine particles. If it can be temporarily fixed to the semiconductor device or the circuit board with weak heating and pressure and is not corrosive, Well, it does not require a particularly strong adhesive force, but thermocompression bonding is not conveniently performed unless it softens even at a temperature 20 degrees lower than the melting point of the solder fine particles.

本発明において、熱圧着は半導体装置の電極に設けた金
属膜と半田微粒子を圧接させる作用と、回路基板に設け
た金属膜と半田微粒子を圧接する作用がある。その際半
田微粒子の温度はその融点よりも3ないし20度低い温度
にしか加熱されないため溶融することはないが、圧力を
かけているため、半田微粒子は金属膜に強く押し付けら
れ変形しながら金属膜に部分拡散が生じ、フラックス塗
布を必要とせずに金属接合が確実にできるものと考えら
れる。加圧接合する際の温度が半田微粒子の融点よりも
3度低い温度超えると金属膜と半田微粒子の接触圧力が
不足してフラックスなしには接合できない。
In the present invention, thermocompression bonding has an action of bringing the metal film provided on the electrode of the semiconductor device into pressure contact with the solder fine particles and an action of bringing the metal film provided on the circuit board into contact with the solder fine particles. At that time, the temperature of the solder fine particles is only 3 to 20 degrees lower than the melting point, so that the solder fine particles are not melted, but since pressure is applied, the solder fine particles are strongly pressed against the metal film and are deformed while being deformed. It is considered that metal diffusion can be ensured without the need for flux application because partial diffusion occurs in the. If the temperature at the time of pressure bonding exceeds the temperature which is lower than the melting point of the solder fine particles by 3 degrees, the contact pressure between the metal film and the solder fine particles is insufficient and the bonding cannot be performed without the flux.

また半田微粒子の融点よりも20度低い温度未満では、半
田微粒子と金属膜の部分拡散が生じない。
If the temperature is lower than the melting point of the solder fine particles by 20 ° C., partial diffusion of the solder fine particles and the metal film does not occur.

実施例 次に第1図〜第3図により本発明の実施例を説明する。Embodiment Next, an embodiment of the present invention will be described with reference to FIGS.

まず、保護膜3を形成した半導体装置1のアルミ電極2
の上に、スパッタ法により形成した膜厚500Åのクロ
ム,スパッタ法と電解メッキ法により形成した膜厚15μ
mの銅をホトリソグラフィー技術を用いてエッチングを
行ないクロム層7と半田付け可能な金属膜である銅層8
を形成しておく。
First, the aluminum electrode 2 of the semiconductor device 1 on which the protective film 3 is formed
Of 500 Å of chromium formed by sputtering, and 15 μ of film formed by sputtering and electroplating
The copper layer 8 which is a metal film which can be soldered to the chromium layer 7 by etching copper of m using the photolithography technique
Is formed.

一方、回路基板であるガラス基板11にはスパッタ法によ
り形成した膜厚500Åのクロム,スパッタ法により形成
した膜厚2000Åの銅をホトリソグラフィー技術を用いて
エッチングを行ないクロム層14と半田付け可能な金属膜
である銅配線膜12を形成しておく。
On the other hand, on the glass substrate 11 which is a circuit board, chromium with a film thickness of 500Å formed by the sputtering method and copper with a film thickness of 2000Å formed by the sputtering method can be soldered to the chromium layer 14 by etching using the photolithography technique. A copper wiring film 12 which is a metal film is formed in advance.

つぎに前記半導体装置1と、ガラス基板11とを位置合わ
せし、その間に示差走差熱量分析法による融点が170℃
の半田微粒子5を含有するフィルム状の熱可塑性樹脂4
を狭み、半導体装置1の裏面より加熱圧着する。その際
の加圧ツールの温度と時間は、予め微細な熱伝対を接合
面に挿入して加圧時間に対する接合面の温度上昇を加圧
ツールの温度毎に測定しておき、最適な条件を求める。
すなわち、接合面の温度が半田微粒子の融点よりも摂氏
3ないしは20度低い温度となるようにツール温度と加圧
時間を決めた。一例をあげるとツール温度270℃で15秒
間加圧することにより良好な結果が得られた。このとき
の接合面の温度は160℃であった。
Next, the semiconductor device 1 and the glass substrate 11 are aligned with each other, and the melting point by the differential scanning calorimetry is 170 ° C. between them.
Film-shaped thermoplastic resin 4 containing the solder fine particles 5
Is narrowed, and thermocompression bonding is performed from the back surface of the semiconductor device 1. For the temperature and time of the pressing tool at that time, insert a fine thermocouple into the joining surface in advance and measure the temperature rise of the joining surface with respect to the pressing time for each temperature of the pressing tool. Ask for.
That is, the tool temperature and the pressurizing time were determined so that the temperature of the joint surface was 3 to 20 degrees Celsius lower than the melting point of the solder fine particles. As an example, good results were obtained by pressing at a tool temperature of 270 ° C for 15 seconds. The temperature of the joint surface at this time was 160 ° C.

加圧時間を10秒としたときの接合面温度に対する接合強
度の関係を第6図に示す。接合強度はチップサイズ4mm
×4mm,パッドサイズ100μm,パッド数12箇所/チップの
半導体装置を引きはがすのに必要なせん断力を1パッド
当りの荷重で示した半田微粒子は示差走査熱量分析法に
よる融点(ピーク)が170℃で、粒子径2〜7μmのも
のを用いた、その結果、接合強度は150℃〜167℃で60グ
ラム/パッド以上の値が得られ実用強度に達している。
特に望ましいのは160℃〜167℃である。接合面温度が15
0℃未満では半田微粒子のつぶれかたが少ないため、接
合強度が不十分となる。また接合面温度が163℃以上で
は半田微粒子がわずかな加圧でつぶれやすくなり、特に
融点以上では液状になり加圧力が作用しないため、半導
体装置1の銅層8およびガラス基板11上の銅配線膜12の
表面酸化膜を破って半田微粒子がこれらの銅被膜に部分
拡散しにくくなり接合強度が低下する。
FIG. 6 shows the relationship between the joining surface temperature and the joining strength when the pressing time is 10 seconds. Bonding strength is chip size 4mm
Solder fine particles showing the shearing force required to peel off a semiconductor device of × 4 mm, pad size 100 μm, pad number 12 places / chip as the load per pad, have a melting point (peak) by differential scanning calorimetry of 170 ° C. Then, particles having a particle diameter of 2 to 7 μm were used, and as a result, a bonding strength of 60 g / pad or more was obtained at 150 ° C. to 167 ° C., and practical strength was reached.
Particularly desirable is 160 ° C to 167 ° C. Junction surface temperature is 15
If the temperature is lower than 0 ° C, the solder fine particles are less likely to be crushed, so that the bonding strength becomes insufficient. Further, when the bonding surface temperature is 163 ° C. or higher, the solder fine particles are easily crushed by a slight pressure, and particularly when the temperature is higher than the melting point, the solder fine particles become liquid and no pressing force is applied. The surface oxide film of the film 12 is broken, and the solder fine particles are less likely to be partially diffused in these copper coatings, so that the bonding strength is reduced.

発明の効果 以上説明したように、本発明によれば、半導体装置の電
極と回路基板の電極の双方に半田付け可能な金属膜を形
成し、これらを熱可塑性樹脂フィルム中に分散した半田
微粒子を溶融することなく加圧接合しているため、フラ
ックスを使用せず双方の電極同志を半田微粒子を介して
接合でき、工業的利用価値が大きいものである。
EFFECTS OF THE INVENTION As described above, according to the present invention, solderable metal films are formed on both electrodes of a semiconductor device and electrodes of a circuit board, and solder fine particles are prepared by dispersing these in a thermoplastic resin film. Since they are pressure-bonded without melting, both electrodes can be bonded through the solder fine particles without using flux, which has great industrial utility value.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例における半導体装置の実装状態
を示す断面図、第2図は同接合部の拡大断面図、第3図
は本発明の実施例における半田微粒子を分散した熱可塑
性樹脂フィルムの斜視図、第4図は従来例の半導体装置
の断面図、第5図は同半導体装置の実装状態を示す断面
図、第6図は本発明の実施例における接合面温度と接合
強度の関係を示す関係図である。 1,101……半導体装置、5……半田微粒子、8……銅
層、11……ガラス基板、12,112……銅配線膜。
FIG. 1 is a sectional view showing a mounted state of a semiconductor device in an embodiment of the present invention, FIG. 2 is an enlarged sectional view of the same joint portion, and FIG. 3 is a thermoplastic resin in which solder fine particles are dispersed in an embodiment of the present invention. FIG. 4 is a perspective view of the film, FIG. 4 is a cross-sectional view of a semiconductor device of a conventional example, FIG. 5 is a cross-sectional view showing a mounted state of the semiconductor device, and FIG. 6 is a graph showing a bonding surface temperature and a bonding strength in an embodiment of the present invention. It is a relationship diagram which shows a relationship. 1,101 ... Semiconductor device, 5 ... solder fine particles, 8 ... copper layer, 11 ... glass substrate, 12,112 ... copper wiring film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体装置の電極に、半田付け可能な金属
膜を形成する工程と、回路基板の電極に半田付け可能な
金属膜を形成する工程と、前記回路基板の電極に対し前
記半導体装置の電極が互いに対向しフェースダウンとな
るように配置する際に前記回路基板と前記半導体装置の
間に半田微粒子を分散した熱可塑性樹脂フィルムを挟む
工程と、前記回路基板と前記半導体装置とを、前記半田
微粒子の融点より3ないし20度低い温度となるように熱
圧着し、前記回路基板の電極と、前記半導体装置の電極
とを金属接合させる工程とからなる半導体装置の実装方
法。
1. A step of forming a solderable metal film on an electrode of a semiconductor device, a step of forming a solderable metal film on an electrode of a circuit board, and the semiconductor device on the electrode of the circuit board. A step of sandwiching a thermoplastic resin film in which solder fine particles are dispersed between the circuit board and the semiconductor device when the electrodes are arranged so as to face each other face down, the circuit board and the semiconductor device, A method for mounting a semiconductor device, comprising the steps of thermocompression bonding so that the temperature is lower than the melting point of the solder fine particles by 3 to 20 degrees, and the electrodes of the circuit board and the electrodes of the semiconductor device are metal-bonded.
JP61306924A 1986-12-23 1986-12-23 Semiconductor device mounting method Expired - Lifetime JPH0734448B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61306924A JPH0734448B2 (en) 1986-12-23 1986-12-23 Semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61306924A JPH0734448B2 (en) 1986-12-23 1986-12-23 Semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPS63158845A JPS63158845A (en) 1988-07-01
JPH0734448B2 true JPH0734448B2 (en) 1995-04-12

Family

ID=17962910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61306924A Expired - Lifetime JPH0734448B2 (en) 1986-12-23 1986-12-23 Semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JPH0734448B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5950006B2 (en) * 2014-08-01 2016-07-13 住友ベークライト株式会社 Manufacturing method of semiconductor device and manufacturing method of electronic component

Also Published As

Publication number Publication date
JPS63158845A (en) 1988-07-01

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