JPH0734478B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0734478B2 JPH0734478B2 JP61170023A JP17002386A JPH0734478B2 JP H0734478 B2 JPH0734478 B2 JP H0734478B2 JP 61170023 A JP61170023 A JP 61170023A JP 17002386 A JP17002386 A JP 17002386A JP H0734478 B2 JPH0734478 B2 JP H0734478B2
- Authority
- JP
- Japan
- Prior art keywords
- ion
- layer
- substrate
- semiconductor device
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/03—Gettering within semiconductor bodies within silicon bodies
- H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
Landscapes
- Element Separation (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はイオン注入による半導体装置の製造方法に関す
るものであり、特にシリコン層と組成比の正しい絶縁物
層が急峻な界面で接するSOI（Silicon On Insulator）
基板からなる半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device by ion implantation, and in particular, an SOI (Silicon On Insulator) in which a silicon layer and an insulating layer having a correct composition ratio are in contact with each other at a steep interface. )
The present invention relates to a method for manufacturing a semiconductor device including a substrate.
従来の技術 （Ａ）例えば酸素イオンを注入してSOI構造を作り、こ
の構造に半導体素子を作り込むSIMOX技術（Separation
by IMplanted OXygen）の場合について第３図，第４図
を用いて説明する。シリコン単結晶２の（100）面2Aに
16O+ビーム４を80KeVの加速エネルギーで１×1018ions/
cm2注入し、窒素雰囲気中1150℃で熱処理して絶縁物層
６を形成する。2Bは単結晶２の上層に残された部分であ
る。しかるのち、第３図ｂの様に１μｍ程度のエピタキ
シャル層28を積み、この層28に第３図ｃの様に所定の半
導体素子16を形成している〔Y.Omucra et al.VLSI Symp
osium（ブイ エル エス アイ シンポジウム）Kobe
（1985）24−25〕。18は領域2B,28の一部が酸化された
周辺絶縁物領域26はゲート電極、20,22はソース，ドレ
イン電極、24はゲート絶縁物である。この様な方法で形
成されたSOI基板は、実際第３図ｂにおいて、表面エピ
タキシャル層28を除くと第３図の様に表面側からシリコ
ン単結晶層８、照射損傷を受け酸素を不純物として多量
に含む層10、組成比の正しいSiO2層６となる（PLF Hewm
ent;マテリアル リサーチ ソサイアティ シンポジウ
ム プロシーディング（Mat.Res.Soc.Symp.Proc.）Vol3
3（1984）41）。Conventional technology (A) For example, SIMOX technology (Separation) in which oxygen ions are implanted to form an SOI structure and semiconductor elements are formed in this structure
The case of by IMplanted OXygen) will be described with reference to FIGS. 3 and 4. On (100) face 2A of silicon single crystal 2
16 O + beam 4 at 1 × 10 18 ions / with acceleration energy of 80 KeV
cm 2 is implanted, and heat treatment is performed at 1150 ° C. in a nitrogen atmosphere to form the insulating layer 6. 2B is a portion left in the upper layer of the single crystal 2. Then, an epitaxial layer 28 of about 1 μm is stacked as shown in FIG. 3b, and a predetermined semiconductor element 16 is formed on this layer 28 as shown in FIG. 3c [Y. Omucra et al. VLSI Symp.
osium (Buyer SII Symposium) Kobe
(1985) 24-25]. Reference numeral 18 denotes a peripheral insulator region 26 in which a part of the regions 2B and 28 are oxidized, a gate electrode, 20 and 22 source and drain electrodes, and 24 a gate insulator. The SOI substrate formed by such a method is actually the silicon single crystal layer 8 from the surface side as shown in FIG. 3 except the surface epitaxial layer 28 in FIG. Layer 10 and the SiO 2 layer 6 with the correct composition ratio (PLF Hewm
ent; Material Research Society Symposium Proceedings (Mat.Res.Soc.Symp.Proc.) Vol3
3 (1984) 41).
（Ｂ）なお、16O+ビームを150KeVの加速エネルギーで2.
25×1018ions/cm2注入し窒素雰囲気中1250℃以上の熱処
理を施す事によって表面側のシリコン単結晶層中の不純
物酸素が殆んで無くなり、急峻な界面を得る事が、〔BY
Mao et al.Appl.Phys.Lett.（アプライ フィジックス
レター）48（12）.24March（1986）794〕に示されて
いる。(B) In addition, the 16 O + beam is accelerated by the acceleration energy of 150 KeV 2.
By implanting 25 × 10 18 ions / cm 2 and performing heat treatment at 1250 ° C. or higher in a nitrogen atmosphere, impurity oxygen in the silicon single crystal layer on the surface side is almost completely eliminated, and a steep interface can be obtained [BY.
Mao et al. Appl. Phys. Lett. (Apply Physics Letter) 48 (12) .24 March (1986) 794].
発明が解決しようとする問題点 従来の方法（Ａ）ではイオン注入に際して起こる照射損
傷の為、表面側のシリコン単結晶層28とSiO2層６との間
に第３図に示す如く広く損傷層10が残り、この層10がSi
-SiO2界面の急峻性を低下させ、又表面シリコン単結晶
層28に半導体素子を形成した場合リーク電流の経路とな
る。又表面シリコン層28中に残留する酸素不純物が引き
続く製造プロセスに於いてドナーとなりMOSトランジス
タの閾電圧を変動させる等の影響を及ぼす〔DAVID J.FO
STER etal.IEEE Trans.Ele.Dev.（アイ イイイ トラ
ンザクション エレクトロン デバイス）Vol ED33
（３）（1986）354〕。Problems to be Solved by the Invention In the conventional method (A), due to irradiation damage occurring during ion implantation, a wide damage layer is formed between the silicon single crystal layer 28 on the surface side and the SiO 2 layer 6 as shown in FIG. 10 remains, this layer 10 is Si
When the semiconductor element is formed on the surface silicon single crystal layer 28, the steepness of the -SiO 2 interface is lowered, and it becomes a path of the leak current. Also, the residual oxygen impurities in the surface silicon layer 28 act as a donor in the subsequent manufacturing process, which affects the threshold voltage of the MOS transistor, etc. [DAVID J.FO
STER et al.IEEE Trans.Ele.Dev. Vol ED33
(3) (1986) 354].
従来の方法（Ｂ）では1250℃以上という半導体プロセス
に於いては異常な高温処理を必要とする為、熱処理炉材
料からの重金属汚染が問題となる。Since the conventional method (B) requires an abnormally high temperature treatment in the semiconductor process of 1250 ° C. or higher, heavy metal contamination from the heat treatment furnace material becomes a problem.
問題点を解決するための手段 本発明の方法は、イオン注入によるSOI基板作製時に、
先ず絶縁物層を形成するに足る量の第１のイオンを注入
し、続いて基板を所定の温度に設定して、所定の飛程で
軽元素の第２のイオンを注入した後熱処理を施し、SOI
構造を形成して、表面側シリコン層に半導体素子を作り
込むものである。Means for Solving the Problems The method of the present invention, when manufacturing an SOI substrate by ion implantation,
First, a sufficient amount of the first ions for forming the insulating layer is implanted, then the substrate is set to a predetermined temperature, the second ions of the light element are implanted at a predetermined range, and then heat treatment is performed. , SOI
A structure is formed and a semiconductor element is built in the silicon layer on the front surface side.
作用 SOI構造基板作製時のイオン注入による表面側シリコン
層14内の残留不要被注入不純物を、高温に於ける軽元素
イオンの注入による所謂Radiation euhanced diffusion
により減少せしめ、かつ不要不純物の存在による熱処理
時の２次欠陥発生をも減少せる事により、表面シリコン
層と絶縁物層間の損傷を軽減し、急峻な界面を得る。Action The residual unnecessary injected impurities in the surface side silicon layer 14 due to ion implantation at the time of manufacturing the SOI structure substrate are so-called Radiation euhanced diffusion due to the implantation of light element ions at high temperature.
And the occurrence of secondary defects at the time of heat treatment due to the presence of unnecessary impurities is reduced, and damage between the surface silicon layer and the insulating layer is reduced, and a steep interface is obtained.
実施例 以下にシリコン基板（100）面に酸素イオンを注入した
後、水素イオンを注入した本発明の一実施例について第
１図を用いて説明する。シリコン基板２の（100）表面2
Aに酸素イオンビーム４を例えば加速エネルギー180KeV
で照射し、前記シリコン基板中に埋め込み酸素物層６を
形成する。この際には、イオン注入の分布に従って表面
に残るシリコン層８と酸化物層６との間には照射損傷を
伴う酸素を多量に含む層10が形成され、表面シリコン層
８中にも固溶限度を越える濃度の酸素が残留する。これ
ら残留不要被注入酸素は引き続く高温熱処理により析出
物を形成したり、析出物形成に伴う転位の発生を引き起
こす。この様な析出もしくは転位はSOI基板としては不
純物の捕獲中心となったり、キャリアの生成消滅中心と
なったりして、有害であり、不要の酸素は除去する必要
がある。Example An example of the present invention in which oxygen ions are implanted into the surface of a silicon substrate (100) and then hydrogen ions are implanted will be described below with reference to FIG. (100) surface 2 of silicon substrate 2
Oxygen ion beam 4 to A, for example, acceleration energy 180 KeV
And the embedded oxygen layer 6 is formed in the silicon substrate. At this time, a layer 10 containing a large amount of oxygen accompanied by irradiation damage is formed between the silicon layer 8 and the oxide layer 6 remaining on the surface according to the distribution of ion implantation, and a solid solution is also formed in the surface silicon layer 8. Oxygen with a concentration exceeding the limit remains. These residual unnecessary injected oxygen forms precipitates by subsequent high temperature heat treatment or causes dislocations accompanying the formation of precipitates. Such precipitation or dislocation is harmful to the SOI substrate as a center for trapping impurities or a center for annihilation of carriers, and unnecessary oxygen needs to be removed.
そこで第１図ａに於ける基板を第１図ｂの様に300℃か
ら1000℃程度の高温、例えば600℃に保ち、軽元素イオ
ンとして水素イオンビーム12を例えば加速エネルギー10
KeVで、ドーズは1015〜1018ions/cm2例えば1017ions/cm
2注入してやると、酸素濃度の低い表面シリコン層14を
得る。すなわち、層10,8は酸素濃度の低い表面シリコン
層14となる。この基板を1100〜1200℃例えば1150℃で熱
処理した。Therefore, as shown in FIG. 1b, the substrate in FIG. 1a is kept at a high temperature of 300 ° C. to 1000 ° C., for example, 600 ° C.
In KeV, the dose is 10 15 〜 10 18 ions / cm 2 For example 10 17 ions / cm
When two implantations are performed, a surface silicon layer 14 having a low oxygen concentration is obtained. That is, the layers 10 and 8 become the surface silicon layer 14 having a low oxygen concentration. This substrate was heat-treated at 1100 to 1200 ° C, for example 1150 ° C.
第２図はそのシリコン基板中の酸素濃度をSIMS（Second
ary Ion Mass Spectroscopy）で測定したデータであ
る。横軸は１次イオンCs+によるスパッタリングタイ
ム、縦軸は２次イオン（酸素）のシグナル強度でいずれ
も任意単位である。点線は単に1150℃で熱処理した従来
の方法にもとづく例で、表面シリコン層14に酸素濃度の
ピーク９をもつ、実線は本発明の実施例のものでピーク
９は大幅に減少し、表面シリコン層14と埋め込み絶縁物
層６の境界にわずかにスパイク11を残すのみである。こ
の様に処理したシリコン基板の表面シリコン層14中に第
１図ｃの様に例えばMOSトランジスタ16を形成する。18
は周辺分離酸化物20,22はソース・ドレイン電極、24は
ゲート絶縁膜、26はゲート電極である。尚、軽元素イオ
ンとしては水素分子イオンもしくはヘリウムイオンを用
いても同様の結果が得られる。Figure 2 shows the oxygen concentration in the silicon substrate by SIMS (Second
ary Ion Mass Spectroscopy). The horizontal axis represents the sputtering time by the primary ion Cs + , and the vertical axis represents the signal intensity of the secondary ion (oxygen), which is an arbitrary unit. The dotted line is an example based on the conventional method in which heat treatment is simply performed at 1150 ° C., and the surface silicon layer 14 has a peak 9 of oxygen concentration. The solid line is the embodiment of the present invention and the peak 9 is greatly reduced. Only a slight spike 11 is left at the boundary between 14 and the buried insulating layer 6. In the surface silicon layer 14 of the silicon substrate thus treated, for example, a MOS transistor 16 is formed as shown in FIG. 1c. 18
Peripheral isolation oxides 20 and 22 are source / drain electrodes, 24 is a gate insulating film, and 26 is a gate electrode. Similar results can be obtained by using hydrogen molecule ions or helium ions as the light element ions.
発明の効果 以上の様に本発明によれば、イオン注入によりSOI基板
を形成する際に、被注入イオンが本来とる分布に従って
表面シリコン層に残留する多量の不要酸素を軽元素イオ
ン注入によるradiation euhanced diffusionにより外向
拡散させる事が出来、もって酸化析出物のない表面シリ
コン層と、埋め込み絶縁物層が急峻な界面で接するSOI
基板を得る。この様にして形成されたSOI基板にMOSトラ
ンジスタを形成する際にはソース・ドレイン電極の拡散
層を界面まで下げる事が出来、浮遊容量の低減というSO
I構造本来の特徴を生かした構造にする事が出来、高性
能なSOI型半導体装置作製に寄与する。As described above, according to the present invention, when an SOI substrate is formed by ion implantation, a large amount of unnecessary oxygen remaining in the surface silicon layer according to the distribution originally taken by the implanted ions is emitted by the light element ion implantation. SOI can be diffused outward by diffusion, and thus the surface silicon layer without oxide precipitate and the buried insulator layer are in contact with each other at a steep interface.
Get the substrate. When forming a MOS transistor on the SOI substrate formed in this way, the diffusion layer of the source / drain electrodes can be lowered to the interface, reducing the stray capacitance.
It is possible to make a structure that makes full use of the original characteristics of the I structure, which contributes to the fabrication of high-performance SOI semiconductor devices.
第１図は本発明の一実施例の半導体装置の製造工程図、
第２図はシリコン基板中の酸素濃度分布を示す特性図、
第３図，第４図は従来の方法を示す断面図である。 ２……シリコン基板、４……酸素イオンビーム、６……
埋め込み絶縁物層、８……酸素を含む表面シリコン層、
10……損傷層、12……水素イオンビーム、14……表面シ
リコン層、16……半導体素子、18……周辺絶縁物、20…
…ソース電極、22……ドレイン電極、24……ゲート酸化
膜、26……ゲート電極。FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention,
FIG. 2 is a characteristic diagram showing the oxygen concentration distribution in the silicon substrate,
3 and 4 are sectional views showing a conventional method. 2 ... Silicon substrate, 4 ... Oxygen ion beam, 6 ...
Buried insulator layer, 8 ... Oxygen-containing surface silicon layer,
10 …… damaged layer, 12 …… hydrogen ion beam, 14 …… surface silicon layer, 16 …… semiconductor element, 18 …… peripheral insulator, 20…
… Source electrode, 22 …… Drain electrode, 24 …… Gate oxide film, 26 …… Gate electrode.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/12 Ｅ Ｈ０１Ｌ 21/265 Ｚ 9169−4Ｍ 21/76 Ｒ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location H01L 27/12 E H01L 21/265 Z 9169-4M 21/76 R
Claims (3)
入によって、埋め込み絶縁物層を形成した後、軽元素の
第２のイオンの注入によって前記絶縁物層上の前記基板
の一部よりなる表面シリコン層内に於ける残留不要被注
入不純物を外向拡散させ、前記表面シリコン層に半導体
素子を形成する事を特徴とする半導体装置の製造方法。1. A buried single insulator layer is formed in a silicon single crystal substrate by implanting a first ion, and then a second ion of a light element is implanted to form a portion of the substrate on the insulator layer. A method for manufacturing a semiconductor device, characterized in that residual unnecessary injected impurities are outwardly diffused in the surface silicon layer to form a semiconductor element on the surface silicon layer.
酸素原子を含むイオンもしくは窒素原子を含むイオンを
用い、軽元素の第２のイオンとして水素イオン，水素分
子イオンもしくはヘリウムイオンを用いる事を特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。2. An ion containing an oxygen atom or an ion containing a nitrogen atom is used as an implanted ion of the first ion implantation, and a hydrogen ion, a hydrogen molecule ion or a helium ion is used as the second ion of the light element. The method of manufacturing a semiconductor device according to claim 1, wherein
板温度を300℃から1000℃の範囲に上昇させる事を特徴
とする特許請求の範囲第１項又は第２項記載の半導体装
置の製造方法。3. The semiconductor device according to claim 1, wherein the temperature of the substrate to be implanted is raised in the range of 300 ° C. to 1000 ° C. at the time of implanting ions containing a light element. Manufacturing method.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61170023A JPH0734478B2 (en) | 1986-07-18 | 1986-07-18 | Method for manufacturing semiconductor device |
| US07/073,829 US4837172A (en) | 1986-07-18 | 1987-07-15 | Method for removing impurities existing in semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61170023A JPH0734478B2 (en) | 1986-07-18 | 1986-07-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6327063A JPS6327063A (en) | 1988-02-04 |
| JPH0734478B2 true JPH0734478B2 (en) | 1995-04-12 |
Family
ID=15897167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61170023A Expired - Lifetime JPH0734478B2 (en) | 1986-07-18 | 1986-07-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0734478B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2752799B2 (en) * | 1991-03-27 | 1998-05-18 | 三菱マテリアル株式会社 | Method for manufacturing SOI substrate |
| JPH1197377A (en) | 1997-09-24 | 1999-04-09 | Nec Corp | Method for manufacturing SOI substrate |
| JPH11307747A (en) * | 1998-04-17 | 1999-11-05 | Nec Corp | SOI substrate and manufacturing method thereof |
| FR2784796B1 (en) * | 1998-10-15 | 2001-11-23 | Commissariat Energie Atomique | PROCESS FOR PRODUCING A LAYER OF MATERIAL BURIED IN ANOTHER MATERIAL |
| JP2007281316A (en) * | 2006-04-11 | 2007-10-25 | Sumco Corp | SIMOX wafer manufacturing method |
-
1986
- 1986-07-18 JP JP61170023A patent/JPH0734478B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6327063A (en) | 1988-02-04 |
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| EXPY | Cancellation because of completion of term |