JPH0734555B2 - Frame synchronizer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a frame synchronization device used in a digital transmission system such as a backbone transmission system, a public network, a subscriber system, or the like.

[Conventional technology]

The progress of transmission technology using optical fiber as a transmission medium is remarkable, and the amount of transmitted information is several hundred Mbps to several Mbps.
Transmission of about Gbps is becoming possible. A time division multiplex method is considered to effectively use a large capacity digital transmission system, but since high speed processing is required, the frame configuration should be as simple as possible to reduce the size and simplification of the circuit. I'm thinking.

As one of the methods, there is a bit-unit time division multiplexing method, and FIG. 7 is a general frame configuration diagram of this multiplexing method. In the figure, one frame is composed of K bits, and one frame is divided into K channels in bit units,
One of them is assigned to a frame channel, F is a frame channel, and # 1 to # K-1 are K-1 channels in bit units.

About this technology, "Construction of 1.2 Gbps optical loop LAN" published by Fumio Akashi et al. In P.74, Proc.
It is described in. In this method, when bit multiplexing is performed, a unique frame pattern is inserted into the frame channel (F) in units of several frames, one bit at a time.
In the synchronization detection, the frame channel is detected and the synchronization detection is performed depending on whether the signal sequence separated from any channel after separating the data in units of channels matches the inserted unique frame pattern.

As another method, there is a method in which a frame is divided into subframe units and a frame pattern is dispersed in each subframe. FIG. 8 is a general frame configuration diagram of the method. In the figure, one frame is divided into L subframes, each subframe is a 1-bit unit, and one frame has a configuration of (1 × L) bits. The first 1 bit of each subframe A frame pattern is sequentially inserted into each bit by 1 bit. Fi (i = 1,2 ...,
L) indicates a frame bit inserted in the leading 1 bit of each subframe, and # 1 to #L indicate subframes in 1-bit units.

This technology is described in "Design and Characteristics of F-400M System Terminal Repeater", P597-608, published by Noriaki Yoshikai et al. In this method, (F ₁ F ₂ F ₃ ...... F _{L-1 FL} ) is a frame pattern, and in the synchronization detection, (F ₁ F ₂ F ₃ ...... F _The synchronization detection is performed by detecting the frame pattern of ( _{L-1 FL} ). Need not be inserted in all F ₁ to F _L is the frame bit frame pattern, for example, the remaining frame bit F ₂ in the case where the frame pattern is inserted into the frame bit F ₁ F ₃ F ₅ ...... , F ₄ F ₆ ... can also be used to transmit information such as transmission line monitoring monitors and service monitors.

[Problems to be solved by the invention]

In the bit multiplexing method as shown in FIG. 7, 1 out of 1 frame K bit is set as the frame channel (F).
Are using a bit. In order to reduce the size and simplification of the circuit, the length of K constituting one frame cannot be increased so much that the signal amount of the frame pattern in the transmission data amount is as large as 1 / K. . This overhead is expected to increase as the transmission capacity increases and the speed increases, and considering the reliability and serviceability of the system, a channel for transmitting information such as a transmission line monitoring monitor and a service monitor is required. The trend will increase significantly.

Further, in the method as shown in FIG. 8 in which the frame is divided into sub-frame units and the frame pattern is distributed to each sub-frame, it is a unique frame pattern (F ₁ F ₂ F ₃ ... _{FL -1} F _L ) is detected from the separated signal sequence to detect synchronization, and frame synchronization and subframe synchronization are ensured. Frame bit F ₁ to F _L transmission line number of sub-frames L and in the Monitor or service monitor, a frame or transmission information inserted to the inside, the number of bits of a sub-frame I
By increasing the number of bits, it is possible to transmit information with less overhead for the amount of transmission data without increasing the complexity of the circuit.

However, once the synchronization is lost, it is the worst case to detect the signal sequence that coincides with the frame pattern (F ₁ F ₂ F ₃ ... _{FL-1 FL} ) from the separated signal sequence. Since the one-frame handing is required, the worst synchronization period required for the synchronization recovery is L × I × 1 frame [SEC], and the number of subframes L and the number of subframe constituent bits I are large. If this happens, the average time taken to detect the frame pattern (F ₁ F ₂ F ₃ ...... F _L-1 F _L ) once the synchronization is lost becomes large.

The present invention solves these problems by increasing the circuit scale, reducing the overhead of the frame pattern signal amount with respect to the transmission data amount without increasing complexity, facilitating detection of the frame pattern, and averaging time required for synchronization recovery. It is an object of the present invention to provide a synchronization detection circuit suitable for a high-speed and large-capacity transmission system that can reduce the power consumption.

[Means for solving problems]

According to the present invention, a serial / parallel converter for extracting a received signal for each M bits and M outputs of the serial / parallel converter are connected,
A channel interchanger for exchanging channels of the M input signals to output M signals and one of M output lines of the channel interchanger are connected, and the code length is L bits from the output line. Means for extracting a certain N sets of codes and calculating a remainder between a code polynomial having the codes as coefficients and a predetermined generator polynomial, and means for calculating a phase difference between the codes based on the multiplication result calculation result. And a means for performing channel switching control of the channel switching device by using the phase difference between the codes of the calculation result.

〔Example〕

Before describing the present invention, a cyclic code will be briefly described here. Generally, the code word is (A0A1A2 ... An−
1), A0 is n-1 order, A1 is n-2 order, ..., An
-1 0 then allowed to correspond, code polynomial F a (X) F (X) = An-1 + An-2X + An-3X 2 + ... + A1X n-2 + A0
X ^n-1 can be expressed as (1). Here, the code length is n, and in terms of time, the higher-order term A0 first appears, then progresses toward the lower order sequentially, and finally An-1 appears.

Here, assuming that the code length is 8 and (C ₁ C ₂ C ₃ ... C ₇ C ₈ ) is selected as the code word, the code polynomial F (X) can be expressed by a polynomial of degree 7 F (X) = C ₈ + C ₇ X + C ₆ X ² + C ₅ X ³ + C ₄ X ⁴ + C ₃ X ⁵ + C ₂ X ⁶ + C
₁ X ⁷ (2) For example, if a third-order polynomial is selected as the generator polynomial G (X) and G (X) = 1 + X + X ² + X ³ (3), then F (X) = Q (X) If there exists a polynomial Q (X) that satisfies G (X) (4), then equation (2)
The polynomial of is generated from the generator polynomial of Expression (3). Here, as the polynomial Q (X), the input bit string I =
Polynomial with (1011) as coefficient Q (X) = 1 + X + X ³ (5) and assuming a field modulo 2, F (X) = Q (X) G (X) = (1 + X + X ³ ) ・ (1 + X + X ² ＋ X ³ ) = 1 + X ³ ＋ X ⁵ ＋ X ⁶ …… (6), and the codeword W0 = (01101001) …… (7) is generated from the input bit string I = (1011). Become.

In addition, as shown in the publication “The Code Theory” (Hiroshi Miyakawa, Yoshihiro Iwadari, Hideki Imai, Shokoido, p194-197), n is generally coded in the modulo 2 body. When the length is set to a length, the code word generated from G (X) by which the generator polynomial G (X) divides X ⁿ +1 forms a cyclic code.
The generator polynomial of is (X ⁸ +1) / G (X) = (X ⁸ +1) / (X ³ + X ² + X + 1) = X ⁵ + X ⁴ + X + 1) (8), and X ⁸ +1 becomes X ⁵ + X Divide by ⁴ + X + 1. Therefore, the codeword of code length 8 generated from the generator polynomial of Expression (3) is a cyclic code. That is, in the code word of equation (7) Each row component of the matrix W represented by the equation (9) becomes a cyclic code having a code length of 8, and W11 = (01101001) (10-1) W12 = (11010010) (10-2) W13 = (10100101). (10-3) W14 = (01001011) ... (10-4) W15 = (10010110) ... (10-5) W16 = (00101101) ... (10-6) W17 = (01011010) ... (10-7) W18 = (10110100) (10-8), the code polynomial having W11, W12, ..., W17, W18 as coefficients is divisible by the generator polynomial of Expression (3).

Similarly, W21 = (00001111) ... (11-1) W22 = (00011110) ... (11-2) W23 = (00111100) ... (11-3) W24 = (01111000) ... (11-4) W25 = ( 11110000) ... (11-5) W26 = (11100001) ... (11-6) W27 = (11000011) ... (11-7) W28 = (10000111) ... (11-8), then W21, W22, ... It is also shown that the code polynomial whose coefficients are W27, W27 and W28 are also divisible by the generator polynomial of Expression (2).

In the following, the eight kinds of codes shown in formulas (10-1), ..., Formula (10-8) are represented by W ₁ , formula (11-1) ,. Let us denote the sign of the seed by W ₂ .

FIG. 1 shows an embodiment of a frame synchronizer according to the present invention. In the figure, 101 is the high-order group input data S _IN , 102 is a development circuit, 103 is a channel exchange circuit, 104 _{1 to} 104 ₃ are dividers, 1
05 is a phase difference detector, 106 _{1 to} 106 ₆₄ are low order group output data S
_OUT .

In the figure, a high-order group input data (S _IN ) 101 is transmitted with a data sequence in which low-order group output data of 64 sequences are bit-multiplexed, and this data sequence is sequentially extracted in 64-bit units in a decompression circuit 102. Expanded to 64 series.
Each of these 64 series becomes an input line of the channel switching circuit 103. This channel switching circuit 103 performs channel switching using control information from a phase difference detector 105, which will be described later, and then outputs 64-sequence information. In this channel exchange control, once the synchronization is pulled in, the subsequent channel control only needs to maintain the state, and high speed control is not required. Also, this channel switching circuit 103 is
The function of connecting each input to an arbitrary output is not necessary, and the channel exchange control here only needs to perform sequential channel exchange.

Hereinafter, the hunting control in the synchronous state and the asynchronous state will be sequentially described.

First, in the synchronized state, the low-order group output data 106 _{1 to} 106
The frame of the data series transmitted to ₆₄ will be described. In the synchronized state, the data sequence having the frame structure shown in FIG. 2 is the low-order group output data 106 _{1 to} 106 _64.
Sent to.

As shown in the figure, the subframe length of each low-order group frame is composed of I bits and 24 subframes.
1 to # 64 indicate frame numbers. In addition, three sets of codes (F _S1 , F _S2 , and F _S3 ) each having a code length of 8 bits are dispersedly inserted into the first 1 bit of each subframe by 1 bit as a frame synchronization pattern. That is, a frame synchronization pattern having a pattern length of 24 bits is dispersedly inserted in each frame, and three sets of 8-bit patterns extracted every 3 bits from the 24-bit frame pattern form a code. The code inserted here is
For example, it is possible to use a cyclic code having a code length of 8 generated from the generator polynomial shown in Expression (3).
A configuration in which three sets of cyclic codes are inserted so that (F _S1 , F _S2 , F _S3 ) = (W ₁ , W ₁ , W ₁ ) is also conceivable, but here,
Three sets of cyclic codes are inserted so that (F _S1 , F _S2 , F _S3 ) = (W ₁ , W ₂ , W ₁ ).

FIG. 5 is an embodiment showing the correspondence between the code inserted as the frame synchronization pattern and the cyclic code. For example,
In frame # 2 in Figure 2, The frame pattern is inserted so that That is, the low-order group output data (S _OUT1 ) 106 ₁ is the # 1 frame, the low-order group output data (S _OUT2 ) 106 ₂ is the # 2 frame, ..., The low-order group output data (S _OUT64 ). Will send # 64 frames.

Next, the phase difference between the symbols W ₁₁ , W ₁₂ , ..., W ₁₈ is examined. For example, the sign W ₁₆ is obtained by cyclically shifting the code W ₁₁ to 5 bits to the left, the phase difference P (W ₁₁ codes W ₁₁ and code W _16, W
₁₆ ) becomes P (W ₁₁ , W ₁₆ ) = 5 (13). On the contrary, the code W ₁₁ is the code W ₁₆ cyclically shifted to the left by 3 bits, so that P (W ₁₆ , W ₁₁ ) = 3 (14).

FIG. 3 shows the relationship of the phase difference between these code groups W ₁ . Similarly, FIG. 4 defines the phase difference between the code group W ₁ and the code group W ₂ .

Here, reference numeral W ₁ does not match the code W ₂ be cyclically shifted, for example, code W ₁₁ and the phase difference P (W ₁₁ code W _26,
W ₂₆ ), P (W ₁₁ , W ₂₆ ) = A5 (15) The phase difference P (W ₂₆ , W ₁₁ ) between code W ₂₆ and code W ₁₁ is P (W ₂₆ , W ₁₁ ) = B3 ... (16) shall be defined.

Furthermore, three sets of cyclic codes (F _S1 , F
_S2, the phase difference vector P _V a _{P V = (P (F S1} , F S2) of F _S3), is defined as _{P (F S2, F S3)} ), examines the phase difference vector P _V.

The phase difference vector shown in mode 0 of FIG. 5 indicates the phase difference vector of the three sets of cyclic codes inserted in each frame. For example, the frame pattern (W The phase difference vector of ₁₁ , W ₂₁ , W ₁₂ ) is (P (W ₁₁ , W ₂₁ ), P (W ₂₁ , W ₁₂ )) = (A0, B1) ... (17). Further, in mode 1, the 24-bit frame pattern inserted in each frame is cyclically shifted leftward by 1 bit, and in mode 2, the bit pattern is cyclically shifted leftward by 2 bits and extracted every 3 bits. 3 shows a phase difference vector between three sets of codes having a code length of 8 bits. For example, 24 inserted in frame # 2
The frame pattern of bits (W ₁₁ , W ₂₁ , W ₁₂ ) is cyclically shifted by 1 bit and then extracted every 3 bits 3
The codes of the set are (W ₂₁ , W ₁₂ , W ₁₂ ), three sets of codes extracted every 3 bits after cyclically shifting by 2 bits are:
(W ₁₂ , W ₁₂ , W ₂₂ ), the phase difference vector in mode 1 is (P (W ₂₁ , W ₁₂ ), P (W ₁₂ , W ₁₂ )) = (B 1,0) mode 2
The phase difference vector of is (P (W ₁₂ , W ₁₂ ), P (W ₁₂ , W ₂₂ )) = (0, A0).

These relationships are shown in FIG. Generally, if the mod of 3 of the cyclic shift amount of a 24-bit frame pattern is 0, the mode is 0, if 1 is the mode 1, and if it is 1, the phase difference vector shown in the mode 2 is matched.

Next, the synchronization holding method will be described.

In synchronous state, low order group output data (S _OUT64 ) 106 ₆₄
, The frame # 64 shown in FIG. 2 is transmitted, and becomes the input information of the dividers 104 _{1 to} 104 ₃ . . The divider 104 ₁ takes in a bit pattern of 8 bits per frame for every triple subframe period ( _S1 ).

In the synchronized state, the bit pattern fetched by the divider 104 ₁ is the code W ₁₁ . Similarly, the divider 104
₂ is a triple subframe period, and the clock _{S2 is} delayed by a subframe from the clock _S1 for fetching data into the divider 104 ₁ , and the divider 104 ₃ is a triple subframe period, and The bit pattern is captured at clock _S3, which is delayed by two subframes from clock _S1 . These bit patterns match the code W ₂₈ and the code W ₁₈ . The divider 104 ₁ is a code polynomial whose coefficient is the code W ₁₁ ,
The divider 104 ₂ divides the code polynomial having the code W ₂₈ as a coefficient, and the divider 104 ₃ divides the code polynomial having the code W ₁₈ as a coefficient and the generating polynomial of Expression (3) for each frame. To do.

In the synchronous state, all the remainders become zero. Divider 104 ₁
~ 104 ₃ send the result of each remainder zero to the phase difference detector 105. The phase difference detector 105 confirms the residual zero and the divider 104 ₁
-104 ₃ and the sign taken by performing the inserted match verification code as a frame pattern to the frame of the # 64 performs the holding of the synchronization state.

In addition, the confirmation of the synchronization hold can be confirmed by each low group output data (S _OUT ) 10
6 _1-106 configured to perform a match confirmation frame pattern is inserted to the transmitted come data series ₆₄ is also possible.

Next, the hunting control in the case of falling into the asynchronous state will be described.

In the asynchronous state, first, the low-order group output data (S
_OUT64) 106 ₆₄ to carry out the detection of the frame pattern is inserted in the data sequence being transmitted. Therefore, the dividers 104 _{1 to} 104 ₃ synchronize with clocks whose phases are different from each other by 3 times the sub-frame period, and the
The code of the 8-bit pattern is read for each frame, and the code polynomial having the read code as a coefficient is divided by the generator polynomial G (X) shown in Expression (3).

The phase difference detector 105 examines the remainder results of the dividers 104 _{1 to} 104 ₃ and if the remainder is non-zero, each of the dividers 104 _{1 to} 104 ₃ takes in three times the subwarem period. The clock phase is shifted by 1 bit. This operation is divided by 104 ₁
Repeat until the remainder of ~ 104 ₃ becomes zero.

The fact that the remainder is non-zero means that the bit string taken in by the dividers 104 _{1 to} 104 ₃ is other than the frame pattern inserted in any of the frames shown in FIG. ), ..., Expression (10-8) or Expression (11-1),
..., which means that the information is information other than the frame pattern composed of the cyclic code shown in Expression (11-8).

On the other hand, the remainder zero means that equations (10-1), ..., (10−
8), or the detection of the frame pattern group consisting of the cyclic code shown in equation (11-1), ..., Equation (11-8).

Next, based on this information, it is detected which low-order group output data (S _OUT64 ) 106 ₆₄ is transmitted as shown in FIG.

As an example, the frame of # 2 is the low-order group output data (S
_OUT64 ) 10 6 Consider that it is sent to ₆₄ .

After confirming that the remainders of the dividers 104 _{1 to} 104 ₃ are all zero,
The phase difference detector 105 detects the phase difference between the codes fetched by the dividers 104 _{1 to} 104 ₃ . That is, the divider 104 ₁
Is the code W ₁₁ , the divider 104 ₂ is the code W ₁₂ , and the divider 104 ₃ is the code W
_{If 13} is taken in, the phase difference P (W ₁₁ , W ₁₂ ) between the code W ₁₁ and the code W ₁₂ , and the phase difference P (W between the code W ₁₂ and the code W _13
12 , W ₁₃ ), and further the phase difference vector (P (W ₁₁ , W ₁₂ ),
P (W ₁₂ , W ₁₃ )) is calculated.

If the frame transmitted to the low-order group output data (S _OUT64 ) 106 ₆₄ is the frame # 2 in FIG. 2, this phase difference vector is (A0, B1), (B1,0), or (0, A
It will be one of 0). If the phase difference vector shown in FIG. 5 exists exclusively, which frame shown in FIG. 2 is the frame transmitted to the low-order group output data (S _OUT64 ) 106 ₆₄ ? Judgment is possible. That is, the frame pattern inserted for frame synchronization in each frame is the high-order group input data (S _IN ) 101
Can also be used as the identification information of the frame that is bit-expanded by the expansion circuit 102.

Using this frame identification information, the phase difference detector 105,
Low-order output data (S _OUT64) 106 ₆₄ to the frame of # 64 to perform the sequential channel replacement control channel exchange circuit 103 be sent. This control on the low-order output data (S _OUT64) 106 ₆₄ is so that the frames # 64 are transmitted, the code (W _11, W ₁₂ to be taken to a divider 104 _{1-104 3,} W ₁₃ ) does not always match the code (W ₁₁ , W ₂₈ , W ₁₈ ) inserted in the # 64 frame. That is, here, the sub-frame cycle is merely secured. Therefore, the phase difference detector 105 obtains the phase difference vector after the sequential channel switching control. If this phase difference vector is (A7, B0), code W
Phase difference of ₁₁ and code W _11, in the case of (B0,2), the phase difference of the symbol W ₁₁ and code W _13, (2, A7) code W ₁₁ and the code W in the case of
By obtaining each of the ₁₂ phase differences, the frame header is promptly detected and the frame synchronization is secured.

This is the divider 1 when the phase difference vector is (A7, B0).
04 ₁ is the divider 104 when the phase difference vector is (B0,2)
₃ and further, when the phase difference vector is (2, A7), the divider 104 ₂ is a code inserted in the frame # 64 in FIG.
This is because the code group consisting of F _S1 (= W ₁₁ ) is included.

In the above description, the process after the determination of the remainder zero is divided into two steps, but it is also possible to collectively perform this process.

Since the number of subframe bits in the low-order group output data 106 _{1 to} 106 ₆₄ is I bits, the worst number of hunting times required to perform channel exchange control and frame synchronization after once falling into an asynchronous state is (I-1)
Very few times. Further, until the detection of the frame pattern group, that is, until the remainder zero is determined, the dividers 104 ₁ to 10
By hunting the phase difference of the clocks that 4 ₃ takes in with a triple sub-frame period as 1/3 sub-frame, it is possible to reduce the number of hunting in the worst case to (I / 3-1). .

Generally, when the cyclic code inserted in one frame according to the frame pattern insertion method shown in FIG. 5 is set to be l ₁ and the code length of the cyclic code is set to be l ₂ , it is possible to identify the frame in which the high-order group data is expanded into bits. It is easily shown that the maximum number is l ₂ ^(l-1) .

FIG. 6 shows the phase difference detector 106 in a ROM (Read Only Memory).
An example is shown in the case of using the above. In the figure, 601 _{0-601 7} address lines (A ₀ ~A _7), 602 has ROM,
603 _{0-603 8} control signal output line _{(D 0 ~D 8), 604} 0 ~604 2 is modulo input line (R ₀ ~R _2), 605 is an OR gate.

Here, the 16 sets of codes (cyclic codes) shown in equations (10-1), ..., Equation (10-8), and equations (11-1) ,. The code itself can be identified by identifying the upper 4 bits, and if only the first element of the phase difference vector shown in FIG. 5 is searched, 64 types of high-order group data (101) are developed. Since the frame identification can be performed, and the output control information only needs to identify 64 types of frames, the capacity of the ROM used is 2048 bits (256 words × 8 bits).

That is, among the eight address lines (601 _{0 to 601 7),} the address lines (601 _{0 to 601 3),} which is supplied to a divider 104 ₁ 8
Upper 4 bits of bit pattern, address line (601 _{4 to} 60
₁₇ ), each of the upper 4 bits of the 8-bit pattern supplied to the divider 104 ₂ is transmitted as address information. The remainder is the output of the divider (104 ₁ to 104 ₃₎ is input from the remainder input lines 604 ₀ ~604 _2, OR gate 60
It becomes 5 inputs. The output of this OR gate becomes the chip enable input of ROM.

Thus, only when the remainder of the divider 104 _{1-104 3} has become all zero, 8-bit information corresponding to the address information is output from the control information output line 603 _{0-603 7.} By using this information as the control information of the channel switching circuit 103, it is possible to detect the phase difference vector and control the output. When 64 types of frame identification control are performed, the number of output lines required to control the channel exchange circuit 103 is (64 = ²⁶ ).

The case where the cyclic code used has a code length of 8, the number of codes inserted into one frame is 3, and the generator polynomial G (X) = 1 + X + X ² + X ³ has been described as an example. Needless to say, it is not limited to the combination, and various combinations can be considered.

〔The invention's effect〕

As described above, by using the frame synchronizer according to the present invention, it is possible to easily detect the synchronization and to reduce the speed of the synchronization processing unit.
In addition, it is possible to grasp the state of the entire system without being conscious of the frame structure in the high-order group data, and it can be seen that the average asynchronous duration time is significantly improved compared to the conventional synchronous system.

The present invention is a frame synchronization device suitable for such a high-speed, large-capacity transmission system, and is expected to be utilized for application to a transmission system with a higher speed and larger capacity in the future.

[Brief description of drawings]

FIG. 1 is a block diagram in an embodiment of the present invention, FIG. 2 is a frame configuration diagram thereof, FIGS. 3 and 4 are phase difference diagrams of cyclic codes, FIG. 5 is a frame pattern and phase difference vector diagram,
FIG. 6 is a block diagram of the phase difference detector, and FIGS. 7 and 8 are frame diagrams of the conventional example. 101 …… High-order group input data S _IN , 102 …… Expansion circuit, 103…
… Channel switching circuit, 104 _{1 to} 104 ₃ …… Divider, 105 ……
Phase difference detector, 106 _{1 to} 106 ₆₄ ... Low-order group output data S _OUT1
~ S _OUT64 , 601 _{0 to} 601 ₇ ...... Address line (A _{0 to} A ₇ ), 602
...... ROM, 603 ₀ ~603 ₈ ...... control information output lines (D ₀ ~D _8), 6
04 _{0-604 2} ...... remainder input line _{(R 0 ~R 2), 605} ...... OR gate.

Claims (1)

[Claims] 1. A serial-parallel converter for extracting a received signal for each M (M is an integer) bits and M outputs of the serial-parallel converter are connected, and the channels of the M input signals are exchanged and M A channel interchanger for outputting a signal of a book, and N (N is an integer) pairs of codes, which are connected to one of M output lines of the channel interchanger and have a code length of L bits, are extracted from the output line, Means for calculating a remainder between a code polynomial having the code as a coefficient and a predetermined generator polynomial, means for calculating a phase difference between the codes based on the residue calculation result, and between the codes of the calculation results And a means for performing channel switching control of the channel switching device using a phase difference.