JPH0736259B2 - Digital audio playback device data processing circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data processing circuit of a digital audio reproducing apparatus, and in particular, it is uncorrectable as a result of error detection and error correction of digital data read from a disc. The present invention relates to a circuit that performs interpolation or previous value hold processing on various error data.

(B) Conventional technology In a compact disc reproducing apparatus, an FEM signal is created based on an RF signal taken out from a disc by a laser, and this EFM signal is demodulated to obtain recorded digital data. This digital data after EFM demodulation is applied to an error detection and correction circuit called CIRC (Cross Interleaved Reed-Solomon Code), and it is checked whether the read digital data is correct or not Correct the data and restore the correct data. However, if the data exceeds the correction capability, the data cannot be corrected. Therefore, interpolation or previous value hold processing is performed without using the erroneous data. This prevents noise from occurring when a dropout or the like occurs when reading data.

Conventionally, in a data processing circuit that performs interpolation or pre-value hold on error data, one sample data consisting of 16 bits created by an error detection and correction circuit is an MSB data of an upper 8 bits and an upper symbol and a lower 8 bits. The LSB data is divided into lower symbols and applied, and an error indication flag indicating whether or not the upper and lower symbols are erroneous is applied. Therefore, the data processing circuit resets the sample data composed of the upper symbol and the lower symbol as they are, when the error indication flags attached to the upper symbol and the lower symbol are reset and it is shown that the data is correct. If the error indication flag of either the upper symbol or the lower symbol is set, the entire sample data is not used as an error and the error indication flag of the next sample data is checked and this sample data is also output. If there is an error, the previous value hold processing that outputs the previous sample data is performed, and if it is determined that the next sample data is correct, the interpolation that outputs the intermediate value between the previous sample data and the next sample beta It was processing.

FIG. 5 is a signal waveform diagram of data created by the above-described interpolation processing and previous value hold, a solid line is a signal waveform that should be created by correct data, and a broken line is created by interpolation processing or previous value hold. Signal waveform. The horizontal axis shows the correction instruction flag which is the logical sum of the error instruction flags added to the upper symbol and the lower symbol. This correction instruction flag is "1" in only one place
In this case, interpolation is performed to obtain the average value from the correct data before and after, and if the correction instruction flag is continuously set to "1", the previous value is output to output the previous correct data, and then correct When data is applied, the average value interpolation between the value of the previous value hold and the correct data is performed.

For the data processing described above, refer to No. 10 of "Compact Disc Reader" issued by Ohmsha on November 25, 1982.
It is described on pages 9 to 110.

(C) Problems to be solved by the invention However, as described above, even if either the upper sample or the lower sample is erroneous, it is determined that the entire sample data is erroneous. The number of times the processing is performed becomes large, and in particular, as shown in FIG. 5, if the previous value is continuously held at the time of a large signal, the value is significantly different from the original correct value, and this is reproduced as noise. .

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and when the volume represented by the sample data is large, the volume is substantially higher than the sample data. Focusing on the fact that it is determined by the bit, that is, the upper symbol, if the upper symbol is correct, the sample data is treated as correct even if the lower symbol is erroneous, and a predetermined number of sample data following the loud sample data Even if is a small signal, if a higher-order symbol is correct, in order to perform the same treatment, a level detection circuit for detecting that one sample data is more than a predetermined value in absolute value is provided. A count circuit for counting a predetermined number of times of processing of sample data which is reset by the detection output of the circuit and which is followed by the high-volume sample data, and When the error indication flag attached to the upper symbol of the sample data according to the signal indicating that the counting unit is counting is correct regardless of the content of the error indication flag attached to the lower symbol, the sample data is said to be a correct value. A flag processing circuit that creates a correction instruction flag is provided, and processing such as interpolation and previous value hold is performed according to the correction instruction flag.

(E) Action According to the above means, the upper symbol of the signal data processed by the error correction circuit is an absolute value equal to or larger than a predetermined value,
That is, when the level detection circuit detects that the signal is a large signal, the count circuit is reset and enters the counting operation state according to the situation that the detection output and the upper symbol of the sample data are correct. At this time, if the error indication flag attached to the lower symbol of the signal data has a content indicating an error, the flag processing circuit causes the error indication flag of the lower symbol by the signal indicating that the count circuit is operating. Is cut off and the correction instruction flag is reset to make all the data correct. Further, if the counting circuit is in the middle of counting, an error indicating flag indicating that the upper symbol is correct and an error indicating flag indicating that the lower symbol is erroneous even if the upper symbol is a small signal and not detected by the level detection circuit. When applied, the signal indicating the operation of the counting circuit shuts off the error instruction flag attached to the lower symbol and resets the correction instruction flag. On the other hand, regardless of the operation of the counting circuit, the flag processing circuit sets the correction instruction flag when the error instruction flag indicating that the upper symbol is in error is applied, and when the counting circuit is in the counting stopped state, the lower symbol is set. Is applied, the correction instruction flag is set in the same manner and the entire data is determined to be erroneous. As a result, the same flag operation as in the case of the large signal is performed for the predetermined number of data counted by the counting unit after the detection of the large signal data, even if the data is the small signal.

(F) Embodiment 1 FIG. 1 is a block diagram showing an embodiment of the present invention, in which an 8-bit data bus (1) includes an error correction circuit (2), a RAM (3), an A register (4) and an MSBF. The latch (5) and the LSBF latch (6) are connected. The error correction circuit (2) decodes the data called CIRC read from the disk, and outputs an 8-bit upper symbol and 8
16-bit sample data consisting of low-order symbols of bits is created, and whether or not there is an error in the read data is detected and corrected. For uncorrectable high-order symbols or low-order symbols, error indication flag MSBF or
Set LSBF. These upper symbol, lower symbol, error indication flags MSBF and LSBF are stored in the RAM (3) via the data bus (1). The A register (4) is
Timing signals DLCM and DL different from the timing of writing data from the error correction circuit (2) to the RAM (3), which consists of an 8-bit MSB register for capturing the upper symbol and an 8-bit LSB register for capturing the lower symbol.
The CL reads the upper symbols and the lower symbols from the RAM (3) and fetches them. MSBF latch (5) and LSBF
The latch (6) has an error indication flag MSBF attached to the upper symbol and an error indication flag LSBF attached to the lower symbol.
Is read from the RAM (3) by the timing signal DACP and fetched.

To the stages after the A register (4), the upper symbol of the A register (4) is applied and the lower symbol is applied through the multiplexer (7) to the A'register (8).
And B to which the 16-bit output of A'register (8) is applied
A register (9), a multiplexer (10) with the 16-bit output of the B register (9) applied to one input, a B'register (11) with the 16-bit output of the multiplexer (10) applied, 'The output register (12) to which the 16-bit output of the register (11) is applied is provided, and these registers (8) (9) (11) (12) are the timing signal DLCM.
Captures the 16-bit output from the previous stage. Also, A
The MSB output of the register (4), the output of the multiplexer (7) and the 16-bit output of the output register (12) are applied to the average interpolation circuit (13), and the output of the average interpolation circuit (13) and the output register (12). The 16-bit output of the multiplexer (1
4) selected and applied to one input of the multiplexer (10). Here, since the right channel sample data and the left channel sample data are alternately applied to the A register (4), for example, when the right channel sample data is stored in the A register (4) at a certain timing, , B register (9) stores the previous left channel sample data, and the output register (12) also stores and outputs the previous right channel sample data. By creating such a state, when the sample data stored in the B register (9) is incorrect, the sample data stored in the A register (4) output from the average interpolation circuit (13) and the output register The interpolation result with the sample data stored in (12) is B
The multiplexers (10) and (14) can perform an interpolation process used in place of the sample data stored in the register (9) and a pre-value holding process using the sample data stored in the output register (12). These selections are made based on the correction instruction flags FA and FB created by the flag control circuit (15). In this state, the A'register (8) and the B'register (11) store the left channel sample data of the previous time and the previous two times.

Furthermore, the 8-bit output of the MSB register of the A register (4) is applied to the level detection circuit (16) and whether or not the upper symbol is a predetermined value or more in absolute value, that is, whether or not it is a large signal. To be detected. This level detection circuit (16) has a second
As shown in the figure, the OR gate (21) to which bits 1 to 6 of the upper sample are applied, the inverter (22) to which bit 7 is applied, and the OR
A circuit for detecting a positive predetermined value "02H" or more, which is composed of an AND gate (23) to which the output of the gate (21) and the output of the inverter (22) are applied, and a NAND gate (24) to which Bits 1 to 6 are applied. And the output of Bit7 and NAND gate (24) was added
It is composed of a circuit composed of an AND gate (25) for detecting a negative predetermined value “FDH” or less, and an OR gate (26) to which the outputs of the AND gates (23) and (25) are applied. That is, in the compact disc, the sample data uses the "2'S complement system" in which the most significant bit indicates positive and negative, and the absolute value of the upper symbol of the sample data is "2" by the level detection circuit (16). 02H ”or more is detected, and when detected, the output BS of the OR gate (26)
Becomes “1”. The output BS of the level detection circuit (16) is applied to the flag control circuit (15).

The flag control circuit (15) is composed of a count circuit and a flag processing circuit, receives the outputs of the MSBF latch (5) and the LSBF latch (6), and outputs the output BS of the level detection circuit (16).
Is a circuit that creates a correction flag FA and a control flag C that controls the multiplexer (7) according to the signal of
The high-order symbol taken into the A register (4) was detected as a small signal and the output BS was "0", and the predetermined number of data was not a large signal after the large signal data was detected. In this case, the correction instruction flag FA is set when at least one of the error instruction flag MSBF or LSBF is "1", and it is detected that the upper symbol is a large signal, and the output BS becomes "1". Error indication flag MSBF
Is set to "1", the correction instruction flag FA is set, and when LSBF is "1", the control flag C is set.

The flag control circuit (15) is constructed as shown in FIG. In FIG. 3, the timing signal ▲ ▼, the output MSBF of the MSBF latch (5) and the output LSBF of the LSBF latch (6) are applied to the NOR gate (27), and the timing signal is applied to the NOR gate (28). ▲ ▼, the output MSBF of the MSBF latch (5), the output LSBF of the LSBF latch (6) are inverted by the inverter (29), and
Control signal ▲ ▼ is applied, NOR gate (27) (28)
Is applied to the set input S of the R-SFF (31) via the OR gate (30), and the output of the NOR gate (28) is R
It is applied to the set terminal S of -SFF (32). R-SFF (3
1) stores the correction instruction flag FA, and R-S
The FF (32) stores the control flag C and is reset by the timing signal DACP applied to the reset input R in advance. The R-SFF (31) outputs the error indication flag MSBF and the error indication flag MSBF at the timing of the timing signal ▲ ▼.
When both LSBF are “0”, the output is from the NOR gate (27), and the output BS of the level detection circuit (16) becomes “1”, the control signal ▲ ▼ becomes “0”, and the error indication flag LSBF Only set at the output of the NOR gate (28) when only "1". The output of this R-SFF (31) is output as the correction instruction flag FA. On the other hand, the R-SFF (32) is at the timing of the timing signal ▲ ▼ and when the control signal ▲ ▼ is "0", the error instruction flag MSFBF is "0".
Set by the output of NOR gate (28) when LSBF is “1” at. The output Q of this R-SFF (32) is output as a control flag C, and when the control flag C is set to "1", the multiplexer (7) uses the intermediate value instead of the lower symbol of the A register (4). "80H" is output to the A'register (8).

The inverted output ▲ ▼ of the output MSBF of the MSBF latch (5) by the inverter (33) and the output BS from the level detection circuit (16) are applied to the AND gate (34) to which the timing signal DPIN is applied, and AND The output of the gate (34) is applied to AND gates (35) (36) which are controlled by control signals SDSY and ▲ ▼ for controlling the right channel sample data and the left channel sample data. A
The ND gates (35) (36) form a switching circuit, and the output of each AND gate (35) (36) is the reset input of the counter (37) (38) and the set of R-SFF (39) (40). Applied to the input. Further, to each input of the counters (37) (38), the control signal SDSY or the timing signal DACP controlled by ▲ ▼ and the output of each counter (37) (38) is inverted by the inverters (41) (42). The outputs of the AND gates (43) (44) to which the output is applied are connected. Furthermore, R-SFF (3
9) Output Q of (40) is control signal SDSY or ▲
The output of the NOR gate (47), which is applied to the AND gates (45) and (46) controlled by ▼, and the outputs of the AND gates (45) and (46) are applied, is the control signal ▲ ▼. Each of the counters (37) and (38) has a four-stage structure of T-FF, and the output when counting eight timing signals DACP output one for one processing of sample data is R-SFF (39). (Four
0) is reset and the timing signal DACP is cut off in the AND gates (43) and (44), one of which is divided into right channel sample data and the other of which is divided into left channel sample data. This counter (37) (38)
After the level detection circuit (16) detects that the high-order symbol is a large signal, the sample data on the one-channel side that is processed thereafter is sample data that is not detected by the level detection circuit (16). However, the processing of eight consecutive sample data sets the same flag operation as in the case of a large signal.

Returning to FIG. 1, the correction instruction flag FA output from the flag control circuit (15) is applied to the FA 'latch (17) provided corresponding to the A'register (8) and the multiplexer (14). Applied to the control input of. That is, when the correction instruction flag FA is “0”, the sample data stored in the A register (4) is recognized as correct, and the sample data stored in the B register (9) is incorrect. At this time, the multiplexer (14) is controlled so as to use the interpolated data instead of the sample data, and the output of the average interpolation circuit (13) is sent to the multiplexer (10). In addition, B register (9),
An FB latch (18), an FB 'latch (19) and an FC latch (20) which store a correction instruction flag are provided corresponding to the B'register (11) and the output register (12). these,
FA 'Latch (17), FB Latch (18), FB' Latch (19)
And the latch operation of the FC latch (20) is controlled by the timing signal PLCM, and each register (4) (8) (9) (11)
At the same time that the sample data stored in (12) is shifted to the next stage, the correction instruction flag FM attached to the sample data is also shifted to each latch (17) (18) (19) (20). The output FB of the FB latch (18) is the multiplexer (1
0) is applied to the control input and FB is "1", that is, B
When the sample data stored in the register (9) is incorrect, the multiplexer (10) is controlled to apply the output of the multiplexer (14) to the B'register (11).
As a result, the interpolated data or the data stored in the output register (12) is used instead of the error sample data stored in the B register (9).

FIG. 4 is a timing chart showing the operation of the circuit shown in FIGS. 1 to 3, and the timing signals DLCM, DACP, DCLC and DPIN are output in this order in order to process one sample data. Pulses are used. Therefore, when the timing signal DLCM is generated, the MSB register, A'register (8), B register (9), B'register (11) and output register (12) of the A register (4) are applied to the inputs. Data that is present. At this time, if the control flag C is "0", the sample data of the A register (4) is A '.
If the output FB of the FB latch (18) is taken into the register (8) and is "0", the sample data stored in the B register (9) is passed through the multiplexer (10) to B '.
It is taken into the register (11). That is, the sample data stored in each register is shifted by one stage. In addition, FA 'latch (17), FB latch (18), FB'
Similarly, in the latch (19) and the FC latch (20), the correction instruction flag stored in each latch is shifted to the next stage. On the other hand, RAM is stored in the MSB register of A register (4).
The upper symbol (probably the right channel data) of the next sample data read from (3) is captured. The value of this upper symbol is "02H" or more, or "F
The output BS of the level detection circuit (16) becomes "1" when it is less than or equal to "DH", and becomes "0" in other cases.

Next, when the timing signal DACP is generated, the error indication flag MSBF read from the RAM (3) to the data bus (1)
And LSBF are captured in the MSBF latch (5) and the LSBF latch (6). The error indication flag MSBF at this time is A
The error indication flag LSBF is a flag attached to the upper symbol loaded in the register (4), and the error instruction flag LSBF is a flag attached to the lower symbol loaded in the A register (4) in the next timing. On the other hand, R-SFF (31) and (32) of the flag control circuit (15) shown in FIG. 3 are reset by the timing signal DACP, the output FA becomes "1", and the control flag C becomes "0". Becomes Further, since the control signal SDSY is "1" and ▲ ▼ is "0", the counter (37) that counts the number of processing times after the detection of the large signal of the left channel is selected. If the value is “8”, the timing signal is output from the inverter (41).
The DACP is shut off at the AND gate (43) and the counter (3
If the count value of 7) is less than “8”, the timing signal DAC
P is counted by the counter (37) via the AND gate (43). At this time, the counter (37) counts A
The sample data before the upper symbol of the right channel is loaded into the register (4), that is, the sample data currently stored in the A'register (8) is added to the processing. When the count result of the counter (37) becomes "8", the R-SFF (39) is reset. Therefore, when the sample data of the left channel is fetched into the A register (4) for processing next, the control signal ▲ ▼ Is set to "1", and the same flag operation as that for the large signal is canceled even for the small signal.

Next, when the timing signal DLCL is generated, the lower symbol read from the RAM (3) to the data bus (1) is taken into the LSB register of the A register (4). At this point, the sample data of the right channel is prepared in the A register (4).

Next, the timing signal DPIN is generated, but before that, the control signal SDSY changes to "0" and ▲ ▼ changes to "1", and the counter (38) of the right channel is kept in the selected state. Then, when the timing signal DPIN is generated, the flag control circuit (15) operates to capture the outputs of the MSBF latch (5) and the LSBF latch (6) and perform the flag processing according to the output BS of the level detection circuit (16). To do. That is, in FIG. 3, the timing signal ▲ ▼ is the NOR gate (27) (2
When applied to 8), when both MSBF and LSBF are “0”,
That is, when both the upper symbol and the lower symbol are correct data, the output of the NOR gate (27) becomes "1", R-SFF (31) is set, the correction instruction flag FA becomes "0", and NOR The output of the gate (28) is "0" and RS
FF (32) remains reset. On the other hand, when the MSBF is “1”, that is, when the upper symbol is in error, the outputs of the NOR gates (27) and (28) are both “0”, so that the R-SFF (31) outputs the timing signal. It remains reset by the signal DACP and the correction instruction flag FA becomes "1".

Next, when MSBF is "0" and LSBF is "1", that is, when the upper symbol is correct and the lower symbol is incorrect, the output of the NOR gate (27) becomes "0", but the NOR gate (28 ) Output will be determined by the control signal ▲ ▼.

Therefore, when the level detection circuit (16) detects that the sample data is a large signal from the upper symbol and the output BS is "1", AND gate () of "1" is applied. When the timing signal DPIN is applied to 34), the output of the AND gate (34) becomes "1", and this output resets the counter (38) and sets R-SFF (40). As a result, the control signal ▲ ▼ becomes "0", so the output of the NOR gate (28) becomes "1" and RS
FF (31) is set, the correction instruction flag FA becomes "0", and R-SFF (32) is set, and the control flag C
Becomes “1”. That is, if the upper symbol is correct and is a large signal, the entire 16-bit signal data using the intermediate value “80H” instead of the lower symbol is treated as correct even if the lower symbol is incorrect. Be seen.

On the other hand, if the output BS of the level detection circuit (16) is "0", AN
The output of the D gate (34) remains "0", but when the count value of the counter (38) is less than "8", R-SF
Since F (40) is in the set state, the control signal ▲ ▼ is "0". Also at this time, the output of the NOR gate (28) becomes "1", R-SFF (31) (32) is set, the correction instruction flag FA becomes "0", and the control flag C becomes "1". In other words, during the eight subsequent signal data counted by the counter (38) after the large signal sample data is last detected, if the small signal upper symbol is correct, the intermediate value is generated even if the lower symbol has an error. 16-bit sample data using "80H" is treated as correct. Therefore, even if there is an error in the lower symbol when changing from a large signal to a small signal, interpolation processing or previous value holding processing is not performed, so that the generation of noise that reproduces a signal that is substantially close to a correct signal is reduced.

When the output BS of the level detection circuit (16) is “0”, AN
The output of the D gate (34) remains "0", but when the count value of the counter (38) is "8", R-SFF (4
0) is reset by the output of the counter (38), and the control signal ▲ ▼ becomes "1". Therefore, the outputs of the NOR gates (27) (28) are "0", and the R-SFF (31) (3
In 2), the correction instruction flag becomes "1" and the control flag C becomes "0" while being reset by the timing signal DACP. That is, when the sample data after the continuous of eight or more small signal sample data from the large signal sample data is a small signal and the upper symbol is correct and the lower symbol is incorrect, the correction instruction flag FA is "1". Is set to and the sample data is treated as an error.

As in the above-described operation, the output content of the level detection circuit (16) for detecting whether the signal of the higher-order symbol taken into the A register (4) is equal to or higher than a predetermined value, and the higher-order symbol is higher than or equal to the predetermined value. Error indication flag depending on the situation of whether the sample data is within 8 pieces after the detection of
The correction instruction flag FA and the control flag C are created by changing the processing method of MSBF and LSBF. The multiplexer (14) is controlled by the correction instruction flag FA and the control flag C created by the flag control circuit (15) to select whether to use the interpolation data or the previous value data. ), It is selected whether or not to use the intermediate value “80H” instead of the lower symbol, and when the correction instruction flag FA is shifted to the FB latch (18), it is shifted to the B register (9). The multiplexer (10) selects whether to use the sampled data.

(G) Effect of the Invention As described above, according to the present invention, if the upper symbol is correct when a large signal is detected, the magnitude of the signal represented by the upper symbol is the correct magnitude of the signal even if the lower symbol is wrong. Since the sample data using the higher-order symbol is regarded as correct, the flag operation is performed, and the same flag operation is performed on a predetermined number of sample data from the time of detection of a large signal, so that interpolation processing or Since the number of times the pre-value hold processing is performed is reduced, noise is reduced, and there is an advantage that a compact disc reproducing apparatus with high sound quality can be realized.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing the level detection circuit shown in FIG. 1, and FIG. 3 is a circuit showing the flag control circuit shown in FIG. 4 and 5 are timing charts showing the operation of the block diagram shown in FIG. 1, and FIG. 5 is a conventional signal waveform chart. (1) ... data bus, (2) ... error correction circuit,
(3) …… RAM, (4) …… A register, (5) …… MSB
F latch, (6) …… LSBF latch, (8) …… A ′ register, (9) …… B register, (7) (10) (14) ……
Multiplexer, (11) …… B 'register, (12) ……
Output register, (13) ... average interpolation circuit, (15) ... flag control circuit, (16) ... level detection circuit, (17) ...
FA ′ latch, (18) …… FB latch, (19) …… FB ′ latch, (20) …… FC latch.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kazuhiro Kimura Inventor, Kazuhiro Kimura 180 Sakata, Oizumi-cho, Ora-gun, Gunma Higashi Kyoyo Electric Co., Ltd. (56) Reference JP-A-54-21210 (JP, A)

Claims (1)

[Claims] 1. The sample data is composed of a plurality of symbols, an error correction flag is created by an error correction circuit for each symbol, and processing such as interpolation and previous value hold is performed on the error sample data based on the error correction flag. In a data processing circuit of a digital audio reproducing device, a level detection circuit for detecting that the absolute value of the sample data is a predetermined number or more, and the number of the sample data reset by the output of the level detection circuit Counting circuit, and the output of the level detecting circuit, the output of the counting circuit, and the plurality of symbols for a fixed number of sample data counted by the counting circuit after detecting that the number is equal to or more than the predetermined number. And a flag processing circuit that performs a flag operation according to the error instruction flag of I, the data processing circuit of the interpolation, digital audio reproduction apparatus characterized by performing a process of pre-value hold or the like.