JPH0736401B2 - Semiconductor manufacturing equipment - Google Patents
Semiconductor manufacturing equipmentInfo
- Publication number
- JPH0736401B2 JPH0736401B2 JP61276097A JP27609786A JPH0736401B2 JP H0736401 B2 JPH0736401 B2 JP H0736401B2 JP 61276097 A JP61276097 A JP 61276097A JP 27609786 A JP27609786 A JP 27609786A JP H0736401 B2 JPH0736401 B2 JP H0736401B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- forming chamber
- film forming
- film
- sputtering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 40
- 239000010408 film Substances 0.000 claims description 24
- 238000004544 sputter deposition Methods 0.000 claims description 19
- 239000010409 thin film Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 229910052786 argon Inorganic materials 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 7
- -1 argon ions Chemical class 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000013077 target material Substances 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000498 cooling water Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマグネトロン型スパッタ装置、特に半導体基板
へのD.C.電圧又はR.F.電圧印加などによる半導体基板及
び装置内壁の帯電を防止可能な半導体製造装置に関す
る。TECHNICAL FIELD The present invention relates to a magnetron type sputtering apparatus, and more particularly to a semiconductor manufacturing apparatus capable of preventing a semiconductor substrate and an inner wall of the apparatus from being charged by applying a DC voltage or an RF voltage to the semiconductor substrate. .
マグネトロン・スパッタ法による薄膜の形成はアルゴン
などの不活性ガスを導入し、マグネトロン放電により生
じた不活性ガスイオンをターゲットに衝突させ、その衝
撃によりターゲット材料をスパッタし、半導体基板上に
被着させるもので、近年、半導体装置の製造に広く使わ
れている。The thin film is formed by the magnetron sputtering method by introducing an inert gas such as argon and causing the inert gas ions generated by the magnetron discharge to collide with the target, and the impact sputters the target material to deposit it on the semiconductor substrate. In recent years, it has been widely used for manufacturing semiconductor devices.
しかし、この方法では半導体基板上に段差がある場合、
段差の側壁の被覆度が悪い。そのため、近年では半導体
基板に負電圧を印加しながらスパッタを行うことによっ
て、薄膜の段差部での被覆性を改善させる方法が行われ
るようになった。However, in this method, if there is a step on the semiconductor substrate,
The sidewall coverage of the step is poor. Therefore, in recent years, a method of improving the covering property at the step portion of the thin film by performing sputtering while applying a negative voltage to the semiconductor substrate has come to be used.
第４図はその一例を示したものである。第４図におい
て、ターゲット８の表面に磁石６で磁界を発生させてお
き、そこへアルゴンガスを導入しターゲット８に負電圧
を印加すると、ターゲット近傍でマグネトロン放電が起
こり、放電により発生したアルゴンイオンがターゲット
に衝突する。アルゴンイオンの衝撃によりターゲット８
からはターゲット材がスパッタされる。放電が安定した
ところでシャッター板９を開けると、スパッタされたタ
ーゲット材が半導体基板３に付着する。その際、半導体
基板３にホルダー５を介して負電圧を印加すると、半導
体基板３の表面にもアルゴンイオンが衝突し、半導体基
板３上ではターゲット材の堆積と、アルゴンイオンの衝
突によるエッチングが同時進行する。アルゴンイオンに
よるエッチング速度は下地の角度依存性があるため、段
差部の上に薄膜を形成する際に、半導体基板３に印加す
る負電圧を調整し、アルゴンイオンによるエッチング速
度をコントロールすることにより、段差部のかどに形成
される薄膜の形状をある程度制御でき、段差部側壁の被
覆度を改善することができる。図中、７は冷却水、10は
シールド板である。FIG. 4 shows an example thereof. In FIG. 4, when a magnetic field is generated by the magnet 6 on the surface of the target 8 and argon gas is introduced into the target 8 and a negative voltage is applied to the target 8, magnetron discharge occurs near the target, and argon ions generated by the discharge are generated. Collides with the target. Target 8 by the impact of argon ions
The target material is sputtered from. When the shutter plate 9 is opened when the discharge is stable, the sputtered target material adheres to the semiconductor substrate 3. At that time, when a negative voltage is applied to the semiconductor substrate 3 via the holder 5, argon ions also collide with the surface of the semiconductor substrate 3, and the deposition of the target material on the semiconductor substrate 3 and the etching due to the collision of argon ions occur simultaneously. proceed. Since the etching rate by argon ions depends on the angle of the base, by adjusting the negative voltage applied to the semiconductor substrate 3 when forming a thin film on the step portion and controlling the etching rate by argon ions, The shape of the thin film formed at the corner of the step can be controlled to some extent, and the coverage of the side wall of the step can be improved. In the figure, 7 is cooling water and 10 is a shield plate.
しかし、上述した半導体基板に負電圧を印加するスパッ
タ法では半導体基板上に正電荷が入射、堆積するため、
絶縁膜上にスパッタを行う場合などには半導体基板表面
への正電荷の蓄積により異常放電が発生し、半導体基板
表面の素子に大きなダメージを与えるという欠点があ
る。However, in the above-described sputtering method in which a negative voltage is applied to the semiconductor substrate, since positive charges are incident on and deposited on the semiconductor substrate,
When sputtering is performed on the insulating film, abnormal discharge occurs due to the accumulation of positive charges on the surface of the semiconductor substrate, which causes a serious damage to the elements on the surface of the semiconductor substrate.
又、半導体基板に負電圧を印加するスパッタ法を用いて
絶縁性の薄膜を作成する場合は、半導体基板表面が導電
性であっても、絶縁性の薄膜の成長につれ、半導体基板
表面に正電荷の蓄積が生じ、異常放電が発生する。更
に、絶縁性薄膜のスパッタは半導体基板周辺のシールド
板やホルダーの表面にも絶縁性薄膜を形成し、その表面
に正電荷の蓄積を生じ、異常放電を生じる。半導体基板
の周辺で異常放電が発生すると、スパッタの不均一やゴ
ミの発生を生じ、歩留りの低下をもたらす。Further, when an insulating thin film is formed by using a sputtering method in which a negative voltage is applied to a semiconductor substrate, even if the semiconductor substrate surface is conductive, as the insulating thin film grows, a positive charge is applied to the semiconductor substrate surface. Is accumulated and abnormal discharge occurs. Further, the sputtering of the insulating thin film also forms the insulating thin film on the surface of the shield plate and the holder around the semiconductor substrate, and the positive charges are accumulated on the surface to cause abnormal discharge. When abnormal discharge occurs around the semiconductor substrate, non-uniformity of spatter and generation of dust occur, resulting in a decrease in yield.
本発明の目的は半導体基板への電荷の蓄積による異常放
電を防止する半導体製造装置を提供することにある。An object of the present invention is to provide a semiconductor manufacturing apparatus that prevents abnormal discharge due to the accumulation of charges on a semiconductor substrate.
上述した従来の半導体基板に負電圧を印加するスパッタ
法に対し、本発明はスパッタ中に半導体基板及びその周
辺を含む成膜チャンバの表面に紫外線を照射し、スパッ
タ中における半導体基板及びその周辺を含む成膜チャン
バ表面への正電荷の蓄積を消滅させるという独創的内容
を有する。In contrast to the conventional sputtering method in which a negative voltage is applied to the semiconductor substrate described above, the present invention irradiates the surface of the film forming chamber including the semiconductor substrate and its periphery with ultraviolet rays during sputtering to protect the semiconductor substrate and its periphery during sputtering. It has the original content of eliminating the accumulation of positive charges on the surface of the film forming chamber including.
前記目的を達成するため、本発明に係る半導体製造装置
は、正電荷除去機構を有し、成膜チャンバ内で半導体基
板にスパッタ法により薄膜を形成する半導体製造装置で
あって、 正電荷除去機構は、成膜チャンバ内に設置され、成膜チ
ャンバ内でのスパッタ処理中に動作し、半導体基板及び
その周辺を含む成膜チャンバの表面の広範囲な領域に渡
って紫外線を照射し、これらの表面に発生する正電荷を
除去するものである。In order to achieve the above object, a semiconductor manufacturing apparatus according to the present invention is a semiconductor manufacturing apparatus that has a positive charge removing mechanism and forms a thin film on a semiconductor substrate by a sputtering method in a film forming chamber. Is installed in the film forming chamber, operates during the sputtering process in the film forming chamber, irradiates ultraviolet rays over a wide area of the surface of the film forming chamber including the semiconductor substrate and its periphery, and these surfaces It removes the positive charge generated in the.
本発明の原理について図面を参照して説明する。 The principle of the present invention will be described with reference to the drawings.
第３図は表面に絶縁膜２を有する半導体基板３にホルダ
ー５を介して負電圧を印加しながらスパッタによる薄膜
作成を行っているところに紫外線１を照射したときの現
象を模式的に示した図である。紫外線１を絶縁膜２に照
射すると、電子e-・正孔ｈ対が発生する。発生した正孔
ｈは、スパッタ中に絶縁膜表面に蓄積された正電荷によ
って生じる電場によって、半導体基板３やクランプ４へ
移動し、ホルダー５を経て流れていく。一方、残された
電子e-は絶縁膜表面に蓄積された正電荷と結合し、電荷
を中和する。FIG. 3 schematically shows a phenomenon when ultraviolet rays 1 are applied to a semiconductor substrate 3 having an insulating film 2 on its surface while applying a negative voltage through a holder 5 to form a thin film by sputtering. It is a figure. When the insulating film 2 is irradiated with ultraviolet rays 1, electron e − and hole h pairs are generated. The generated holes h move to the semiconductor substrate 3 and the clamp 4 by the electric field generated by the positive charges accumulated on the surface of the insulating film during the sputtering, and flow through the holder 5. On the other hand, the remaining electrons e − combine with the positive charges accumulated on the surface of the insulating film to neutralize the charges.
一方、スパッタ中において半導体基板３の周辺例えばク
ランプ4,ホルダー5,成膜チャンバの表面にも絶縁膜２が
成膜され、その表面に正電荷の蓄積が生じるが、これら
のものにも紫外線１が同様に照射されるため、上述した
と同様に電荷の中和が行われ、半導体基板３を含む成膜
チャンバ内での異常放電の発生は防止されることとな
る。On the other hand, during the sputtering, the insulating film 2 is formed around the semiconductor substrate 3, for example, the clamp 4, the holder 5 and the surface of the film forming chamber, and positive charges are accumulated on the surface. Is similarly irradiated, the charge is neutralized in the same manner as described above, and the occurrence of abnormal discharge in the film forming chamber including the semiconductor substrate 3 is prevented.
以下、本発明の実施例を図により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
（実施例１） 第１図は本発明の半導体製造装置についての実施例１を
示す図である。第１図に示すように、成膜チャンバ内の
シールド板10の上方位置に紫外線ランプ12を設置し、紫
外線ランプ12の後方に紫外線ランプ用シールド板兼反射
板11を設置している。シールド板兼反射板11は、その開
口縁が拡がっており、紫外線ランプ12からの紫外線が半
導体基板３及びその周辺を含む成膜チャンバの表面に照
射されるようになっている。その他の構成は従来と同じ
である。(Embodiment 1) FIG. 1 is a view showing Embodiment 1 of a semiconductor manufacturing apparatus of the present invention. As shown in FIG. 1, an ultraviolet lamp 12 is installed above the shield plate 10 in the film forming chamber, and an ultraviolet lamp shield plate / reflector 11 is installed behind the ultraviolet lamp 12. The shield plate / reflector plate 11 has a wide opening edge so that the ultraviolet rays from the ultraviolet lamp 12 are applied to the surface of the film forming chamber including the semiconductor substrate 3 and its periphery. The other configuration is the same as the conventional one.
実施例において、半導体基板３へのスパッタ処理の際に
紫外線ランプ12から発生した紫外線は、半導体基板３及
びその周辺を含む成膜チャンバ表面に照射され、それら
の表面に蓄積される正電荷を上述した原理により消滅さ
せる。In the embodiment, the ultraviolet light generated from the ultraviolet lamp 12 during the sputtering process on the semiconductor substrate 3 is applied to the surface of the film forming chamber including the semiconductor substrate 3 and the periphery thereof, and the positive charges accumulated on those surfaces are described above. It disappears according to the principle.
（実施例２） 第２図は本発明の半導体製造装置の実施例２を示す図で
ある。(Embodiment 2) FIG. 2 is a diagram showing Embodiment 2 of the semiconductor manufacturing apparatus of the present invention.
第２図において、半導体基板３の表面に絶縁性薄膜を成
長させる際に、同時に絶縁性薄膜が成長しその表面に正
電荷が蓄積される下段のシールド板10に加えて上段のシ
ールド板10にも紫外線が照射されるように、紫外線ラン
プ12と反射板13を配している。紫外線ランプ12より発生
する紫外線は半導体基板３やシールド板10の表面に成長
する絶縁性薄膜中に電子・正孔対を生成させ、表面に蓄
積される正電荷を消滅させることができる。In FIG. 2, when an insulating thin film is grown on the surface of the semiconductor substrate 3, at the same time as the insulating thin film grows and positive charges are accumulated on the surface, the upper shield plate 10 is added to the lower shield plate 10. Also, an ultraviolet lamp 12 and a reflector 13 are arranged so that the ultraviolet rays are emitted. Ultraviolet rays generated by the ultraviolet lamp 12 can generate electron-hole pairs in the insulating thin film grown on the surface of the semiconductor substrate 3 or the shield plate 10 to eliminate positive charges accumulated on the surface.
〔発明の効果〕 以上説明したように本発明は半導体基板に負電圧を印加
しながらスパッタ法により薄膜を形成する方法におい
て、スパッタ処理中において半導体基板及びその周辺を
含む成膜チャンバの表面の広範囲な領域に渡って紫外線
を照射するため、これらの表面に正電荷が帯電すること
を防止でき、成膜チャンバ内での異常放電を防止して半
導体基板表面の素子へのダメージをなくすとともに、ス
パッタの不均一性の発生を防止できるという効果を有す
る。As described above, the present invention is a method for forming a thin film by a sputtering method while applying a negative voltage to a semiconductor substrate. In the method, a wide range of the surface of the film forming chamber including the semiconductor substrate and its periphery during the sputtering process is used. Since ultraviolet rays are irradiated over various areas, it is possible to prevent these surfaces from being charged with positive charges, prevent abnormal discharge in the film formation chamber, and prevent damage to the elements on the semiconductor substrate surface. This has the effect of preventing the occurrence of non-uniformity.
第１図は本発明の実施例１を示す構造図、第２図は本発
明の実施例２を示す構造図、第３図は本発明の原理図、
第４図は従来の半導体製造装置の構造図である。 １……紫外線、２……絶縁膜、３……半導体基板、４…
…クランプ、５……ホルダー、６……磁石、７……冷却
水、８……ターゲット、９……シャッター板、10……シ
ールド板、11……紫外線ランプ用シールド板兼反射板、
12……紫外線ランプ、13……反射板1 is a structural diagram showing Embodiment 1 of the present invention, FIG. 2 is a structural diagram showing Embodiment 2 of the present invention, FIG. 3 is a principle diagram of the present invention,
FIG. 4 is a structural diagram of a conventional semiconductor manufacturing apparatus. 1 ... UV rays, 2 ... insulating film, 3 ... semiconductor substrate, 4 ...
… Clamp, 5 …… Holder, 6 …… Magnet, 7 …… Cooling water, 8 …… Target, 9 …… Shutter plate, 10 …… Shield plate, 11 …… Ultraviolet lamp shield plate / reflector plate,
12 …… UV lamp, 13 …… Reflector
Claims (1)
半導体基板にスパッタ法により薄膜を形成する半導体製
造装置であって、 正電荷除去機構は、成膜チャンバ内に設置され、成膜チ
ャンバ内でのスパッタ処理中に動作し、半導体基板及び
その周辺を含む成膜チャンバの表面の広範囲な領域に渡
って紫外線を照射し、これらの表面に発生する正電荷を
除去するものであることを特徴とする半導体製造装置。1. A semiconductor manufacturing apparatus having a positive charge removing mechanism for forming a thin film on a semiconductor substrate by a sputtering method in a film forming chamber, wherein the positive charge removing mechanism is installed in the film forming chamber. It operates during the sputtering process in the film chamber, irradiates ultraviolet rays over a wide area of the surface of the film forming chamber including the semiconductor substrate and its periphery, and removes positive charges generated on these surfaces. A semiconductor manufacturing apparatus characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61276097A JPH0736401B2 (en) | 1986-11-19 | 1986-11-19 | Semiconductor manufacturing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61276097A JPH0736401B2 (en) | 1986-11-19 | 1986-11-19 | Semiconductor manufacturing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63128725A JPS63128725A (en) | 1988-06-01 |
| JPH0736401B2 true JPH0736401B2 (en) | 1995-04-19 |
Family
ID=17564756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61276097A Expired - Lifetime JPH0736401B2 (en) | 1986-11-19 | 1986-11-19 | Semiconductor manufacturing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0736401B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7547633B2 (en) * | 2006-05-01 | 2009-06-16 | Applied Materials, Inc. | UV assisted thermal processing |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5980935A (en) * | 1983-08-24 | 1984-05-10 | Hitachi Ltd | Sputtering device |
| JPS6244995A (en) * | 1985-08-23 | 1987-02-26 | 日立マイクロコンピユ−タエンジニアリング株式会社 | Static electricity remover |
-
1986
- 1986-11-19 JP JP61276097A patent/JPH0736401B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63128725A (en) | 1988-06-01 |
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