JPH0736404B2 - Method for manufacturing superconductor device - Google Patents
Method for manufacturing superconductor deviceInfo
- Publication number
- JPH0736404B2 JPH0736404B2 JP62202143A JP20214387A JPH0736404B2 JP H0736404 B2 JPH0736404 B2 JP H0736404B2 JP 62202143 A JP62202143 A JP 62202143A JP 20214387 A JP20214387 A JP 20214387A JP H0736404 B2 JPH0736404 B2 JP H0736404B2
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- Japan
- Prior art keywords
- semiconductor
- metal
- superconducting material
- lead
- oxide
- Prior art date
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- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Containers, Films, And Cooling For Superconductive Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 「発明の利用分野」 本発明は酸化物セラミック系超電導材料を用いた超電導
装置の作製方法に関する。本発明は超電導体装置におい
て特に、半導体装置の相互配線の一部または全部を酸化
物超電導材料および金属または金属半導体化物の重ね合
わせたリードで形成するとともに、このリードの金属ま
たは金属半導体化物を有する導体の上面と半導体装置の
電極とを金属または金属半導体化物の連結部で構成せし
め、この半導体装置を70〜300K好ましくは77K以上の温
度で動作せしめんとするものである。The present invention relates to a method for producing a superconducting device using an oxide ceramic superconducting material. The present invention particularly relates to a superconductor device in which a part or all of interconnections of a semiconductor device is formed by a lead in which an oxide superconducting material and a metal or a metal semiconductor compound are superposed on each other, and the lead has a metal or metal semiconductor compound. The upper surface of the conductor and the electrode of the semiconductor device are constituted by a connecting portion of a metal or a metal semiconductor compound, and the semiconductor device is operated at a temperature of 70 to 300K, preferably 77K or higher.
「従来の技術」 従来、超電導材料はNb-Ge系(例えばNb3Ge)等の金属材
料を線材として用い、超電導マグネットとして用いられ
るに限られていた。"Background of the Invention" Conventionally, superconducting materials using Nb-Ge system (eg Nb 3 Ge) metal material such as wires, have been limited to use as a superconducting magnet.
また最近はセラミック材料で超電導を呈し得ることが知
られている。しかしこれもインゴット構造であり、薄膜
の超電導材料の形成はまったく提案されていない。Recently, it has been known that a ceramic material can exhibit superconductivity. However, this is also an ingot structure, and formation of a thin film superconducting material has not been proposed at all.
いわんや、この薄膜をフォトリソグラフィ技術によりパ
ターニングする方法も、またこれをさらに半導体装置の
相互配線の一部に用いることもまったく知られていな
い。In other words, there is no known method of patterning this thin film by photolithography, and its use as a part of interconnection of a semiconductor device.
他方、半導体集積回路を含めた複数の素子を同一基板に
設けた半導体装置が知られている。しかしこの半導体装
置を液体窒素温度(77K)の如き低温で動作させる試み
はまったく知られてない。On the other hand, a semiconductor device in which a plurality of elements including a semiconductor integrated circuit are provided on the same substrate is known. However, no attempt has been made to operate this semiconductor device at a low temperature such as liquid nitrogen temperature (77K).
「従来の問題点」 半導体集積回路は近年益々微細化するとともに高速動作
を要求されている。また微細化とともに半導体素子の発
熱による信頼性低下または発熱部の動作速度の低下が問
題となっていた。“Conventional Problems” In recent years, semiconductor integrated circuits have become more and more miniaturized and are required to operate at high speed. Further, with the miniaturization, there has been a problem that reliability is lowered due to heat generation of the semiconductor element or operation speed of the heat generating portion is lowered.
このため、もし半導体素子を液体窒素温度で動作させん
とすると、その素子での電子およびホールの移動度は室
温のそれに比べて3〜4倍も高めることができ、ひいて
は素子の周波数特性を向上できる。Therefore, if the semiconductor device is operated at the liquid nitrogen temperature, the mobility of electrons and holes in the device can be increased by 3 to 4 times as much as that at room temperature, and the frequency characteristic of the device is improved. it can.
またかかる問題を解決するため、本発明人の出願(昭和
62年3月9日出願超伝導半導体装置 特願昭62-05372
4)を用いんとしたものである。かかる超電導体半導体
装置において、そのリード線はセラミック材料の超電導
材料よりなる。かかる材料は被形成面上に材料を形成し
た後、酸化物雰囲気で長時間の酸化をしなければならな
い。そのため、半導体素子の電極部においては、その素
子を構成する半導体の酸化物が電極部に形成されてしま
う。そしてこの酸化物は一般に絶縁物であり、例えば半
導体がシリコン集積回路においてはその電極部には酸化
珪素絶縁膜が形成されてしまうことが判明した。In addition, in order to solve such a problem, the present application (Showa
Applied on March 9, 62 Superconducting semiconductor device Japanese Patent Application No. 62-05372
4) is not used. In such a superconductor semiconductor device, the lead wire is made of a superconducting material such as a ceramic material. After forming the material on the surface to be formed, such a material must be oxidized in an oxide atmosphere for a long time. Therefore, in the electrode portion of the semiconductor element, the oxide of the semiconductor forming the element is formed in the electrode portion. It has been found that this oxide is generally an insulator, and a silicon oxide insulating film is formed on the electrode portion of a semiconductor such as a semiconductor integrated circuit.
「問題を解決すべき手段」 本発明はかかる問題点を解決するため、半導体装置にお
ける相互配線に低温(70〜300Kの温度)で超電導を呈す
る材料を用いるものである。その際、超電導材料と重ね
合わせて金属または金属半導体化物を設け、半導体素子
の電極部との連結にはこの金属または金属半導体を密接
し、かつ半導体とも酸化物を作らない金属または合金の
半導体化物により構成せしめている。[Means for Solving the Problem] In order to solve such a problem, the present invention uses a material exhibiting superconductivity at a low temperature (temperature of 70 to 300K) for interconnection in a semiconductor device. At that time, a metal or metal semiconductor compound is provided by superimposing it on the superconducting material, and the metal or metal semiconductor is brought into close contact with the electrode portion of the semiconductor element, and a metal or alloy semiconductor compound which does not form an oxide with the semiconductor is formed. It is configured by.
本発明は半導体特に好ましくは耐熱性を有する半導体、
例えば単結晶シリコン半導体基板を用いて、この半導体
に複数の素子、例えば絶縁ゲイト型電界効果トランジス
タ、バイポーラ型トランジスタ、SIT(静電誘導型トラ
ンジスタ)、抵抗、キャパシタを設ける。そしてこの上
に、またその上面の絶縁膜を耐熱性絶縁材料特に好まし
くは耐熱性窒化珪素または酸化珪素を設ける。そしてこ
の絶縁膜上に電気抵抗が零または零に近い酸化物超電導
材料の薄膜材料を形成する。さらにこの上に銅、銀、
金、アルミニウム、WSi2,MoSi2等の金属の半導体化物の
薄膜を形成する。次にこの金属または金属の半導体化物
と超電導材料をともにフォトリソグラフィ技術により選
択エッチをしてパターニングをする。The present invention is a semiconductor, particularly preferably a semiconductor having heat resistance,
For example, a single crystal silicon semiconductor substrate is used, and a plurality of elements such as an insulating gate type field effect transistor, a bipolar type transistor, a SIT (static induction type transistor), a resistor and a capacitor are provided on this semiconductor. Then, a heat-resistant insulating material, particularly preferably heat-resistant silicon nitride or silicon oxide is provided on this and the insulating film on the upper surface thereof. Then, a thin film material of an oxide superconducting material having an electric resistance of zero or close to zero is formed on the insulating film. On top of this, copper, silver,
A thin film of a metal semiconductor such as gold, aluminum, WSi 2 , MoSi 2 is formed. Next, the metal or the semiconductor compound of the metal and the superconducting material are both selectively etched by the photolithography technique and patterned.
本発明においては、絶縁物基板上に超電導材料およびそ
の上面に金属または金属半導体化物の導体を設け、かか
るリードの導体上にフリップチップをワイヤボンド法に
よりバンプまたはワイヤの連結部を用い半導体集積回路
装置、抵抗等を設けてもよい。According to the present invention, a superconducting material and a conductor of a metal or a metal-semiconductor compound are provided on an upper surface of an insulating substrate, and a flip chip is mounted on the conductor of such a lead by a wire bonding method using bumps or connecting portions of a semiconductor integrated circuit. A device, a resistor, etc. may be provided.
「作用」 かかる半導体装置を液体窒素温度とすると、その電子ま
たはホール移動度は3〜4倍に向上させることができ
る。加えて、そのリード、電極の電気抵抗を零または零
に等しくすることが可能となる。周波数特性の遅れを示
すCR時定数におけるR(抵抗)を零とすることができ、
そのためきわめて高速動作をさせることが可能となる。"Operation" When the temperature of such a semiconductor device is set to the liquid nitrogen temperature, its electron or hole mobility can be improved 3 to 4 times. In addition, the electric resistance of the leads and electrodes can be made zero or equal to zero. R (resistance) in the CR time constant indicating the delay of the frequency characteristic can be set to zero,
Therefore, extremely high speed operation can be performed.
以下に本発明の実施例を図面に従って説明する。Embodiments of the present invention will be described below with reference to the drawings.
「実施例1」 第1図は絶縁ゲイト型電界効果半導体装置の実施例を示
す。Example 1 FIG. 1 shows an example of an insulating gate type field effect semiconductor device.
第1図(A)において、シリコン半導体基板(1)を構
成せしめた。さらにアクティブ素子を構成せしめる領域
を除き絶縁表面を有するフィールド絶縁膜(2)を選択
酸化法で形成する。さらにゲイト絶縁膜(3)を約200
Åの厚さで高温酸化法により形成せしめる。次にその表
面にきわめて薄く、窒化珪素膜を構成せしめた。このブ
ロッキング用膜(4)は酸化珪素膜とアンモニア等で反
応せしめる固相−気相反応とし、5〜20Åの厚さとす
る。In FIG. 1 (A), a silicon semiconductor substrate (1) was constructed. Further, a field insulating film (2) having an insulating surface is formed by a selective oxidation method except for a region which constitutes an active element. Furthermore, about 200 gate insulating film (3)
Å Thickness is formed by high temperature oxidation method. Next, a very thin silicon nitride film was formed on the surface. The blocking film (4) is a solid-gas phase reaction in which a silicon oxide film is reacted with ammonia or the like, and has a thickness of 5 to 20 Å.
次にスパッタ法によりこの基板全体を700℃とし、酸化
物超電導材料を構成せしめた。この場合はターゲットと
してYBa2Cu3.6O6〜8を用いた。そして形成される薄膜
(5)は熱アニールをすることなしに超電導特性を呈す
るYBa2Cu3O6〜8とし、Tcoは84Kを得るプロセスとした。Next, the entire substrate was heated to 700 ° C. by a sputtering method to form an oxide superconducting material. In this case, YBa 2 Cu 3.6 O 6 to 8 was used as the target. The thin film (5) formed was made of YBa 2 Cu 3 O 6 to 8 exhibiting superconducting properties without thermal annealing, and Tco was set to 84K.
この酸化物超電導材料(5)の厚さは0.1〜2μm例え
ば0.5μmとした。The thickness of the oxide superconducting material (5) was 0.1 to 2 μm, for example 0.5 μm.
次にこの上面に金属膜(6)を同装置を用いてスパッタ
法により形成した。ここでは銅、銀または金で100〜100
00Åの導体を形成した。さらにその上にTiSi2を0.1〜0.
5μm例えば0.3μmの厚さに形成してもよい。この半導
体基板(1)の一部としてSiのかわりにリンまたはホウ
素が添加された基板と同一主成分材料の珪素であって
も、またタングステン等の非酸化性耐熱性金属であって
も、さらにWSi2等の金属半導体化物であってもよい。こ
の実施例では耐熱性を必要とするため、耐熱材料を用い
た。Next, a metal film (6) was formed on this upper surface by a sputtering method using the same apparatus. Here 100-100 with copper, silver or gold
A conductor of 00Å was formed. On top of that, TiSi 2 is 0.1-0.
The thickness may be 5 μm, for example, 0.3 μm. Silicon, which has the same main component material as the substrate to which phosphorus or boron is added instead of Si as a part of the semiconductor substrate (1), or a non-oxidizing heat-resistant metal such as tungsten, It may be a metal semiconductor compound such as WSi 2 . In this example, a heat resistant material was used because heat resistance is required.
かくして第1図(A)における多層膜(7)を形成し
た。Thus, the multilayer film (7) in FIG. 1 (A) was formed.
さらにこれにフォトレジスト(8)を選択的に設け、こ
のフォトレジストのない部分の導体(6)および酸化物
超電導材料(5)をエッチング法により除去した。この
酸化物超電導材料は酸例えば硫酸または塩酸によりエッ
チングが可能である。Further, a photoresist (8) was selectively provided on this, and the conductor (6) and the oxide superconducting material (5) in the portion without the photoresist were removed by an etching method. The oxide superconducting material can be etched with an acid such as sulfuric acid or hydrochloric acid.
導体(6)の選択的除去は公知のプラズマエッチングを
用いて行った。The selective removal of the conductor (6) was performed by using known plasma etching.
この後フォトレジスト(8)を除去した。After this, the photoresist (8) was removed.
かくして得られた第1図(B)においては、フィールド
絶縁膜(2)上のリード(10)(半導体の電極と連結す
るためのリード),酸化物超電導材料を用いたリード
(10′),ゲイト(11)も設けられた酸化物超電導材料
を用いたゲイト電極(9)とを有する。さらにこの後イ
オン注入法および熱アニールによりソース(12),ドレ
イン(13)を構成した。この熱アニールは超電導材料の
特性を向上させるべく950℃で行う。その後徐冷し、さ
らに500〜600℃での1〜2時間の追加アニールを行っ
た。この追加アニールにより酸化物超電導材料は正方晶
形より斜方晶形を有する変形ペルブスカイト構造とな
り、超電導特性が向上する。In FIG. 1 (B) thus obtained, a lead (10) on the field insulating film (2) (a lead for connecting with a semiconductor electrode), a lead (10 ') using an oxide superconducting material, The gate (11) is also provided with a gate electrode (9) using an oxide superconducting material. After that, the source (12) and drain (13) were constructed by ion implantation and thermal annealing. This thermal anneal is performed at 950 ° C. to improve the properties of the superconducting material. After that, it was gradually cooled, and additional annealing was performed at 500 to 600 ° C. for 1 to 2 hours. By this additional annealing, the oxide superconducting material becomes a deformed perovskite structure having an orthorhombic structure rather than a tetragonal structure, and the superconducting property is improved.
この後これら全体に気相法により層間絶縁膜(10)(例
えば酸化珪素)を0.3〜1μmの厚さに形成し、さらに
公知のフットエッチング法により開穴部(15),(16)
を構成せしめた。開穴部(15)はその一部において多層
のリード(10)の上部の導体を露呈せしめ、その他部に
おいて半導体素子の電極部(15−2)を構成せしめる。
次に2層目のリード(18)を作り、同時にリード(10)
の上面(15−1)と電極(15−2)との連結部(19)を
構成する。After that, an interlayer insulating film (10) (for example, silicon oxide) is formed in a thickness of 0.3 to 1 μm on the whole by a vapor phase method, and the hole portions (15), (16) are further formed by a known foot etching method.
I made it. Part of the opening (15) exposes the conductor above the multilayer lead (10), and the other part constitutes the electrode part (15-2) of the semiconductor element.
Next, make the second layer lead (18) and at the same time lead (10)
Forming a connecting portion (19) between the upper surface (15-1) of the electrode and the electrode (15-2).
これはアルミニウムを0.3〜1μmの厚さに形成し、そ
のフォトエッチングにおいて第1図(D)に示す如くに
構成せしめた。This was formed by forming aluminum to a thickness of 0.3 to 1 .mu.m and performing photoetching on it as shown in FIG.
かくして抵抗零のリード(10)と半導体素子の電極部
(15−2)との電気的連結(19)は酸化物超導体材料が
間接的に導体(19)を介しての連結をせしめ、熱処理に
より材料の酸化物が電極部に形成されやすい絶縁膜の生
成を防ぎつつ互いに連結させることができた。Thus, the electrical connection (19) between the lead (10) having zero resistance and the electrode portion (15-2) of the semiconductor element is such that the oxide superconductor material indirectly connects through the conductor (19), It was possible to connect the oxides of the material to each other while preventing the formation of the insulating film that is easily formed on the electrode portion.
第1図(D)において、(18)は金属リードのみである
ため、材料を選択し、これを抵抗材料として作用せしめ
ることも可能である。In FIG. 1 (D), (18) is only a metal lead, so it is possible to select a material and make it act as a resistance material.
また(18)の2層目の配線をアルミニウムの金属膜を0.
1〜0.3μmの厚さに設けて、その上に非反応性金属を0.
05〜0.2μmの厚さに形成し、さらにその上に酸化物超
電導材料を構成せしめ、これちをフォトエッチングをし
てリードを構成する場合、2層目も抵抗零のリードとす
ることが可能である。The wiring of the second layer of (18) is a metal film of aluminum.
It is provided to a thickness of 1 to 0.3 μm, and a non-reactive metal is deposited on it.
If the lead is formed by forming the oxide superconducting material on it with a thickness of 05 to 0.2 μm and then photoetching this, the second layer can also be a lead with zero resistance. Is.
即ち、1層目の配線はリードが酸化物超電導材料とその
上に導体(金属、半導体または金属半導体化物)を設
け、2層目の配線においては半導体とオーム接触し、か
つ酸化物超電導材料と反応しない導体を設け、その導体
の上に酸化物超電導材料を設けることにより、ともに抵
抗を零として、連結部において金属導体同志を互いに密
接せしめるようにした。That is, in the wiring of the first layer, the lead has an oxide superconducting material and a conductor (metal, semiconductor, or metal-semiconductor compound) formed thereon, and in the wiring of the second layer, the ohmic contact is made with the semiconductor, and A conductor that does not react is provided, and an oxide superconducting material is provided on the conductor so that the resistance is zero and the metal conductors are brought into close contact with each other at the connecting portion.
本発明において、超電導セラミックスに密接して銅、銀
または金を用いた。しかし、金属は半導体にとっては侵
入型原子となるため、半導体に密接せしめるのはアルミ
ニウム、WSi2、MoSi2,Siとして良好なオーム接触をせし
めた。In the present invention, copper, silver or gold was used in close contact with the superconducting ceramics. However, since the metal becomes an interstitial atom for the semiconductor, it is possible to make a good ohmic contact with aluminum, WSi 2 , MoSi 2 , and Si that are brought into close contact with the semiconductor.
かくして第1図(D)に示す如く、電界効果半導体装置
を複数ケ同一基板に設け、超LSIを得ることが可能とな
った。Thus, as shown in FIG. 1D, it is possible to provide a plurality of field effect semiconductor devices on the same substrate and obtain a VLSI.
第1図(A)において、酸化物超電導材料はスパッタ法
で形成した。しかしスクリーン印刷法、真空蒸着法また
は気相法(CVD法)を用いてもよい。スパッタに際して
はその実施例として、基板温度700℃、アルゴン・酸素
雰囲気、周波数50Hz、出力100Wで行った。かかる場合の
セラミック材料の膜厚を0.2〜2μm、例えば1μmの
厚さとして、被膜形成と同時に薄膜がより超電導を呈す
る結晶を成長させやすくすべくTcオンセット=95K(抵
抗は95Kより下がりはじめ、実験的には79Kで抵抗は実質
的に零になった)の超電導薄膜を作ることができた。In FIG. 1 (A), the oxide superconducting material was formed by the sputtering method. However, a screen printing method, a vacuum vapor deposition method or a vapor phase method (CVD method) may be used. As an example of the sputtering, the substrate temperature was 700 ° C., the atmosphere was argon / oxygen, the frequency was 50 Hz, and the output was 100 W. In such a case, the thickness of the ceramic material is set to 0.2 to 2 μm, for example, 1 μm, and Tc onset = 95K (the resistance starts to drop below 95K, in order to facilitate the growth of a crystal in which the thin film exhibits superconductivity simultaneously with the formation of the film. Experimentally, a superconducting thin film with a resistance of substantially zero at 79K could be made.
本発明の酸化物超電導材料は(A1-xBx)yCuzOw(Aは元素
周期表IIIa族より選ばれた1種または複数種の元素、B
は元素周期表IIa族より選ばれた1種または複数種の元
素で、x=0.1〜1,y=2.0〜4.0好ましくは2.5〜3.5,z=
1.0〜4.0好ましくは1.5〜3.5,w=4.0〜10.0好ましくは
6〜8を主成分とする)を用いている。The oxide superconducting material of the present invention is (A 1-x Bx) yCuzOw (A is one or more elements selected from Group IIIa of the periodic table of elements, B
Is one or more elements selected from Group IIa of the Periodic Table of Elements, and x = 0.1 to 1, y = 2.0 to 4.0, preferably 2.5 to 3.5, z =
1.0 to 4.0, preferably 1.5 to 3.5, w = 4.0 to 10.0, preferably 6 to 8) is used.
「実施例2」 第2図(A)は第1図(D)の実施例の変形である。第
2図(A)において、酸化物超電導材料を有するリード
(10)は下側に第1の金属リード(6−2)を設け、そ
の上に酸化物超電導材料のリード(5)を、その上に酸
化物超電導材料と反応をして絶縁物を作らない導体(6
−1)とを有する3層構造のリード(10)を設けてい
る。さらにこのリード(10)の電極部(15−1)と半導
体の電極(15−2)とを導体の連結部(19)を構成する
導体により互いを連結せしめた。Example 2 FIG. 2 (A) is a modification of the example of FIG. 1 (D). In FIG. 2 (A), a lead (10) having an oxide superconducting material is provided with a first metal lead (6-2) on the lower side thereof, and a lead (5) of an oxide superconducting material is provided thereon. Conductor that does not form an insulator by reacting with the oxide superconducting material (6
-1) and a lead (10) having a three-layer structure. Further, the electrode portion (15-1) of the lead (10) and the semiconductor electrode (15-2) were connected to each other by a conductor forming a conductor connecting portion (19).
かかる連結部(19)はそれぞれと十分抵抗の低いオーム
接触をさせることが重要である。例えばタングステンの
選択成長法を用いている。するとその他の連結部(1
9′)をも有する。そのため、このリード(18)はその
下面を酸化物超電導材料(21)、さらにそれに密接して
金属の導体(22)との多層構造とせしめ得る。It is important that the connecting portions (19) make ohmic contact with each other with sufficiently low resistance. For example, the selective growth method of tungsten is used. Then, other connecting parts (1
Also has 9 '). Therefore, the lower surface of the lead (18) can have a multilayer structure including the oxide superconducting material (21) and the metal conductor (22) in close contact therewith.
「参考例」 第2図(B)に参考例を示す。第2図(B)における基
板は耐熱性絶縁基板(1)であり、例えば熱膨張係数を
合わせたアルミナ基板、YSZ(イットリウム・スタビラ
イズド・ジルコン),チタン酸ストロンチウムである。
この上に酸化物超電導材料を実施例1と同様にして設け
た。さらにこの上に導体を銅、銀を用いて設け、これら
プリント配線用基板上に半導体装置等のチップ(20)を
フェイスダウン方式にバンプ(21)(連結部)を用いて
連結した。“Reference Example” A reference example is shown in FIG. The substrate in FIG. 2 (B) is a heat-resistant insulating substrate (1), for example, an alumina substrate having a matched thermal expansion coefficient, YSZ (yttrium stabilized zircon), or strontium titanate.
An oxide superconducting material was provided thereon in the same manner as in Example 1. Further, a conductor was provided thereon by using copper and silver, and a chip (20) such as a semiconductor device was connected to these printed wiring boards by a bump (21) (connecting portion) in a face-down method.
かかる構造においては、基板内に熱処理に敏感なアクテ
ィブ素子がない等の熱処理条件が容易になる特長を有す
る。しかし精密なパターニングを行いにくいという欠点
を有する。Such a structure has a feature of facilitating heat treatment conditions such as no active element sensitive to heat treatment in the substrate. However, it has a drawback that it is difficult to perform precise patterning.
「効果」 本発明により半導体装置を室温ではなく、冷却して形成
する場合において実用化が初めて可能となった。"Effects" The present invention makes it possible for the first time to put the semiconductor device into practical use when it is formed by cooling the semiconductor device at room temperature.
特に半導体は液体窒素温度に冷却することにより周波数
特性を向上させることができる。そして他方、低温にす
ることにより抵抗が増してしまう金属を用いることな
く、本発明は超電導材料を用いた。In particular, the frequency characteristics of a semiconductor can be improved by cooling it to the temperature of liquid nitrogen. On the other hand, the present invention uses a superconducting material without using a metal whose resistance increases at a low temperature.
そのため、本発明の技術思想を発展させることにより、
16M〜1Gビット等の超々LSIに対する応用も可能となっ
た。Therefore, by developing the technical idea of the present invention,
It has become possible to apply to ultra super LSI such as 16M to 1G bit.
本発明は超電導材料を銅の酸化物の超電導材料とした。
しかし微細パターンができる他の超電導材料を用いるこ
とも有効である。In the present invention, the superconducting material is a copper oxide superconducting material.
However, it is also effective to use another superconducting material capable of forming a fine pattern.
第1図は本発明の製造工程を示す。 第2図は本発明の他の実施例を示す。 FIG. 1 shows the manufacturing process of the present invention. FIG. 2 shows another embodiment of the present invention.
フロントページの続き (56)参考文献 特開 昭64−27244(JP,A) 特開 昭63−318755(JP,A) 特開 昭60−154613(JP,A) Physical Review Le tters,vol58,No9.PP. 908−910(2 Mar 1987) Japanese Journal o f Applied physics,v ol.26,No.6(June 1987), PP.L1017〜L1018Continuation of the front page (56) Reference JP-A-64-27244 (JP, A) JP-A-63-318755 (JP, A) JP-A-60-154613 (JP, A) Physical Review Letters, vol58, No9 . PP. 908-910 (2 Mar 1987) Japanese Journal of Applied physics, vol. 26, No. 6 (June 1987), PP. L1017 ~ L1018
Claims (1)
導材料の薄膜と、該薄膜上に銅または銀または金の薄膜
とを設ける工程と、 これら多層薄膜を選択的に除去して他部をリードとする
工程と、 このリードの上部の銅または銀または金と前記基板上の
半導体の電極部とをアルミニウムまたはWSi2またはMoSi
2またはSiにより連結せしめる工程とを有することを特
徴とする超電導体装置の作製方法。1. A step of providing a thin film of an oxide superconducting material on a field insulator on a substrate, and a thin film of copper, silver or gold on the thin film, and selectively removing the multilayer thin film from other parts. And the copper or silver or gold on the upper part of the lead and the electrode part of the semiconductor on the substrate are aluminum or WSi 2 or MoSi.
2. A method for producing a superconductor device, comprising the step of connecting with 2 or Si.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62202143A JPH0736404B2 (en) | 1987-08-13 | 1987-08-13 | Method for manufacturing superconductor device |
| CN88106054A CN1017110B (en) | 1987-08-13 | 1988-08-13 | A superconducting device |
| EP88307561A EP0303521A3 (en) | 1987-08-13 | 1988-08-15 | Superconducting device and methods of manufacturing the same |
| US07/751,573 US5283465A (en) | 1987-08-13 | 1991-08-22 | Superconducting lead on integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62202143A JPH0736404B2 (en) | 1987-08-13 | 1987-08-13 | Method for manufacturing superconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6445144A JPS6445144A (en) | 1989-02-17 |
| JPH0736404B2 true JPH0736404B2 (en) | 1995-04-19 |
Family
ID=16452671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62202143A Expired - Fee Related JPH0736404B2 (en) | 1987-08-13 | 1987-08-13 | Method for manufacturing superconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0736404B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2553101B2 (en) * | 1987-09-04 | 1996-11-13 | 株式会社東芝 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0648733B2 (en) * | 1984-01-25 | 1994-06-22 | 株式会社日立製作所 | Cryogenic semiconductor device |
| JPS6427244A (en) * | 1987-04-08 | 1989-01-30 | Hitachi Ltd | Wiring construction of integrated circuit |
| JPS63318755A (en) * | 1987-06-22 | 1988-12-27 | Mitsubishi Electric Corp | Semiconductor device |
-
1987
- 1987-08-13 JP JP62202143A patent/JPH0736404B2/en not_active Expired - Fee Related
Non-Patent Citations (2)
| Title |
|---|
| JapaneseJournalofAppliedphysics,vol.26,No.6(June1987),PP.L1017〜L1018 |
| PhysicalReviewLetters,vol58,No9.PP.908−910(2Mar1987) |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6445144A (en) | 1989-02-17 |
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