JPH0736422B2 - Clock supply circuit - Google Patents

Description

The present invention relates to a clock supply circuit, and more particularly to a clock supply circuit capable of suppressing internal clock skew to a minimum.

(Prior Art) In a clock supply circuit in a large-scale integrated circuit (LSI), the number of F / Fs (flip-flops) connected to a clock line is very large, and therefore the wirings thereof are also long, so that the clock system Design becomes difficult and various problems occur. That is, the load on the clock line becomes large, and the internal clock skew (hereinafter simply referred to as clock skew) and the external clock skew also increase. Since the external clock skew acts to limit the performance of the LSI, it is desirable that the skew be as small as possible.

Regarding the internal clock skew as well, if it is not kept small, a data transfer error will occur between F / Fs connected in series, which will cause the LSI to malfunction.

That is, for two F / Fs, the Q output of the front stage and the D of the rear stage
The signal propagation delay between the inputs is the clock skew (that is, the phase shift time at the clock input of two F / Fs).
If it is smaller, the F / F in the subsequent stage will take in the Q output of the previous stage in the same clock cycle and cause a malfunction.

To avoid the occurrence of this phenomenon, Q output of two F / Fs and D
The delay between inputs may be made larger than the clock skew, but if it is made too large, the operation speed of the LSI will be reduced, so it is necessary to keep the internal clock skew as small as possible.

FIG. 4 shows an example of a clock driving system for the F / F group according to the prior art. By arranging the internal clock lines in a branch shape in this way, the difference in delay between the wirings can be made relatively small, and therefore the clock skew can be suppressed to a certain extent.

However, when the circuit scale of the LSI has become large as in recent years, the number of F / Fs in the chip has reached to several thousand, the wiring length of the clock line has become considerably large as a whole, and the first buffer 1 The variation in the length of the wiring from the output of the second buffer 2 connected to each F / F also becomes large.

FIG. 5 shows another clock driving method according to the prior art.
In this example, the buffer is divided into two layers, the buffer 1'of the first layer drives the buffers 2'-N 'in the second layer, and each buffer is divided so as to drive each dependent F / F. It uses a drive system.

In this method, for example, the driving capabilities β 2 and β _{N-1 of the} buffer 2'and the buffer N-1 'having different numbers of F / Fs are used.
Is determined as follows.

The delay time t _AB between A and B and the delay time t _AC between A and C are obtained, and then the load C _DE of the clock line _DE and the load C of the F-G C
_{Find FG} , t _AB + T (β ₂ , c _DE ) = t _AC + T
(Β _N-1 ′, C _FG ) = constant value (where T is the time required to drive each load).

(Problems to be Solved by the Invention) In the driving method shown in FIG. 4, the wiring length is different, for example, from the point A to the point B or the point D, so that a clock delay is caused due to this, and therefore the clock skew is generated. Cause That is, such a collective driving method has a drawback that clock skew cannot be avoided, and cannot be ignored in the case of a large-scale LSI. In addition, since the buffer 2 is of a collective driving type, a large driving capability is required for the buffer 2. Therefore, a large current locally flows through the clock line, resulting in noise and malfunction.

On the other hand, in the divided driving method shown in FIG. 5, the overall calculation for minimizing the clock skew is complicated, and a large number of buffers having different driving forces are required, which makes the circuit design difficult.

Also, if the number of F / Fs dependent on a specific buffer becomes large, the clock skew at both ends cannot be ignored.

[Configuration of the Invention] (Means for Solving the Problems) A clock supply circuit according to the present invention includes a first buffer and a predetermined point on the output side of the buffer to an input of a buffer provided on each of a plurality of channels. There is at least two layers of a first layer including wiring and a second layer composed of each buffer in each channel and each flip-flop group subordinate thereto, and each buffer has the same performance, The wiring lengths of the channels in the first layer are different, and the first channel is adjusted so that the other channels are substantially equal to the clock circuit condition of the specific channel in the first layer having the maximum length of wiring. Is provided in each channel except the specific channel in the first layer, and the number of flip-flops in each channel in the second layer is different. And a second capacitance means for adjusting the clock circuit condition of a specific channel in the second layer having the maximum number of flip-flops so that the clock circuit condition of the other channel becomes substantially equal. It is characterized in that it is provided in each channel except a specific channel.

(Operation) In the clock supply circuit according to the present invention, the clock skew is reduced by driving the equalized circuit conditions and the equalized loads by the respective buffers having the equalized ability.

(Embodiment) FIG. 1 and FIG. 2 are views for explaining the principle of the clock supply circuit according to the present invention.

In the figure, the buffer 11 from the output side of the point A of the buffer 10 in the first hierarchical _-1, 11 _-2, constituting each wiring length and the wiring width to the input of ... 11 _-N to be identical. Further, in the second layer, the buffers 11 _-1 , 11 _-2 , 11 _-3 ... 11 _-N are arranged to have the same driving capability, and F / Fij (j = 1, 2, The number of 4, ... m) and the load wiring are all equal.

In this way, the wiring conditions of each layer and the equalized drive capacity of the distributed buffers, and the F / F subordinate to each buffer
By equalizing the number of Fs, each F / F during operation
It is possible to minimize the clock skew that may occur in the meantime.

Also, in the circuit shown in FIG. 2, the wiring conditions in the first layer are the same as those in FIG. 1, but the number of F / Fs in the second layer, and hence the length of the wiring connecting them are Are different. That is, the respective buffers 11 _-1 , 11 _-2 , 11 _-3 ... 11 _-N dispersed from point A on the output side of the first buffer 10
The wiring conditions leading to the inputs C, D, F, and G are the same. On the other hand, the number of F / F ₁ j (j = 1,2,3 ... P) subordinate to a specific buffer, for example, the buffer 11 _-1 in the second layer, is smaller than that of the channels. Load capacities C ₁ , C ₂ , C ₃ ... C _N-1 for RC delay adjustment are connected to the end of the channel having several F / F connected buffers. The load capacity is the buffer of each channel.
11 _-2, 11 _-3, ... 11 takes a value that is adjusted according to the number of dependent F / F to _-N, and the clock of the reference channel having a buffer 11 _-1 by considering the wiring length of each channel It is adjusted to be substantially the same as the signal delay of the line.

That is, the arbitrary load capacity Ci is calculated as CiJ = insufficient wiring capacity + insufficient gate capacity for the number of F / Fs,
Its value is determined.

As a method of implementing each of the load capacitances Ci, a method of realizing it as a gate capacitance of a MOS transistor is easy to design, and the overhead is the smallest in area, which is preferable. The wiring length of the reference channel that has the most F / F is the F / F at the end immediately after the buffer output.
Naturally, it is necessary to set the value within the range where the adverse effect of clock skew due to RC delay does not appear.

Next, an embodiment of the clock supply circuit according to the present invention will be described with reference to FIG. Here, the clock skew is reduced separately for both the first layer and the second layer. That is, in the circuits of FIGS. 1 and 2, description has been made assuming an ideal case where the conditions in the first layer are uniform in each route, but in reality, such a case is limited. Cage,
This is because it does not lead to general facilitation of design. In this embodiment, each buffer 11 _-1 11 _-2 , ... 11 _-N dispersed from point A on the output side of the first buffer 10 in the first layer
The wiring length is also different up to the input of. In order to prevent the clock skew caused by this, a specific buffer having the longest input wiring, for example, buffer 11 in this case, is used as a reference, and adjustment capacitors C ₁₁ and C for preventing clock skew caused by RC delays of different input wirings are used. ₁₂ , ... C _1N-1 is provided. In this case, the value of each capacitance may be determined according to the shortage of the input wiring.

In this embodiment, the configuration in the second layer is the same as that in FIG. 2, and the method of determining the value of the capacity for each adjustment is also the same as that in FIG. 2, so detailed description will be omitted. To do.

Although the first and second hierarchies are used in the above embodiment, the number of hierarchies is not limited to this.

(Effects of the Invention) The embodiments of the present invention have been described above. However, in the clock supply circuit of the present invention, a first layer including a first buffer portion and wiring to each buffer input of the next stage,
The clock skew is reduced because the buffer is divided into a second layer consisting of each channel including a dependent F / F and each layer is set to a substantially equal circuit state to drive the F / F as a load. It can be kept small.

Further, since the buffers of the same type and the same performance can be used for the buffers of the channels in the second layer, the circuit design becomes easy.

Further, even if there is a difference in the wiring length and the number of dependent F / Fs in the first layer or the second layer, or in the first and second layers, the capacitance that can adjust the circuit state of each channel to be substantially the same. The clock skew can be kept uniform and small even if the driving capability of each buffer of each channel varies to some extent.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining the principle of the clock supply circuit according to the present invention, FIG. 2 is another circuit diagram for explaining the principle of the clock supply circuit according to the present invention, and FIG. 3 is a clock according to the present invention. An embodiment of a supply circuit, FIG. 4 shows one F / F clock driving method according to the prior art, and FIG. 5 shows another F / F clock driving method according to the prior art. 10 ... 1st buffer, 11 _-1 , 11 _-2 , ... 11 _-N is the second buffer of each channel, F / Fij (i = 1,2,3 ... N, j = 1,2, ... m ) ... Each subordinate flip-flop.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-55-115352 (JP, A) JP-A-63-87744 (JP, A) JP-A-62-231498 (JP, A) Actual development Sho-61- 146951 (JP, U)

Claims (1)

[Claims] 1. A first layer including a first buffer and wirings from a predetermined point on the output side of the buffer to an input of the buffer provided in each of a plurality of channels, the buffers in the channels, and the first layer. At least 2 of the second hierarchy composed of flip-flop groups subordinate to
Each of the buffers has the same performance, the wiring lengths of the channels in the first layer are different, and the clock circuit condition of the specific channel in the first layer having the maximum length of wiring is satisfied. A first capacitance means for adjusting the other channels to be substantially equal is provided in each channel except the specific channel in the first layer, and the number of flip-flops in each channel in the second layer is Second capacitance means for adjusting the clock circuit condition of a particular channel in the second layer having a different maximum number of flip-flops so that the clock circuit conditions of other channels are substantially equal to each other. A clock supply circuit provided in each channel except a specific channel in the clock supply circuit.