JPH0736497B2 - amplifier - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier, and more particularly to a high input impedance amplifier suitable for a sample hold circuit and an integrator.

[Conventional technology]

As described in Japanese Patent Laid-Open No. 60-005616, a conventional device is provided with a pseudo input transistor through which a current equivalent to the input transistor flows, detects the base current of the transistor, and inputs the current by a current mirror circuit. It was supplied to the base of the transistor.

[Problems to be solved by the invention]

In the above conventional technique, the input current is detected by the transistor, and the base current cancel circuit is configured by the current mirror circuit that outputs a current substantially equal to the current. Therefore, the input bias current cannot be improved to about 1/100. However, the error due to the base current of the base current detection transistor and the base current in the current mirror circuit was not considered, and the input bias current could not be made zero.

An object of the present invention is to bring the input bias current closer to zero.

[Means for solving problems]

The above-mentioned object is to provide a gain adjusting circuit or a base current canceling circuit in the current mirror circuit to correct the reduction of the current to be canceled due to the base current of the base current detecting transistor and the base current of the current mirror circuit which cause an error. Is achieved by

[Action]

A compensation circuit compensates for the base current of a base current driving transistor in which the base and collector of the input side transistor of the current mirror circuit are connected, and the base current of the input base current detecting transistor. As a result, the same current value as the detected base current value can be supplied to the base of the input transistor of the amplifier, and the input bias current of the amplifier can be made zero.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. First
The figure shows a high input impedance amplifier used in a sample and hold circuit of a digital audio A / D converter. 23 is an inverting input terminal, 22 is a non-inverting input terminal, 24
Is an output terminal. As shown in FIG. 2, the sample-hold circuit is used by connecting a hold capacitor 85 between the inverting input terminal 23 and the output terminal 24 and grounding the non-inverting input terminal.
86 is an amplifier shown in FIG. 1, 81 is a buffer amplifier,
Reference numerals 82 and 83 are resistors, and 84 is an analog switch, which is turned on in the sample mode and turned off in the hold mode. In the configuration as shown in FIG. 2, the potential of the inverting input terminal 23 is solidified to the ground potential. When the input bias current flows through the inverting input terminal 23, the electric charge accumulated in the capacitor 85 in the hold mode decreases and a so-called droop phenomenon occurs. In order to reduce this, conventionally, an input base current cancel circuit as shown in FIG. 3 has been used. In Figure 3, Q1
01 is the input side transistor of the first stage differential transistor pair, and this base current causes droop. Q102 is a quasi-input transistor and carries the same emitter current as Q101. Q103 is a base current detection transistor for detecting the base current of Q102.
As the base potential (ground potential) of Q101, the power source of 106 is set to Q in order to match the collector-emitter potential of Q101 and Q102.
The base-emitter potential of 103 is used. Q104 and Q105 are current mirror circuits. The base current, emitter current, and collector current of Q102 are represented as IB102, IE102, and IC102, respectively, and the error between the base current of Q101 and the collector current (cancellation current) of Q105 is calculated.

IB101 = IB102 = IE103 = IB103 + IC103 IC103 = IC104 + IB104 + IB105 IE104 = IC104 + IB104 IE105 = IE104 IB105 = IB104 IC105 = IE105−IB105 IC103 = IB102 = IB103 IE104 = IC103−IB105 IC105 = IC103−2IB105 IB101−IB103−2IB105 IB105 It can be seen that the error of occurs.
If the DC current amplification factor h _{FE of the} transistor is sufficiently large, the error will be small, but in principle a cancellation error will occur. When h _FE is reduced in the IC or when used in a high-precision integrating amplifier, the cancel current error becomes a problem.

In FIG. 1, first, emitter follower transistors 31 and 32 are provided in the differential pair transistors 2 and 3 in order to reduce the absolute value of the base current of the first stage input transistor. twenty five
Is a base current compensating circuit, 45 is a pseudo input transistor, and a current equivalent to that of the transistor 2 is made to flow 44 so that currents equal to the transistors 31 and 45 flow. A means for detecting the base current of the transistor 45 is a diode 46. By not using a transistor for 46, the base current error of the transistor 46 can be eliminated. However, since the base potential of the transistor 45 cannot be fixed to the desired potential, a level shift circuit is constructed with the diode 61 and the resistor 62, and the resistance is changed from the power supply voltage supplied to 20.
Base of 52,62, transistors 48,52,61,46. The base potential of the transistor 45 is determined via the emitter voltage. In addition, transistors 48 and 49 of the current mirror circuit
To reduce the error of
52 are provided. Even in this state, an error of 1 / h _FE of the transistor 52 of IB48 + IB49 occurs, so by adding a transistor 63 in series to the transistor 52 and adding this base current to the collector of the output side transistor 49, the base current of the transistor 45 is completely eliminated. Since the same current can be supplied from the collector of transistor 49 and the base of 63, the input bias current can be zero.

FIG. 4 shows another embodiment of the present invention. The base current compensation circuit of FIG. 4 is IB46 + (IB49 + IB48) as in the example of FIG.
/ h _FE52 current error occurs. So the emitter resistance 50,5
1, the base current can be completely canceled by changing the emitter size of the transistors 48 and 49 to give the current mirror circuit a gain. The gain G at this time is You can set it to.

FIG. 5 shows the configuration of FIG. 1 applied to a PNP transistor input and the principle is the same.

FIG. 6 is an example in which the configuration of FIG. 4 is applied to a PNP transistor input, and the operation principle is the same as that of FIG. The base current detection transistor has a 10, 11 Darlington configuration.

In FIG. 7, the base current detection means is a diode 10, the level shift circuits 61 and 62 determine the base potential of the transistor 9 from the negative power source 21, and the transistor base current error in the current mirror circuit is compensated by the gain of the mirror circuit. is doing.

〔The invention's effect〕

As described above, according to the present invention, since the base current error in the base current compensation circuit of the amplifier input transistor can be completely compensated, the input bias current can be reduced to zero, and the high performance sample hold circuit and There is an effect that the high-performance integrating amplifier can be constructed by an inexpensive bipolar process.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a sample and hold circuit in which an amplifier of the present invention is used, FIG. 3 is a conventional base current compensation circuit diagram, and FIG. ,
5, 6 and 7 are circuit diagrams showing another embodiment of the present invention. 45,9 …… Pseudo input transistor, 46,10 …… Base current detection means, 63 …… Mirror circuit Base current compensation transistor, 48,49,50,51 …… Current mirror circuit.

Claims (3)

[Claims] 1. A pseudo input transistor through which a current equivalent to that of a first stage input transistor of a differential pair transistor flows, a base current detecting means for detecting a base current of the pseudo input transistor, a first transistor on an input side and an output side. A current mirror circuit in which the base current detection means is connected to the collector terminal of the first transistor, and the collector terminal of the second transistor is connected to the first stage input transistor. In a base current compensation type amplifier connected to a base terminal to supply a base current from the current mirror circuit to the first stage input transistor, an emitter and a base terminal are respectively connected to a base and a collector terminal of the first transistor. A third transistor and an emitter terminal of the third transistor Is connected to the collector terminal, the base terminal connected to the collector terminal of the second transistor, an amplifier, characterized by comprising a fourth transistor having its collector terminal connected to a reference potential. 2. A pseudo input transistor through which a current equivalent to that of a first stage input transistor of a differential pair transistor flows, a base current detecting means for detecting a base current of the pseudo input transistor, and a first resistor connected to an emitter terminal. A pair of a first transistor on the input side and a second transistor on the output side in which a second resistor is connected to the emitter terminal, and the base current detecting means is connected to the collector terminal of the first transistor. A current mirror circuit, wherein a collector terminal of the second transistor is connected to a base terminal of the first-stage input transistor to supply a base current from the current mirror circuit to the first-stage input transistor. In, the emitter terminal is connected to the base terminal of the first transistor, and the base terminal is A third transistor connected to the collector terminal of the first transistor, the collector terminal of which is connected to a reference potential, and the emitter size of the first and second transistors of the current mirror circuit, or the first and second transistors. An amplifier characterized in that resistance values of resistors connected to the emitter of the second transistor are different from each other. 3. The amplifier according to claim 1, wherein the base current detecting means is a diode, and the base of the pseudo input transistor is between the diode and the collector terminal of the transistor. An amplifier characterized by being connected with a level shift circuit for fixing a potential.