JPH0736522B2 - PLL lock detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

This invention relates to a PLL (Phase
Locked loop) PLL in frequency synthesizer
Lock detection circuit

[0002]

2. Description of the Related Art PL in a PLL frequency synthesizer
As a digital type phase detection circuit forming an L loop, for example, a phase detection circuit 1 as shown in FIG. 1 is known from US Pat. No. 4,110,694.

The outputs PD ₁ and PD ₂ of the phase detection circuit 1 are input to a NAND circuit G ₁₀ , and the output is N channel M.
Prior to the present invention, it is possible to obtain a PLL lock detection signal by applying to the gate electrode of an ISFET (insulated gate type field effect transistor) Q and smoothing the drain output signal of the MISFET Q by the smoothing circuits R ₁ and C _1. Proposed.

In the above circuit, when the PLL loop is in a locked state, the phase detection outputs PD ₁ and PD ₂ match as is well known, but due to a slight time lag, the output of the NAND circuit G ₁₀ has a whisker shape. Pulse is output. Therefore, by smoothing with a smoothing circuit, an average value is obtained and P
The LL lock detection signal is obtained.

Further, since the proposed circuit requires a smoothing circuit, there is a drawback that the external terminal P ₁ and the external components R ₁ and C ₁ are required in making a monolithic IC, and there is a variation in the judgment level. It has the drawback of being affected.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL lock (or unlock) detection circuit which can obtain a highly accurate PLL lock detection signal and can eliminate the smoothing circuit.

[0007]

According to the basic feature of the present invention, a pulse formed by delaying by a time corresponding to about 1/2 of 1 / N frequency division output pulse width of a programmable counter in a PLL frequency synthesizer. The signal is sampled by the reference frequency pulse.

According to another basic feature of the present invention, the PL
An output pulse of a phase detection circuit that constitutes the L frequency synthesizer or a phase detection circuit having a similar configuration to this is used as a PLL lock detection signal in a continuous lock state in a pulse train sampled at a predetermined timing signal.

[0009]

Operation: PLL by signal processing like a digital logic circuit
Since the lock state can be determined, it is not affected by variations in the determination level and a smoothing circuit is not required.

Therefore, when the PLL frequency synthesizer including the PLL lock detection circuit is made into a monolithic IC, the number of external terminals and external components can be reduced.

[0011]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 2 is a block diagram showing an embodiment of the present invention.

In this embodiment, the programmable counter 2 outputs 1 / N divided output, in other words, N pulse count output signals are applied to the input terminal D, and the input signal F _IN of the programmable counter 2 is applied to the clock terminal φ. The output D-type flip-flop circuit 3 having a pulse width corresponding to one cycle of the input signal F _IN from the output Q of the flip-flop circuit 3 and divided by 1 / N
i is formed, is used as an N-value preset gate pulse, is inverted by the inverter circuit IV, and is applied to one input Fi of the phase detection circuit 1 shown in FIG.

A reference frequency REF is applied to the other input of the phase detection circuit 1, and its outputs PD ₁ and PD ₂ are n.
A channel MISFET (insulated gate field effect transistor) Q ₂ and a p-channel MISFET Q ₁ are applied to the gates thereof, and their drains are commonly connected to the output terminal P ₂ .

The phase detection output passed through this output circuit is converted into a DC voltage by the loop filter 6 and applied to the control input terminal of a voltage controlled oscillator (hereinafter abbreviated as VCO) 7. The output of the VCO 7 is applied as the input signal F _IN of the programmable counter 2 via the terminal P ₃ and is used as, for example, the local oscillation frequency signal f _LOC in the radio receiver.

By the operation of the PLL loop, the VCO 7 is controlled so that the frequencies (phases) of the input signals Fi and REF of the phase detection circuit 1 match. Therefore, V
The oscillation frequency of CO7 can be made equal to N times the reference frequency REF when the PLL loop is locked.

In order to configure the PLL lock detection circuit in such a PLL frequency synthesizer, in this embodiment, the output signal bar Fi of the D-type flip-flop circuit 3 is applied to the input terminal D and the input signal of the programmable counter 2 is applied. The D-type flip-flop circuit 4 to which the inverted signal of F _IN is applied to the clock terminal φ, and the output signal bar Fi ′ of this flip-flop circuit 4 is applied to the input terminal D, and the inverted reference frequency signal REF is applied to the clock terminal φ. φ
And a D-type flip-flop circuit 5 applied to. The lock detection signal LOCK is obtained from the output Q of the flip-flop circuit 5.

The operation of this embodiment circuit will be described below with reference to the operation waveform diagram shown in FIG.

The frequency-divided output from the programmable counter 2 is usually obtained as a count-up or count-down clear signal. In this embodiment, although not particularly limited, a down counter circuit is used and its coefficient content is 2
At this time, the output signal n which becomes low level is transmitted to the flip-flop circuit 3.

At this time, since the falling edge of the output signal n at the low level has a delay time td, the flip-flop circuit 3 reads this low level at the falling edge of the input pulse F _IN of the next cycle. It becomes low level. Therefore, the output signal bar Fi of the flip-flop circuit 3 becomes low level when the count content of the programmable counter 2 is 1. And this output signal bar F
The preset gate circuit is opened by i and the N value is set in the programmable counter 2. Therefore, the content of the programmable counter 2 changes from 1 to N. The output signal n of the programmable counter 2 changes to the high level in accordance with the earlier timing of the input of the N value or the count content of the counter becoming 1. At this time as well, since there is a delay time similar to the above, the output signal bar Fi of the flip-flop circuit 3 is read at the high level at the rising edge of the input pulse F _IN of the next cycle. Therefore, the divided output bar Fi which becomes low level for one cycle of the input pulse F _IN is obtained. Since the preset state of the programmable counter 2 is canceled at the high level of the frequency division output bar Fi, the down count operation is performed from the preset content N '. This operation description shows the case where a new N value, for example, N + 1 = N 'is set.

On the other hand, 1 / N formed as described above
The divided output bar Fi is applied to the input terminal D of the p-type flip-flop circuit 4, and the output signal of the inverter circuit IN forming the inverted signal of the input signal F _IN is applied to the clock terminal φ of the D-type flip-flop circuit 4. When applied, the output signal bar Fi 'of the D-type flip-flop circuit 4 becomes 1
The signal is delayed by a half cycle of the input signal F _IN with respect to the / N frequency-divided signal bar Fi. That is, the D-type flip-flop circuit 4 takes in the input signal at the front edge of the clock pulse.

Since this clock pulse is obtained by inverting the input signal F _IN by the inverter circuit IN, the back edge (falling edge) of the input signal F _IN indicates that the D-type flip-flop circuit 4 However, the 1 / N frequency division signal bar Fi is taken in.

Therefore, the D-type flip-flop circuit 4
Of the output signal bar Fi 'of
On the other hand, the pulse width (low level period) may be delayed by a time corresponding to ½ of the pulse width.

On the other hand, in the PLL lock state, the phase of the reference frequency signal REF and the pulse Fi obtained by inverting the 1 / N frequency-divided signal bar Fi by the inverting circuit IV and inputting it to the phase detection circuit 1 match. . Specifically, the back edges (falling edges) of both pulses REF and Fi coincide.

This locked state can be detected with high precision by the D-type flip-flop circuit 5. The output signal bar Fi 'of the D-type flip-flop circuit 4 is applied to the input terminal D of the D-type flip-flop circuit 5, and the reference frequency signal bar REF inverted by the inversion circuit IV is applied to the clock terminal φ. Has been done. Therefore, regarding the reference frequency signal REF, the D-type flip-flop circuit 5 synchronizes with the falling edge of the signal bar F.
i'takes in. In the PLL lock state, the back edges of both the pulses REF and Fi coincide with each other as described above, and the low level period of the signal bar Fi ′ is the pulse width (high level period) of the pulse Fi. It is delayed by a time corresponding to 1/2.

Therefore, the D-type flip-flop circuit 5
The back edge of the reference frequency REF, which is the sampling timing of the
It coincides with the midpoint of the low level period of i '.

For example, in the PLL lock state in which the divided output signal Fi 'is at the low level with respect to the back edge of the reference frequency REF by the sampling operation in the D flip-flop circuit 5 as described above. , D
The lock detection signal LOCK obtained from the non-inverted output signal Q of the type flip-flop circuit 5 remains at the low level, and the unlock detection signal bar LOCK obtained from the inverted output terminal bar Q remains at the high level.

When the new preset information N '(N + 1) is input to the programmable counter 2 as described above, the reference frequency REF has a constant cycle, whereas the programmable counter circuit 2 and the flip-flop circuit 3 have the same cycle. The frequency-divided output bar Fi formed in 1 is delayed by one cycle of the input pulse F _N (Δθ). Therefore, the divided output bar Fi ′ at the back edge of the reference frequency REF
Becomes a high level, the lock detection signal LOCK obtained from the D-type flip-flop circuit 5 is changed to a high level and the unlock detection signal bar LOCK is changed to a low level by the sampling operation as described above, and the unlock state is changed. Detection is performed. The back edge phase difference Δθ between the reference frequency REF and the frequency-divided output Fi is detected by the phase detection circuit 1 and is controlled to increase the oscillation frequency of the VCO 7. By the operation of the PLL loop as described above, the phases of the both are made to match again.

Since the delayed 1 / N frequency-divided output pulse bar Fi 'follows the 1 / N frequency-divided output pulse bar Fi (Fi), both input signals Fi and REF in the phase detection circuit 1 are compared. When the phase difference is within the half cycle of the input signal F _IN , it is determined that the lock state is established.

In this embodiment, since the PLL lock state can be discriminated by the signal processing like a digital logic circuit as described above, it is not affected by the variation of the discrimination level and the smoothing circuit is not required.

Therefore, when the PLL frequency synthesizer including the PLL lock detection circuit is formed into a monolithic IC, the number of external terminals and external components can be reduced.

The PLL lock detection signal is, for example, an FM / FM signal having a PLL frequency synthesizer tuner.
When applied to an AM radio receiver, it is used as an N-value update in an automatic scan operation or as a control signal for audio mute.

FIG. 4 is a block diagram showing another embodiment of the present invention.

Only the PLL lock detection circuit is shown in the block diagram of this embodiment.

In this embodiment, the PLL shown in FIG. 1 is used.
A D-type flip-flop circuit 8, a shift register 9 and a NOR gate circuit G ₁₁ are used instead of the N-channel MISFET Q and the smoothing circuit in the lock detection circuit. That is, the NANDs in which the output signals PD ₁ and PD _{2 of} the phase detection circuit 1 described above are applied to their respective input terminals.
The gate circuit G ₁₀ , the D-type flip-flop circuit 8 to which the output signal of the NAND gate circuit G ₁₀ is applied to the input terminal D, and the sampling pulse φs is applied to the clock terminal φ, and the sampling pulse φs are shift clock pulses. As a PLL lock detection circuit, the shift register 9 receives the output signal Q of the D-type flip-flop circuit 8 and the NOR gate circuit G ₁₁ receives the holding signals S _{1 to} S ₅ of the respective stages of the shift register 9. To be done. The sampling pulse φs is, for example, the PLL
It is formed as a pulse having the same frequency as the reference frequency signal REF in the circuit.

The operation of the circuit of this embodiment will be described with reference to the operation waveform diagram of FIG.

Output signals PD ₁ , PD _{2 of the} phase detection circuit 1
When both of the logic levels of 1 are low level (“1”), it is in the locked state, and the output signal of the NAND gate circuit G ₁₀ becomes high level (“0”). Now, at the first sampling timing, the high level signal indicating the locked state is D
When input to the flip-flop circuit 8, the output signal Q of the flip-flop circuit 8 becomes high level.

Then, at the second sampling timing, the high level signal is transferred to the first-stage circuit of the shift register 9 and the second sampling is performed. At this time, the lock state is deviated or the lock is detected. When the unlocked low level is fetched, the output signal Q of the flip-flop circuit 8 changes to the low level again.

Next, at the third sampling timing, in the shift register 9, the high level holding level of the first-stage circuit is transferred to the second-stage circuit, and the output signal of the low-level flip-flop circuit 8 is transferred to the first-stage circuit. Are transferred. When the high level indicating the locked state is formed again at this sampling timing, this high level is taken into the flip-flop circuit.

Thereafter, when the high level indicating the lock state is taken in continuously by the sampling of the D-type flip-flop circuit 8, the data transfer operation in the shift register 9 causes the third signal at the eighth sampling timing. The high level signal indicating the locked state, which is taken in at the eye sampling timing, is transmitted to the final stage circuit.

At this time, since the output signals S _{1 to} S ₅ of the respective stages of the shift register 9 are all at high level (“0”), the NOR gate circuit G ₁₁ forms the low level lock detection signal LOCK. It

In this way, in this embodiment, the low-level lock detection signal LOCK is formed only after the lock state is sampled five times in succession.

If the shift register 9 has n stages, the lock detection signal LOCK can be generated when the lock state is sampled continuously n times.

Therefore, this PLL lock detection circuit does not respond when the output levels of the output signals PD ₁ and PD ₂ in the phase detection circuit 1 accidentally indicate a locked state, and is in a stable locked state. Only at this time, the low-level lock detection signal LOCK can be output, and P
A stable locked state of LL can be detected.

Paying attention to the fact that the shift register 9 substantially counts the sampling pulse φs, an equivalent operation can be performed by using a counter circuit. That is, the unlock detection level in the NAND gate circuit is used as the reset signal of the counter circuit that receives a constant pulse signal such as the sampling pulse φs. Then, the overflow (count-up) signal of this counter circuit is used as the lock detection signal LOCK. In this case, it is determined whether or not the locked state continues for the time required for counting up. As described above, when the counter circuit is used, the circuit can be simplified as compared with the case where the shift register is used.

That is, in the case of using a shift register, a binary counter that uses a shift clock pulse as an input pulse signal to be counted can be made to correspond to a 2n-stage shift register by an n-stage flip-flop circuit. .

In the circuits of these embodiments, the smoothing circuit can be eliminated as described above, and the phase detection circuit 1 can be changed to P.
When it is provided separately from the phase detection circuit forming the LL loop, the digital phase detection circuit has a complicated structure as described above, and therefore, by combining with the embodiment circuit of FIG. The circuit as the PLL lock detection circuit can be simplified.

FIG. 6 is a block diagram showing an embodiment in which the present invention is applied to an FM / AM radio receiving apparatus using a PLL frequency synthesizer.

Reference numeral 18f is an FM radio tuner circuit, which includes an RF amplification stage, a mixing stage, an FM intermediate frequency amplification stage, an FM detection stage and an FM stereo demodulation stage.

Reference numeral 18a is an AM radio tuner circuit, which includes an RF amplification stage, a mixing stage, an AM intermediate frequency amplification stage, and an AM.
A detection stage is included.

Local oscillation frequencies f _LF and f _LA to the mixing stage
A PLL frequency synthesizer is used to form the.

That is, these local oscillator circuits are respectively constituted by VCOs 7f and 7a using varactors or the like. Since the local oscillation frequency f _LF for FM is a high frequency, it is divided by the frequency dividing circuit (prescaler) 9 and input to the switching circuit 17 together with the local oscillation frequency f _LA for AM to selectively program. It is applied as the input signal F _IN of the counter 2. A flip-flop circuit 3 similar to the above is provided on the output side of the program counter 2, and its output pulse Fi is inverted by the inverter circuit IV and applied to one input of the phase detection circuit 1. On the other hand, the amplifier circuit 11 and the bias resistor R ₂
The output signal of the reference frequency oscillating circuit composed of the crystal oscillator X and the capacitors C ₄ and C ₅ is frequency-divided through the frequency dividing circuit 12 and the variable frequency dividing circuit 13, and is input to the other input of the phase detecting circuit 1. It is converted into the applied reference frequency signal REF. The detection output of the phase detection circuit 1 is converted into a DC voltage V _DC by the loop filter 6, and the control input terminals of the VCOs 7f and 7a constituting the local oscillation circuit and RF.
It is applied to the inter-stage selection circuit in the amplification stage.

The variable frequency dividing circuit 13 is controlled by the frequency dividing ratio switching circuit 14 and has a plurality of types of reference frequency signals REF.
Are selectively formed. For example, when the oscillation frequency of the reference frequency oscillation circuit is 11.52 MHz, the frequency dividing circuit 12 divides the frequency by 1/2 ⁷ and converts it into 90 KHz. Then, in the variable frequency dividing circuit 13, 1/9, 1/10, 1/18, 1/2
Selective frequency division to 0, 10KHz, 9KHz, 5KH
The reference frequencies REF having different frequencies of z and 4.5 KHz are selectively formed.

Therefore, during AM reception, N × REF
The local oscillation frequency f _LA is formed, at the time of FM reception, 'When, N × N' frequency division ratio of the prescaler 9 N × RE
A local oscillation frequency f _{LF of} F is formed.

Reference numeral 16 is a latch circuit for holding the N value of the program counter 2. The program counter 2 takes in this N value and repeatedly counts it to perform a 1 / N frequency dividing operation.

Reference numeral 15 is a control circuit, which is composed of, for example, a microcomputer, and N to the latch circuit 12 is supplied.
The value is sent out as a binary code BCD, or various control signals for the receiving operation, such as the frequency division ratio switching control signal C and FM / AM switching control signal, are formed.

In this embodiment, flip-flop circuits 4 and 5 similar to those shown in FIG. 2 are provided as the PLL lock detection circuit. Then, the unlock level in the lock detection signal of the flip-flop circuit 5 that performs the sampling operation as described above is applied to the counter circuit 10 as a reset signal, and the counter circuit 10
A predetermined timing pulse φ _T of the control circuit 15 is applied to the input terminal IN of. And this counter circuit 1
The overflow signal OUT of 0 is set to the lock detection signal LOC.
K is input to the control circuit 15.

As described above, the counter circuit 10 is provided in order to form the lock detection signal LOCK by discriminating the stable lock state as described above. That is, this is to prevent the temporary lock detection signal LOCK from being output under the unlocked state.

This lock detection signal is used as an N value update timing signal in the automatic search operation.

That is, when updating the N value, it is necessary to determine that the PLL loop is in the locked state and there is no receiving station, and update the N value.

It is also used to form a mute signal to the FM / AM tuner circuits 1 and 2. This prohibits noise output between stations. For example, PL
When the L loop is in the unlocked state, it is when the tuning is not accurately performed, so the audio output for canceling the noise between the stations is muted.

During the automatic search operation as described above, if there is no receiving station even in the locked state, the mute operation is performed by the receiving station detection signal.

Of each circuit block constituting the PLL frequency synthesizer, a portion surrounded by a dotted line IC is formed on a one-chip silicon substrate by a well-known semiconductor manufacturing method. The numbers enclosed in circles indicate the terminal numbers. However, the input terminals 6 and 7 of the control circuit are configured as a terminal group, and the input terminal 6 receives the tuning data (N value) and various operation mode signals, and the terminal 7
From, a digital number display signal of the receiving station, a mute control signal, and the like are output.

The audio output from each tuner circuit 18f, 18a is selectively input to the low frequency power amplifier circuit 20 via the switching circuit 19. The low frequency power amplifier circuit and the speaker for stereo reproduction are omitted.

[0065]

When the PLL lock detection signal is processed in the monolithic IC as in the circuit of this embodiment, the number of external terminals and external components can be reduced by reducing the number of smoothing circuits. In particular, as in this embodiment, when the multi-function is made into a one-chip IC, the restrictions on the external terminals are great, so it is extremely useful to reduce the number of external terminals.

The present invention is not limited to the circuit of the above-described embodiment, and the 1 / N frequency division output pulse has a pulse width of approximately ½.
Any means can be used as the means for delaying the signal and the sampling means for detecting the PLL lock as long as the operation described above is performed.

The present invention can be widely used as a PLL lock detection circuit in a PLL frequency synthesizer.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a PLL lock detection circuit proposed prior to the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

3 is an operation waveform diagram of FIG.

FIG. 4 is a block diagram showing another embodiment of the present invention.

5 is an operation waveform diagram of FIG.

FIG. 6 is a block diagram showing an embodiment when the present invention is applied to an FM / AM radio receiver.

[Explanation of symbols]

1 ... Phase detection circuit, 2 ... Program counter, 3-5 ...
D-type flip-flop circuit, 6 ... Loop filter, 7
f, 7a ... VCO, 8 ... D-type flip-flop circuit, 9
... prescaler, 10 ... counter circuit, 11 ... amplifier circuit, 12 ... divider circuit, 13 ... variable divider circuit, 14 ... divider ratio switching circuit, 15 ... control circuit, 16 ... latch circuit,
17 ... Switching circuit, 18f ... FM tuner circuit, 18
a ... AM tuner circuit, 19 ... switching circuit, 20 ... low frequency power amplifier circuit.

Claims (1)

[Claims] 1. A reference frequency signal and an output pulse divided by 1 / n
Phase detection circuit for detecting the phase difference between
Loop filter to which the output of
Local oscillator frequency whose frequency is controlled by the output of
A voltage-controlled oscillation circuit that forms a signal and the local oscillation frequency
Responding to changes in the wavenumber signal from one level to the other
Answer the above local oscillation frequency signal and count
1 / n frequency division output pulse
PLL lock detection circuit der connexion in the PLL frequency synthesizer comprising a counter circuit for forming the scan, the
From the other level of the local oscillation frequency signal to one level
Input the 1 / n frequency-divided output pulse in response to the change of
As a result, the phase is delayed with respect to the 1 / n frequency division output pulse.
First flip-flop circuit for forming an extended delayed signal
And a delay circuit including a reference frequency signal in a predetermined direction.
A second flit for taking in the delayed signal in response to a bell change
And a second flip-flop circuit, comprising:
A PLL lock detection circuit characterized in that the output of the circuit is used as a lock detection signal .