JPH0736524B2 - D / A converter - Google Patents
D / A converterInfo
- Publication number
- JPH0736524B2 JPH0736524B2 JP60059180A JP5918085A JPH0736524B2 JP H0736524 B2 JPH0736524 B2 JP H0736524B2 JP 60059180 A JP60059180 A JP 60059180A JP 5918085 A JP5918085 A JP 5918085A JP H0736524 B2 JPH0736524 B2 JP H0736524B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- reference voltage
- converter
- buffer amplifier
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、デジタル信号をアナログ信号に変換するD/
A変換器に係り、特に、片電源のバツフアアンプの上限
（電源電位）および下限（零電位）近傍において出力電
圧が非線形になつてしまう現象を回避するようにしたD/
A変換器に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a digital signal converter for converting a digital signal into an analog signal.
Related to the A converter, especially to avoid the phenomenon that the output voltage becomes non-linear near the upper limit (power supply potential) and lower limit (zero potential) of the buffer amplifier with one power supply.
A converter.
第４図は、電圧駆動梯子型Ｒ−2RD/A変換器の従来例を
示す回路図である（参考文献；猪瀬他：「デイジタル回
路」,P218,産業図書（昭和55））。この図において、１
は、抵抗値がR,2Rの抵抗を梯子状に接続してなる梯子部
である。この梯子部１のＮ個のスイッチ２−ｉ（ｉ＝0,
1,2…Ｎ−１）は、Ｎビツトのデジタル入力信号Siの
“1"/“0"に応じ、“1"のときには高い方の基準電圧
（高基準電圧）Vrefh側に、“0"のときには低い方の基
準電圧（低基準電圧）Vrefl側に接続されるようになつ
ている。そして、この梯子部１の出力電圧V0が電圧増幅
率１のバツフアアンプ３の入力端3aに供給され、その出
力端3bからアナログ信号として出力される。FIG. 4 is a circuit diagram showing a conventional example of a voltage-driven ladder type R-2RD / A converter (reference document: Inose et al .: "Digital Circuit", P218, Sangyo Tosho (Showa 55)). In this figure, 1
Is a ladder portion formed by connecting resistors having resistance values of R and 2R in a ladder shape. The N switches 2-i of the ladder unit 1 (i = 0,
1 ... When, the lower reference voltage (low reference voltage) is connected to the Vrefl side. The output voltage V 0 of the ladder unit 1 is supplied to the input terminal 3a of the buffer amplifier 3 having a voltage amplification factor of 1, and is output as an analog signal from the output terminal 3b.
この場合、第４図の矢印A0−A0,A1−A1,…Ai−Ai…から
下位ビツト側（図の下方）を見た抵抗値は常にＲである
から、デジタル入力信号Siのみが“1"のとき、出力側か
らみた梯子部１のテブナンの等価回路は第５図のように
なる。従つて、重ね合わせの理によつて一般の場合の出
力電圧V0は、 となる。すなわち、２進数SN-1SN-2…S0に比例した出力
が得られる。また、出力電圧V0の最大値V0max、最小値V
0minは、 V0min＝Vrefl ……（３） で与えられ、例えばVrefl＝0V,Vrefh＝10V,N＝10とする
と、V0max≒9.99V,V0min＝0Vとなる。In this case, since the resistance value seen from the lower bits (downward in the figure) from the arrows A0-A0, A1-A1, ... Ai-Ai in FIG. 4 is always R, only the digital input signal Si is "1". ", The Thevenin equivalent circuit of the ladder section 1 as seen from the output side is as shown in FIG. Therefore, the output voltage V 0 in the general case is Becomes That is, an output proportional to the binary number S N-1 S N-2 ... S 0 is obtained. Also, the maximum value V 0 max and the minimum value V 0 of the output voltage V 0
0 min is It is given by V 0 min = Vrefl (3). For example, if Vrefl = 0V, Vrefh = 10V, N = 10, then V 0 max ≈ 9.99V, V 0 min = 0V.
ところで、上記D/A変換器を片電源で構成し、その電源
電圧と高基準電圧Vrefhとを共通にしたような場合、バ
ツフアアンプ３は上限（電源電位）および下限（零電
位）近傍で非直線的となり、上述した最大出力電圧V0ma
x,最小出力電圧V0min付近の出力電圧V0が正しい値から
ずれてしまうという問題があつた。By the way, when the above-mentioned D / A converter is constituted by a single power supply and the power supply voltage and the high reference voltage Vrefh are made common, the buffer amplifier 3 is non-linear near the upper limit (power supply potential) and the lower limit (zero potential). The maximum output voltage V 0 ma
There was a problem that the output voltage V 0 near x and the minimum output voltage V 0 min deviated from the correct value.
この発明は、このような事情に鑑みてなされたもので、
片電源のバツフアアンプでも正しい応答ができるように
したD/A変換器を提供することを目的とする。The present invention has been made in view of such circumstances,
It is an object of the present invention to provide a D / A converter capable of giving a correct response even with a buffer amplifier having one power supply.
この発明は、高基準電圧および低基準電圧により駆動さ
れる抵抗梯子型Ｒ−2RD/A変換部を有し、該D/A変換部の
出力端をほぼ前記高基準電圧で駆動されるバッファアン
プに接続し、前記出力端に抵抗（Rm）を介してバイアス
電圧を印加することにより前記D/A変換部の出力端にお
ける電圧の振幅を制御可能とし、前記バイアス電圧を、
前記高基準電圧と前記低基準電圧との中間の電圧に設定
することにより、前記D/A変換部の出力端における電圧
の最小電圧を前記低基準電圧よりも大きくするととも
に、前記D/A変換部の出力端における電圧の最大電圧を
前記高基準電圧よりも小さくしたことを特徴とする。The present invention is a buffer amplifier having a resistance ladder type R-2RD / A conversion section driven by a high reference voltage and a low reference voltage, and an output terminal of the D / A conversion section being driven substantially by the high reference voltage. Connected to the output terminal, by applying a bias voltage to the output terminal via a resistor (Rm), it is possible to control the amplitude of the voltage at the output terminal of the D / A conversion unit, and the bias voltage is
By setting an intermediate voltage between the high reference voltage and the low reference voltage, the minimum voltage of the voltage at the output end of the D / A conversion unit is made larger than the low reference voltage, and the D / A conversion is performed. It is characterized in that the maximum voltage of the voltage at the output end of the section is made smaller than the high reference voltage.
上記構成によれば、バッファアンプへの入力電圧Vbの最
小値Vbminを低基準電圧Vreflよりも大きい値に、また、
最大値Vbmaxを高基準電圧Vrefhよりも小さい値に設定す
ることができる（第３図参照）。この結果、バツフアア
ンプが直線性を有している部分に入力電圧Vbを収めるこ
とが可能となり、常に正しい応答を得ることができる。According to the above configuration, the minimum value Vbmin of the input voltage Vb to the buffer amplifier is set to a value larger than the low reference voltage Vrefl,
The maximum value Vbmax can be set to a value smaller than the high reference voltage Vrefh (see FIG. 3). As a result, the input voltage Vb can be accommodated in the portion where the buffer amplifier has linearity, and a correct response can always be obtained.
以下、図面を参照して本発明の実施例を説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）は、本発明の一実施例によるD/A変換器の
構成を示す回路図である。このD/A変換器が第４図に示
す従来のD/A変換器と異なる点は、バツフアアンプ３の
入力端3aに、抵抗４（抵抗値Rm）を介して、 なるバイアス電圧が印加されている点である。FIG. 1A is a circuit diagram showing a configuration of a D / A converter according to an embodiment of the present invention. This D / A converter differs from the conventional D / A converter shown in FIG. 4 in that the input terminal 3a of the buffer amplifier 3 is connected via a resistor 4 (resistance value Rm). That is, the bias voltage is applied.
このような構成によれば、バツフアアンプ３の入力端3a
に供給される入力電圧Vbは次のようになる。まず、梯子
部１の出力抵抗はすでに述べたようにＲであり（第５図
参照）、その出力電圧はV0であるから、梯子部１と抵抗
４とを含めた等価回路は第２図のようになる。この図よ
り、入力電圧Vbは、 となる。この式に、 V0max≒Vrefh（（２）式より）、 と（３），（４）式を代入すれば、入力電圧Vbの最大値
Vbmaxと最小値Vbminとは次のようになる。According to such a configuration, the input terminal 3a of the buffer amplifier 3
The input voltage Vb supplied to is as follows. First, the output resistance of the ladder section 1 is R as described above (see FIG. 5), and its output voltage is V 0. Therefore, the equivalent circuit including the ladder section 1 and the resistor 4 is shown in FIG. become that way. From this figure, the input voltage Vb is Becomes By substituting V 0 max ≈ Vrefh (from equation (2)) and equations (3) and (4) into this equation, the maximum value of input voltage Vb
Vbmax and the minimum value Vbmin are as follows.
これを図示したものが第３図であり、入力電圧Vbは低基
準電圧Vreflから一定電圧高く、高基準電圧Vrefhから前
記一定電圧低い範囲で変動する。例えば、高基準電圧Vr
efhを10V、低基準電圧Vreflを0V、抵抗値Rm＝Ｒとする
と、 Vbmin＝2.5V となり、入力電圧Vbは、2.5V〜7.5Vの範囲で変動するこ
とになる。 This is shown in FIG. 3, in which the input voltage Vb varies from the low reference voltage Vrefl by a constant voltage and varies from the high reference voltage Vrefh by the constant voltage. For example, high reference voltage Vr
If efh is 10V, low reference voltage Vrefl is 0V, and resistance value Rm = R, Vbmin = 2.5V, and the input voltage Vb will fluctuate within the range of 2.5V to 7.5V.
こうして、バツフアアンプ３の入力電圧Vbをバツフアア
ンプ３の線形部分に収めることができるから、バッファ
アンプの線形範囲がVrefh〜Vreflよりせまい場合でも正
しい応答が可能となる。In this way, the input voltage Vb of the buffer amplifier 3 can be accommodated in the linear portion of the buffer amplifier 3, so that a correct response is possible even when the linear range of the buffer amplifier is narrower than Vrefh to Vrefl.
なお、バイアスの印加方法は第１図（ｂ）に示すよう
に、抵抗値Rm/2の抵抗５と抵抗値Rmの抵抗6,6とをＴ字
状に接続し、上記抵抗6,6の各端に基準電圧VreflとVref
hを印加し、抵抗５の一端をバツフアアンプ３の入力端3
aに接続するようにしても、上と同様の作用、効果を奏
することができる。As shown in FIG. 1 (b), the method of applying the bias is such that the resistor 5 having the resistance value Rm / 2 and the resistors 6 and 6 having the resistance value Rm are connected in a T-shape, and Reference voltage Vrefl and Vref at each end
h is applied and one end of the resistor 5 is connected to the input end 3 of the buffer amplifier 3.
Even if it is connected to a, the same operation and effect as above can be obtained.
以上説明したように、この発明によれば、バツフアアン
プへの入力電圧がバツフアアンプの線形部から逸脱する
ことなく、常に正しい応答を得ることができる。As described above, according to the present invention, a correct response can always be obtained without the input voltage to the buffer amplifier deviating from the linear portion of the buffer amplifier.
第１図（ａ）は本発明の一実施例によるD/A変換器の構
成を示す回路図、同図（ｂ）はバイアス回路の変形例を
示す図、第２図は同実施例における入力電圧Vbを計算す
るための等価回路を示す図、第３図は上記入力電圧Vbの
変動範囲を示すグラフ、第４図は従来のD/A変換器の一
構成例を示す回路図、第５図は第４図のAN-1−AN-1線か
らみたテブナンの等価回路を示す図である。 １……梯子部、３……バツフアアンプ、４……抵抗。1 (a) is a circuit diagram showing a configuration of a D / A converter according to an embodiment of the present invention, FIG. 1 (b) is a diagram showing a modified example of a bias circuit, and FIG. 2 is an input in the embodiment. FIG. 3 is a diagram showing an equivalent circuit for calculating the voltage Vb, FIG. 3 is a graph showing a variation range of the input voltage Vb, FIG. 4 is a circuit diagram showing a configuration example of a conventional D / A converter, and FIG. The figure shows an equivalent circuit of Thevenin as seen from the line A N-1 -A N-1 in FIG. 1 ... Ladder part, 3 ... Buffer amplifier, 4 ... Resistor.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 石田 勝彦 静岡県浜松市中沢町10番１号 日本楽器製 造株式会社内 (56)参考文献 特開 昭52−51853（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Katsuhiko Ishida 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka Nihon Gakki Co., Ltd. (56) Reference JP-A-52-51853 (JP, A)
Claims (1)
れる抵抗梯子型Ｒ−2RD/A変換部を有し、 該D/A変換部の出力端をほぼ前記高基準電圧で駆動され
るバッファアンプに接続し、前記出力端に抵抗（Rm）を
介してバイアス電圧を印加することにより前記D/A変換
部の出力端における電圧の振幅を制御可能とし、 前記バイアス電圧を、前記高基準電圧と前記低基準電圧
との中間の電圧に設定することにより、前記D/A変換部
の出力端における電圧の最小電圧を前記低基準電圧より
も大きくするとともに、前記D/A変換部の出力端におけ
る電圧の最大電圧を前記高基準電圧よりも小さくした ことを特徴とするD/A変換器。1. A buffer having a resistance ladder type R-2RD / A conversion section driven by a high reference voltage and a low reference voltage, and an output terminal of the D / A conversion section being driven substantially by the high reference voltage. It is possible to control the amplitude of the voltage at the output end of the D / A conversion unit by connecting to the amplifier and applying a bias voltage to the output end via a resistor (Rm). By setting an intermediate voltage between the low reference voltage and the low reference voltage, the minimum voltage of the voltage at the output end of the D / A conversion unit is made larger than the low reference voltage, and the output end of the D / A conversion unit. The D / A converter is characterized in that the maximum voltage of the above voltage is lower than the high reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60059180A JPH0736524B2 (en) | 1985-03-23 | 1985-03-23 | D / A converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60059180A JPH0736524B2 (en) | 1985-03-23 | 1985-03-23 | D / A converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61218229A JPS61218229A (en) | 1986-09-27 |
| JPH0736524B2 true JPH0736524B2 (en) | 1995-04-19 |
Family
ID=13105944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60059180A Expired - Lifetime JPH0736524B2 (en) | 1985-03-23 | 1985-03-23 | D / A converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0736524B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6374791A (en) * | 1986-09-18 | 1988-04-05 | ブリヂストンサイクル株式会社 | Variable speed gear for bicycle |
| US4990916A (en) * | 1990-01-30 | 1991-02-05 | Analog Devices, Bv | Single-supply digital-to-analog converter for control function generation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5928091B2 (en) * | 1975-10-23 | 1984-07-10 | 松下電器産業株式会社 | Digital-analog conversion process |
-
1985
- 1985-03-23 JP JP60059180A patent/JPH0736524B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61218229A (en) | 1986-09-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2001511516A (en) | Output circuit for pressure sensor | |
| KR20000010720A (en) | Digital to analogue converter with multiple output stages | |
| JPH0652872B2 (en) | Digital-to-analog converter | |
| US5034699A (en) | Trimming of operational amplifier gain | |
| EP0716308A3 (en) | Calibration circuit for capacitive sensors | |
| US6639539B1 (en) | System and method for extending the dynamic range of an analog-to-digital converter | |
| US4631522A (en) | Method and circuit for compensation of a multiplying digital-to-analog converter | |
| JPH0736524B2 (en) | D / A converter | |
| US5204679A (en) | Differential analog-digital converter | |
| US4868909A (en) | Signal shaping circuit utilizing a magneto-resistor in a voltage divider circuit | |
| US6392578B1 (en) | Digital-to-analog converter and a method for facilitating outputting of an analog output of predetermined value from the digital-to-analog converter in response to a digital input code | |
| US20040246157A1 (en) | Analog input for an electronic circuit | |
| US12375096B2 (en) | Digital-to-analog converter and corresponding digital-to-analog conversion method | |
| JPH0547006B2 (en) | ||
| JP2576222B2 (en) | Digital-to-analog converter | |
| JP3961353B2 (en) | Input device | |
| JPS6256467B2 (en) | ||
| JP3772938B2 (en) | Gain control circuit | |
| JP2626352B2 (en) | A / D converter | |
| JPH031709A (en) | Variable resistance circuit and variable gain amplifier | |
| KR930007592Y1 (en) | DA converter | |
| JPS5934190Y2 (en) | D↓-A converter | |
| JPS6321125B2 (en) | ||
| EP0160557A2 (en) | A folding-type analog-to-digital converter | |
| US3962651A (en) | Analog A-C storage circuit employing a high gain amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |