JPH073666B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A microcomputer having a function of executing a bit operation instruction, and a bit operation instruction for a register including a bit in which read data is status data and write data is control data Read data is status data and write data is control data, and the contents of the register in response to a bit operation instruction. And an MPU which reads the specified bit and then writes it to the register, and generates a signal for distinguishing the bit operation instruction from other instructions from the instruction code of the bit operation. Using only the status control bit A means for holding the contents of the status control bit at that time when writing to the register after the bit operation is additionally provided.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a function of executing a bit operation instruction with respect to a register including a bit in which read data is status data and write data is control data.

[Prior Art] In this type of microcomputer, in response to a bit manipulation instruction, the MPU reads the contents of all bits of the register in the first step, manipulates the predetermined bit in the second step, and In step, the contents of all the bits are written in the register.

[Problems to be solved by the invention] However, if the contents of the status bit are rewritten by the peripheral I / O irrespective of the MPU between reading and writing, this status bit is written in the third step. The original data is rewritten by the operation.

Therefore, if a bit operation instruction is executed for such a register, the subsequent control for the peripheral I / O may not be performed properly, and it is substantially impossible to use the bit operation instruction for the register.

In view of the above problems, an object of the present invention is to provide a microcomputer capable of using a bit operation instruction even for a register including a bit in which read data is status data and write data is control data. Especially.

[Means for Solving the Problems] In order to achieve this object, according to the present invention, read data is status data and write data is a register having a status control bit, which is control data. In response, in a microcomputer having an MPU for reading the contents of the register and operating a predetermined bit of the MPU and writing the MPU to the register, a signal for distinguishing the bit operation instruction from other instructions A means for holding the contents of the status control bit at that point in time when writing to the register after the bit operation is performed by using the signal and generating from the instruction code. is doing.

[Operation] According to the present invention, even if the contents of the status control bits are rewritten by peripheral I / O (including other MPUs) regardless of the MPU between the reading and the writing, the status control bits are With regard to only, since the contents of the status control bit at that time are retained when writing to the register after bit manipulation, it is possible to appropriately change the contents by a bit manipulation instruction for such a register, Therefore, the bit manipulation instruction can be used for such a register.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a main configuration of a microcomputer.

The MPU 10 supplies an address signal and a read / write signal R / W to the address decoder 12, and the address decoder 12 selects the components of the timer / counter 14 from these signals and the components of the timer / counter 14 will be described later. Read signals RD ₁ and RD ₂ and write signals WR ₁ and WR ₂ are generated and supplied to the timer / counter 14. The MPU10 supplies the reset signal RESET to the timer / counter 14 to
The counter 14 is initialized, and the timer /
Read modifier write signal that indicates that the operation mode of counter 14 is set and that bit manipulation instructions are being executed
Supply RMW to timer / counter 14 to supply timer / counter 1
Enables the execution of bit manipulation instructions for 4.

The timer / counter 14 operates based on the clock pulse φ supplied from the clock generator 16, and supplies an interrupt request signal to the MPU 10 when the timer / counter 14 times out in the timer mode. The MPU 10 performs interrupt processing based on this interrupt request.

FIG. 2 shows the detailed structure of the timer / counter 14 shown in FIG. The clock pulse φ output from the clock generator 16 is supplied to the frequency dividing circuit 18 to be frequency-divided, and the clock pulse having a different cycle output from each frequency dividing stage of the frequency dividing circuit 18 is supplied to the selector 20. The selector 20 selects a clock pulse having a cycle designated by the contents of the 4th to 7th bits of the status control register 22 and performs an AND gate.
Supply to one input terminal of 24. The status control register 22 is connected to the other input terminal of the AND gate 24.
The content of the 0th bit is supplied. When this bit is "1", the clock pulse from the selector 20 is supplied to the CK terminal of the counter 26 through the AND gate 24 and counted. Here, the initial value of the counter 26 is set in the data register 28 from the MPU 10 via the data bus DB. At this time, the data register 28 has an address decoder 12
The write signal WR ₂ is supplied from. The counter 26 is initialized by loading the contents of the data register 28 by a control signal from the reload control circuit 30. counter
When the count value of 26 becomes large and the overflow (OVF) bit becomes "1" (H level), the second bit of the status control register 22 is set.

In the status control register 22, only the second bit is the status control bit, that is, the read data is the status data and the write data is the control data, and the other 7 bits are the control bits. .

When the third bit of the status control register 22 is "1", that is, in the timer mode, the reload control circuit is set by setting the second bit.
30 loads the contents of data register 28 into counter 26. At this time, the address decoder 12 to the data register 28
Is supplied with the read signal RD ₂ . The overflow pulse output from the counter 26 is the D flip-flop 32.
Is also supplied to the CK pin of the
The output of the D flip-flop 32 is inverted every time it is output from 26. The output of the first bit and the second bit of the status control register 22 is supplied to the AND gate 34. When the first bit is "1", the status control is performed by the overflow pulse from the counter 26. When the second bit of the register 22 becomes "1", an interrupt request signal is output from the AND gate 34 and supplied to the MPU 10.

Here, for example, when the first bit of the status control register 22 is "1", in order to mask the interrupt by setting only this first bit to "0", execute the bit reset instruction provided in the MPU10. To do. Execution of this instruction is divided into three cycles. In the first cycle (read cycle), the MPU 10 loads the contents of all bits of the status control register 22 into the internal register via the data bus DB, and in the second cycle (bit operation cycle) the first bit of this internal register. Is set to "0", and the contents of this internal register are stored in the status control register 22 via the data bus DB in the third cycle (write cycle).

FIG. 3 shows these three cycles. A is the address of the status control register 22, TD is the contents of this status control register 22 before bit manipulation, and PC is the first bit of the internal register "0". The value of the program counter indicating the address in the main memory where the bit manipulation instruction is written, PD is the code of this bit manipulation instruction, and TD 'is the content of the status control register 22 after bit manipulation.

After the MPU10 reads the contents of the status control register 22 into the internal register and before writing the contents of the internal register into the status control register 22, the counter 26 outputs an overflow pulse and the status control register 22 When 2 bits are changed from "0" to "1", MPU1 is written in the write cycle.
Writing the contents of the internal register of 0 to the status control register 22 causes a disadvantage that the second bit of the status control register 22 is rewritten to the original value "0".

Therefore, in this embodiment, the second bit of the status control register 22 is constructed as shown in the third.

That is, the output of the second bit is the flip-flop 36.
, Q output, and flip-flop 36 is preset by an overflow pulse. Q of flip-flop 36
Output, read signal RD ₁ from address decoder 12 and MPU
The RMW (read modify write) signal from 10 is supplied to the gate of the NMOS transistor 40 via the NOR gate 38. The source of the NMOS transistor 40 is grounded, and the drain is connected to the data bus line DB ₂ of the second bit of the data bus DB. This data bus line DB ₂
The upper signal is supplied to one input terminal of the OR gate 42, and the write signal WR ₁ from the address decoder 12 is supplied to the other input terminal of the OR gate 42. OR gate 4
The output of 2 is supplied to one input terminal of the NAND gate 44, and the reset signal RESET from the MPU 10 is supplied to the other input terminal of the NAND gate 44. The output of the NAND gate 44 is supplied to the clear terminal of the flip-flop 36.

When the reset signal RESET goes low, the NAND gate 4
The output of 4 becomes H level, and the Q output of the flip-flop 36 is reset to L level.

Next, the operation of the circuit configuration shown in FIG. 3 will be described with reference to FIG. FIG. 4 is a timing chart when the bit operation instruction is executed.

(1) Read cycle Since the read modifier write signal RMW is at the L level when it is not a bit operation instruction, when the read signal RD ₁ goes to the L level, the output of the NOR gate 38 is the inverted level of the Q output of the flip-flop 36. Becomes Therefore, when the Q output is at the H level, the NMOS transistor 40 is turned off, and the charges precharged on the data bus line DB ₂ are not discharged even when the read signal RD ₁ goes to the L level, and the MPU 10
Determines that the Q output is at the H level. Further, when the Q output is at the L level, the NMOS transistor 40 is turned on, the charge precharged to the data bus line DB ₂ is discharged when the read signal RD ₁ becomes the L level, and the MPU 10 outputs the Q output at the L level. Judge that there is.

On the other hand, in the case of the bit operation instruction, as shown in FIG. 4, the read modifier write signal RMW becomes H level, so the Q output of the flip-flop 36 and the read signal.
The output of the NOR gate 38 becomes L level regardless of the level of RD ₁ , and the NMOS transistor 40 is turned off. Therefore,
The charge precharged to the data bus line DB ₂ is not discharged even when the read signal RD ₁ goes to L level, and the MPU 10 has Q
It is formally determined that the output is at the H level.

The write signal WR ₁ is at the H level, and therefore the CLR terminal of the flip-flop 36 remains at the L level and is not cleared.

(2) Bit operation cycle MPU10 reads the data T read in the internal register in the previous cycle.
Only the value of the first bit of D is set to "0" to make the data TD '.
At this time, the write signal WR ₁ is at H level, and the flip-flop 36 is not cleared.

(3) Write cycle MPU10 outputs the contents TD 'of the internal register to the data bus DB. Therefore, the data bus line DB ₂ is precharged. On the other hand, since the read signal RD ₁ is at the H level as in the write cycle in the case of not a bit operation instruction, the NMOS transistor 40 is off and is not discharged. Therefore, even if the write signal WR ₁ becomes L level, the output of the NAND gate 44 remains L level and the flip-flop 36 is not cleared.

Therefore, while the MPU10 reads the contents of the status control register 22 into the internal register and then manipulates the bits and writes the contents of this internal register to the status control register 22, an overflow pulse is output from the counter 26 to indicate the status. Even if the second bit of the control register 22 is changed from "0" to "1", the second bit of the status control register 22 is never rewritten to the original value "0" in the write cycle.

[Effects of the Invention] As described above, according to the microcomputer of the present invention, the contents of the status control bits of the register are MPU between the reading and the writing.
Even if it is rewritten by peripheral I / O, etc. regardless of the above, since only the status control bit retains the contents of the status control bit at the time of writing to the register after bit manipulation. The contents of a register can be appropriately changed by a bit operation instruction, and therefore, the excellent effect that the bit operation instruction can be used even for such a register is exerted, and the efficiency of software development is improved. There is a big contribution.

[Brief description of drawings]

1 to 4 relate to an embodiment of the present invention, FIG. 1 is a block diagram of a main part of a microcomputer, and FIG. 2 is a block diagram showing in detail the configuration of the timer / counter 14 of FIG. FIG. 3 shows the status control register 22 of FIG.
FIG. 4 is a circuit diagram showing in detail the configuration of the second bit of FIG. 4, and FIG. 4 is a timing chart at the time of executing a bit operation instruction. In the figure, 10 is the MPU 12, the address decoder 14 is the timer / counter 16, the clock generator 18 is the divider circuit 20, the selector 22 is the status control register 24, 34 is the AND gate 26, the counter 28 is the data register 30, and the data register 30 is reloaded. Control circuits 32 and 36 are flip-flops 38 are NOR gates 40 are NMOS transistors 42 are OR gates 44 are NAND gates

Claims (1)

[Claims] 1. A register (22) having a status control bit, wherein read data is status data and write data is control data, and the contents of the register are read in response to a bit operation command. Write to the register after manipulating the bit
In a microcomputer having an MPU (10), a signal (RM for distinguishing the bit operation instruction from other instructions
W) is generated from the instruction code of the bit operation, and by using the signal, when only the status control bit is written into the register after the bit operation, the contents of the status control bit at that time are retained. A microcomputer having means (38, 40) attached thereto.