JPH073825B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same, and more particularly to a connection structure between an impurity diffusion layer region of a MOS transistor and a conductor layer, and The present invention relates to a method of forming this connection with a gate of a MOS transistor in a self-aligned structure.

(Prior Art) As a technique for forming a connection between an impurity diffusion layer region of a transistor and a conductor layer in a semiconductor integrated circuit by a self-aligned structure with the gate of the transistor, for example, a preprint of the 35th Joint Lecture on Applied Physics Second Volume, P611, Lecture
The method shown in No. 28p-V-14 will be described with reference to FIGS. 3 (a) to 3 (d).

That is, after the gate oxide film 42, the first polycrystalline silicon film 43, and the first insulating film 44 are sequentially stacked on the semiconductor substrate 41 to form a gate portion having a two-layer structure, the above-mentioned structure is formed on the surface of the semiconductor substrate 41. Impurity diffusion layer regions 451 and 452 serving as the source and drain of the MOS transistor are formed on both sides of the channel region below the gate portion.
And then forming a second insulating film on the side surface of the gate portion.
Form 46. After that, a thermal oxide film 47 / nitride film 48 / second polycrystalline silicon film 49 / BPSG film (silicate glass film containing boron / phosphorus impurities) 50 is sequentially formed on the entire surface of the semiconductor substrate 41 from the lower layer side to the upper layer side. After stacking to form a multilayer film, a resist 51 is provided on the entire surface, and this is patterned by a contact hole mask having a size that covers the gate portion. Using this resist 51 as a mask, a part of the BPSG film 50 is removed. To form a contact hole. At this time, BP
Due to the difference in etching rate between the SG film 50 and the second polycrystalline silicon film 49, the second polycrystalline silicon film 49 is not removed but is exposed.

Next, the exposed second polycrystalline silicon film 49 is removed, and then the remaining BPSG film 50 is reflowed in a steam atmosphere to be planarized, and at the same time, the second polycrystalline film under the BPSG film 50 is removed. The silicon film 49 is oxidized to form a polycrystalline silicon oxide film 49 '. Finally, the exposed nitride film 48 / thermal oxide film 47 is removed, and a polycide wiring 52 is formed so as to contact one of the impurity diffusion layer regions 451 through the contact hole.

However, in the above method, the nitride film 48 remains under the BPSG film 50 even after the contact between the polycide wiring 51 and the impurity diffusion layer region 451 is made, and the expansion coefficient of the nitride film 48 and the oxide films 47 and 49 ′ is increased. Therefore, there is a problem that stress is generated in the subsequent thermal process and the transistor characteristics are deteriorated.

(Problems to be Solved by the Invention) In the present invention, when the connection between the impurity diffusion layer region of the transistor and the conductor layer is formed by the transistor gate and the self-aligned structure by the conventional method for manufacturing a semiconductor integrated circuit described above, The nitride film remains even after the connection between the conductor layer and the impurity diffusion layer region is made, and the difference in expansion coefficient between the nitride film and the oxide film causes stress in the subsequent thermal process, which deteriorates the transistor characteristics. The semiconductor integrated circuit and the semiconductor integrated circuit in which the gate and the impurity diffusion layer region of the MOS transistor are connected to the conductor by a self-aligned structure without deteriorating the transistor characteristics. It is intended to provide a manufacturing method.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor integrated circuit according to claim 1 is a gate oxide film formed on a semiconductor substrate of the first conductivity type, and a MOS formed on the gate oxide film. A first conductor serving as a gate of a transistor, a first insulating film formed on the first conductor, and the first conductor formed in the semiconductor substrate and serving as a source / drain of the MOS transistor. An impurity diffusion layer region of a second conductivity type opposite to the conductivity type, a second insulating film formed on a side surface of the first conductor, the semiconductor substrate and the first
Through a third insulating film formed on the second insulating film and the third insulating film, and a contact hole having a size over the first insulating film formed in the third insulating film. A second conductor formed so as to be in contact with the impurity diffusion region, the third insulating film is a composite film including a film having oxidation resistance, and The oxidation resistant film is formed so as not to exist on a part of the impurity diffusion layer region other than the contact hole portion.

The method for manufacturing a semiconductor integrated circuit according to claim 3, wherein a step of sequentially forming a gate oxide film, a first conductor to be a gate of a MOS transistor, and a first insulating film on a first conductivity type semiconductor substrate. And a step of forming an impurity diffusion layer region of a second conductivity type opposite to the first conductivity type, which serves as a source / drain of the MOS transistor in the semiconductor substrate, and a first side surface of the first conductor. Forming an insulating film of No. 2; forming a first oxide film on the semiconductor substrate;
Forming a silicon nitride film on the first oxide film on the impurity diffusion layer region on one side of the impurity diffusion layer regions serving as the source / drain of the MOS transistor; and polycrystal silicon on the entire surface of the semiconductor substrate. A step of forming a film,
Forming a silicate glass film containing impurities on the polycrystalline silicon film; forming a contact hole having a size over the first insulating film in the silicate glass on the silicon nitride film; While reflowing and flattening the rest of the silicate glass film in a steam atmosphere, a step of oxidizing all of the polycrystalline silicon film to form a polycrystalline silicon oxide film, and exposing other than the lower part of the silicate glass film. Removing the polycrystalline silicon oxide film in the contact hole, the silicon nitride film and the first oxide film thereunder, and forming a second conductor on the silicate glass film and in the contact hole. And a forming step.

The method of manufacturing a semiconductor integrated circuit according to claim 4, wherein a gate oxide film, a first conductor to be a gate of a MOS transistor, and a first insulating film are sequentially laminated on a first conductivity type semiconductor substrate. And a step of forming an impurity diffusion layer region of a second conductivity type opposite to the first conductivity type, which serves as a source / drain of the MOS transistor in the semiconductor substrate, and a first side surface of the first conductor. Forming an insulating film of No. 2; forming a first oxide film on the semiconductor substrate;
Forming a silicon nitride film on the first oxide film on the impurity diffusion layer region on one side of the impurity diffusion layer regions serving as the source / drain of the MOS transistor; and polycrystal silicon on the entire surface of the semiconductor substrate. A step of forming a film,
Forming a silicate glass film containing impurities on the polycrystalline silicon film; forming a contact hole having a size over the first insulating film in the silicate glass on the silicon nitride film; A step of removing the polycrystalline silicon film in the exposed contact hole other than the lower portion of the silicate glass film, and reflowing the remaining part of the silicate glass film in a steam atmosphere to planarize the polycrystalline silicon film; A step of oxidizing all of the silicon film into a polycrystalline silicon oxide film; and a step of exposing the silicon nitride film in the exposed contact hole other than the lower part of the silicate glass film and the first oxide film thereunder. And a step of forming a second conductor on the silicate glass film and in the contact hole. And wherein the door.

(Operation) According to the configuration as described in claim 1, the oxidation resistant film for preventing the oxidation of the substrate is configured not to exist on the impurity diffusion layer region other than the contact hole portion. Therefore, no stress is generated in the thermal process after the connection between the second conductor and the impurity diffusion layer region, and there is no possibility of causing deterioration of transistor characteristics.

According to the manufacturing method of claims 3 and 4, since the oxidation resistant film does not remain on the impurity diffusion layer region other than the contact hole portion, the connection between the second conductor and the impurity diffusion layer region is made. No stress is generated in the thermal process after the removal, and there is no possibility of causing deterioration of transistor characteristics. Moreover, the impurity diffusion layer region of the transistor and the second conductor can be connected to the gate of the transistor by a self-aligned structure.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1 (a) to 1 (d) show a manufacturing process of a semiconductor integrated circuit at a stage before reaching the present invention. That is, first, the first
As shown in FIG. 3A, after the gate oxide film 3 having a thickness of about 150 to 200 Å is formed on the first conductivity type semiconductor substrate 1, the first polycrystalline silicon film having a thickness of about 2000 to 4000 Å is formed. Four
On the polycrystalline silicon film 4 to a thickness of 2000-4000
A first insulating film 5 having a thickness of about Å, for example, a SiO ₂ film (CVD oxide film) 5 formed by a CVD (Chemical Vapor Deposition) method is deposited, and the first insulating film 5 and the first polycrystalline silicon film 4 are deposited. Are patterned to form a gate portion of a MOS (insulated gate type) transistor.

Next, on the surface of the semiconductor substrate 1, on both sides of the channel region below the gate portion, second-conductivity-type impurity diffusion layer regions 21 and 22 serving as the source / drain of the MOS transistor are formed.
To form. Next, on the side surface of the gate portion, for example, SiN
A second insulating film 6 made of a film (silicon nitride film) is formed.

Next, as shown in FIG. 1B, a first oxide film 7 / a second polycrystalline silicon film 8 / a silicate glass film containing impurities (for example, a BPSG film 9) are sequentially laminated on the semiconductor substrate 1. To do.
That is, first, a first oxide film (for example, a thermal oxide film) 7 having a thickness of about 200 Å is formed on the semiconductor substrate 1, and a second polycrystalline silicon film 8 having a thickness of about 300 to 500 Å is formed on the first oxide film 7. Is deposited, and a BPSG film 9 having a thickness of about 4000 to 6000Å is formed on the polycrystalline silicon film 8.

Next, a resist 10 is provided on the semiconductor substrate 1, and as shown in FIG. 1C, the resist 10 is patterned by a mask having a contact hole pattern of such a size as to cover the gate portion. As a mask
A part of the BPSG film 9 is removed by etching to form a contact hole.

Next, after removing the resist 10, by oxidizing in a steam atmosphere at a temperature of 900 ° C. for 20 to 60 minutes, the rest of the BPSG film 9 is reflowed and flattened as shown in FIG. 1 (d). At the same time, the second polycrystalline silicon film 8 is entirely oxidized to form a polycrystalline silicon oxide film 11. Next, by RIE (Reactive Ion Etching) method, the polycrystalline silicon oxide film 11 in the exposed contact holes other than the lower part of the BPSG film 9 and the thermal oxide film 7 thereunder are removed to remove the semiconductor substrate. Thickness on the entire surface (including the contact hole) on 1
After forming a conductor layer 12 made of polycide of about 4000 Å and making contact with one of the impurity diffusion layer regions 21, the conductor layer 12 is patterned to form wiring. After that, a desired semiconductor integrated circuit is realized according to a normal semiconductor integrated circuit manufacturing process.

The second insulating film 6 may be, for example, a CVD oxide film other than the SiN film. Further, the conductor layer 12 may be, for example, polycrystalline silicon or silicide other than polycide.

The semiconductor integrated circuit manufactured as described above has a three-layer structure in which the thermal oxide film 7 / polycrystalline silicon oxide film 11 / BPSG film 9 is sequentially laminated on the semiconductor substrate 1 from the lower layer side to the upper layer side. A multilayer film is formed, a nitride film is not included under the BPSG film 9, and an oxidation resistant film does not exist on a part of the impurity diffusion layer region 22 other than the contact hole portion. Since it is configured, no stress is generated in the thermal process after the conductor layer 12 and the impurity diffusion layer region 21 are connected, and there is no possibility of causing deterioration of transistor characteristics. Moreover, the connection between the impurity diffusion layer region 21 of the transistor and the conductor layer 12 is formed in a self-aligned structure with the gate portion of the transistor.

Further, according to the method for manufacturing a semiconductor integrated circuit as described above, after forming the second insulating film 6 on the side surface of the gate portion of the MOS transistor, the multilayer film having the three-layer structure not including the nitride film is formed. , A contact hole is formed by a contact hole mask of such a size on the gate portion, and the conductor layer 12 is formed so as to come into contact with the impurity diffusion layer region 21 through the contact hole. The semiconductor integrated circuit having the semiconductor integrated circuit can be easily formed.

Further, in the method of manufacturing a semiconductor integrated circuit as described above, if the second insulating film 6 has oxidation resistance, the polycrystalline silicon film 4 of the gate of the transistor will be formed when the second polycrystalline silicon is oxidized. It is not oxidized and the transistor characteristics are not changed.

Next, an embodiment of the method for manufacturing a semiconductor integrated circuit of the present invention will be described with reference to FIGS. 2 (a) to 2 (c). That is,
First, as shown in FIG. 2A, on the semiconductor substrate 1,
After forming the gate oxide film 3 having a thickness of about 150 to 200Å, the first polycrystalline silicon film 4 having a thickness of about 2000 to 4000Å is deposited, and the first polycrystalline silicon film 4 having a thickness of about 2000 to 4000Å is deposited on the polycrystalline silicon film 4. A first insulating film 5 made of a CVD oxide film is deposited, and two layers of the first insulating film 5 and the first polycrystalline silicon film 4 are patterned to form a gate portion of a MOS transistor.

Next, on the surface of the semiconductor substrate 1, on both sides of the channel region below the gate portion, impurity diffusion layer regions 21 and 22 serving as the source / drain of the MOS transistor are formed.
Next, the second insulating film 6 made of, for example, a SiN film is formed on the side surface of the gate portion. Next, the first oxide film 7 having a thickness of, for example, about 200 Å is formed on the semiconductor substrate 1, and the SiN film 13 having a thickness of about 250 Å is formed thereon. Next, a resist pattern 14 is provided on the semiconductor substrate 1 so that the SiN film 13 remains at least on the contact portion, and a part of the SiN film 13 is peeled off using the resist pattern 14 as a mask.

Next, after removing the resist pattern 14, FIG. 2 (b)
As shown in FIG.
A second polycrystalline silicon film 8 having a thickness of 0 to 500Å is deposited, and a BPSG film 9 having a thickness of 4000 to 6000Å is formed thereon. Next, a resist 10 is provided on the semiconductor substrate 1, and the resist 10 is patterned with a mask having a contact hole pattern of such a size as to cover the gate portion. Using this resist 10 as a mask, a part of the BPSG film 9 is removed by etching. To form a contact hole.

Next, after removing the resist 10, by oxidizing in a steam atmosphere at a temperature of 900 ° C. for 20 to 60 minutes, the rest of the BPSG film 9 is reflowed and flattened as shown in FIG. 2 (c). At the same time, the second polycrystalline silicon film 8 is entirely oxidized to form a polycrystalline silicon oxide film 11. Next, the RIE method is used to expose the polycrystalline silicon oxide film 11 in the exposed contact holes other than the lower part of the BPSG film 9 and the SiN film 13 thereunder.
And the oxide film 7 are removed, and a conductor layer 12 made of polycide having a thickness of, for example, about 4000 Å is formed on the entire surface of the semiconductor substrate 1 (including the inside of the contact hole). After making contact with, the conductor layer 12 is patterned to form wiring. After that, a desired semiconductor integrated circuit is realized according to a normal semiconductor integrated circuit manufacturing process.

The second insulating film 6 may be, for example, a CVD oxide film other than the SiN film 13. Further, as the conductor layer 12,
Other than polycide, for example, polycrystalline silicon or silicide may be used.

Also in the semiconductor integrated circuit manufactured according to the above-described embodiment, the thermal oxide film is formed on the semiconductor substrate 1 from the lower layer side to the upper layer side similarly to the semiconductor integrated circuit shown in FIGS. 1 (a) to 1 (d).
7 / polycrystalline silicon oxide film 11 / BPSG film 9 are sequentially laminated to form a multi-layered film having a three-layer structure, and oxidation resistance is provided on a part of the impurity diffusion layer region 22 other than the contact hole portion. Since it is configured such that the film that it has does not exist, stress does not occur in the thermal process after the connection between the conductor layer 12 and the impurity diffusion layer region 21, and there is no risk of deterioration of transistor characteristics. Disappear.

In the above-described embodiment, the second polycrystalline silicon film 8 is entirely oxidized in the water vapor atmosphere to form the polycrystalline silicon oxide film 11, and then the exposed polycrystalline silicon oxide film 11 in the contact hole is removed. SiN film 13 and oxide film 7 underneath
And were removed by the RIE method. However, at this time, the CVD oxide film 5 in the gate portion under the SiN film 13 is also etched. Since the etching variation with respect to the oxide film 7 under the SiN film 13 by the RIE method is about several percent, if the CVD oxide film 5 in the gate portion is excessively etched, this C
There is a possibility that the first polycrystalline silicon film 4 under the VD oxide film 5 and the conductor layer 12 formed in a later step may be short-circuited.
In order to avoid this, a part of the above embodiment may be modified as follows.

That is, the second polycrystalline silicon film 8 is formed in the water vapor atmosphere.
Before oxidization, only the second polycrystalline silicon film 8 in the exposed contact hole is removed by the RIE method, and thereafter, it is oxidized in a water vapor atmosphere and the rest of the BPSG film 9 is reflowed and flattened. The second polycrystalline silicon film 8 under the BPSG film 9 is completely oxidized to form a polycrystalline silicon oxide film 11, and then exposed contacts other than the lower part of the BPSG film 9 are formed by the RIE method. Modification is made so as to remove the SiN film 13 in the hole and the oxide film 7 thereunder.

[Advantages of the Invention] As described above, according to the present invention, a MOS is formed in a self-aligned structure with the gate without deteriorating the transistor characteristics.
A semiconductor integrated circuit capable of connecting the impurity diffusion layer region of a transistor and a conductor layer and a method of manufacturing the same can be realized.

[Brief description of drawings]

1 (a) to 1 (d) are cross-sectional views showing a substrate in each step in a method for manufacturing a semiconductor integrated circuit at a stage before reaching the present invention, and FIGS. 2 (a) to (c) are semiconductors according to the present invention. 3A to 3D are cross-sectional views showing a substrate in each step in the embodiment of the integrated circuit manufacturing method, and FIGS. 3A to 3D are diagrams showing the substrate in each step in the conventional semiconductor integrated circuit manufacturing method. 1 ... Semiconductor substrate, 21, 22 ... Source of MOS transistor
Impurity diffusion layer region serving as drain, 3 ... Gate oxide film,
4 ... First polycrystalline silicon film, 5 ... CVD oxide film (first insulating film), 6 ... SiN film (second insulating film), 7 ... Thermal oxide film (first oxide film), 8 ... Second polycrystalline silicon, 9 ... BP
SG film (silicate glass film), 10, 14 ... Resist, 11 ...
Polycrystalline silicon oxide film, 12 ... Polycide (conductor layer),
13 ... SiN film.

Claims (4)

[Claims] 1. A gate oxide film formed on a semiconductor substrate of a first conductivity type, a first conductor which becomes a gate of a MOS transistor formed on the gate oxide film, and the first conductor. A first insulating film formed above, an impurity diffusion layer region of a second conductivity type, which is formed in the semiconductor substrate and serves as a source / drain of the MOS transistor, the second conductivity type being opposite to the first conductivity type; The second formed on the side surface of the first conductor
Insulating film, a third insulating film formed on the semiconductor substrate, the first insulating film and the second insulating film, and the first insulating film formed in the third insulating film. In a semiconductor integrated circuit including a second conductor formed so as to come into contact with the impurity diffusion layer region through a contact hole having such a size on the film, the third insulating film has oxidation resistance. A composite film including a film having a film, and is formed such that the oxidation resistant film does not exist on a part of the impurity diffusion layer region other than the contact hole portion. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the second insulating film has oxidation resistance. 3. A step of sequentially stacking and forming a gate oxide film, a first conductor to be a gate of a MOS transistor, and a first insulating film on a semiconductor substrate of the first conductivity type, in the semiconductor substrate. A step of forming an impurity diffusion layer region of a second conductivity type opposite to the first conductivity type, which becomes a source / drain of the MOS transistor, and a second insulating film is formed on a side surface of the first conductor. A step of forming a first oxide film on the semiconductor substrate, a step of forming a first oxide film on the semiconductor substrate, and a step of forming a first oxide film on an impurity diffusion layer region on one side of the impurity diffusion layer regions serving as the source and drain of the MOS transistor. A step of forming a silicon nitride film on the polysilicon substrate, a step of forming a polycrystalline silicon film on the entire surface of the semiconductor substrate, a step of forming a silicate glass film containing impurities on the polycrystalline silicon film, the silicon nitride film Upper part A step of forming a contact hole having a size over the first insulating film in the silicate glass, and reflowing the remaining portion of the silicate glass film in a steam atmosphere to flatten the polycrystalline silicon film. All of them to form a polycrystalline silicon oxide film, the polycrystalline silicon oxide film in the exposed contact holes other than the lower part of the silicate glass film, the silicon nitride film thereunder, and the first A method of manufacturing a semiconductor integrated circuit, comprising: a step of removing an oxide film; and a step of forming a second conductor on the silicate glass film and in the contact hole. 4. A step of sequentially stacking and forming a gate oxide film, a first conductor to be a gate of a MOS transistor, and a first insulating film on a semiconductor substrate of the first conductivity type, in the semiconductor substrate. A step of forming an impurity diffusion layer region of a second conductivity type opposite to the first conductivity type, which becomes a source / drain of the MOS transistor, and a second insulating film is formed on a side surface of the first conductor. A step of forming a first oxide film on the semiconductor substrate, a step of forming a first oxide film on the semiconductor substrate, and a step of forming a first oxide film on an impurity diffusion layer region on one side of the impurity diffusion layer regions serving as the source and drain of the MOS transistor. A step of forming a silicon nitride film on the polysilicon substrate, a step of forming a polycrystalline silicon film on the entire surface of the semiconductor substrate, a step of forming a silicate glass film containing impurities on the polycrystalline silicon film, the silicon nitride film Upper part Forming a contact hole having a size over the first insulating film in the silicate glass, and removing the polycrystalline silicon film in the exposed contact hole other than under the silicate glass film. And a step of reflowing and flattening the rest of the silicate glass film in a water vapor atmosphere to oxidize all of the polycrystalline silicon film to form a polycrystalline silicon oxide film, except the lower part of the silicate glass film. Removing the silicon nitride film in the exposed contact hole and the first oxide film thereunder, and forming a second conductor on the silicate glass film and in the contact hole. A method of manufacturing a semiconductor integrated circuit, comprising: