JPH0738448B2 - Method for manufacturing SOI MOSFET - Google Patents

Description

DETAILED DESCRIPTION [Overview] A method for manufacturing an SOI MOSFET, in which a region without crystal grains is formed in the process of recrystallization, and a channel portion and an LDD portion are formed in this region by self-alignment. It was done like this.

[Industrial application field]

 The present invention relates to a method for manufacturing an SOI type MOSFET.

The SOI type MOSFET has a silicon layer formed on an insulating substrate, a source electrode (S) and a drain electrode (D) arranged thereon, and a gate electrode (G) provided between S and D. .

This SOI type MOSFET has various advantages that it can be highly integrated, have high breakdown voltage, high speed, and three-dimensional.

However, when a grain boundary (Grain Boundary), which is a boundary (Boundary) of crystal grains (Grain), is generated in a region where carrier transport is performed in the silicon layer of the FET, carriers are scattered or deep in the crystal grain boundary. A level is generated and SOI type MOSFE
The electrical characteristics of T deteriorate.

Therefore, it is necessary to eliminate the crystal grain boundaries so that they do not exist in the carrier transport region.

[Conventional technology]

Conventionally, the size and the position of the region where the crystal grain boundaries do not exist have not been controlled by the recrystallization method.

That is, as shown in FIG. 4 (A), an energy beam such as a laser beam is scanning-irradiated in the direction of the arrow to obtain a silicon layer in which numerous crystal grain boundaries gb are formed in which crystal grains are once liquefied and solidified again. . The crystal grains are enlarged in the process of this recrystallization. In the figure, R indicates a transistor region.

[Problems to be solved by the invention]

However, in the above-described conventional manufacturing method, the crystal grain boundary may be located in the channel region.

For example, as shown in the diagram on the left side of FIG.
There are cases in which gb ₁ is parallel to the longitudinal direction, and cases in which gb ₂ exists in the lateral direction as shown in the diagram on the right side of the figure.

In the former case, accelerated diffusion of the dopant of the source or drain layer occurs along gb ₁ to cause a short in an extreme case.
In the latter case, the presence of gb ₂ causes carrier scattering to reduce the amount of movement.

That is, conventionally, there has been a problem that the electrical characteristics are adversely affected.

[Means for solving problems]

An object of the present invention is to provide a method for manufacturing an SOI type MOSFET that solves the above problems and does not adversely affect the electrical characteristics.

A means for that is to form a layer for controlling heat conduction, in which a region corresponding to a region having no grain boundary is protruding, on the silicon layer, and further, an energy ray absorbing layer is formed thereon, and the energy ray absorbing layer is formed. By irradiating an energy beam from above, crystal grain boundaries are prevented from being formed in the silicon layer region corresponding to the above-mentioned protruding portion in the recrystallization process, and the channel portion and the LDD portion are formed inside this by self-alignment. It is a thing.

[Work]

As described above, according to the present invention, it is possible to form a region in the silicon layer in which the generation of grain boundaries is prevented during the recrystallization process.

Therefore, the crystal grain boundary does not exist under G between S and D, and the accelerated diffusion or scattering of the dopant does not occur, so that the electrical characteristics are not adversely affected.

〔Example〕

Hereinafter, the present invention will be described by way of examples with reference to the accompanying drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 1 (A) is a cross-sectional view, in which the heat conduction control layer 3 having the protrusions 31 on the upper surface of the silicon layer 2 formed on the insulator substrate 1 is further laminated with the energy ray absorbing layer 4. ing.

The energy rays 5 are scanned and irradiated from above the energy ray absorption layer 4 (FIG. 3 (A)).

At this time, a heat flow occurs from the energy ray absorbing layer 4 which absorbs the laser light and generates heat to the silicon layer 2 through the heat conduction control layer 3. Since the amount of heat flow of No. 2 is larger than that of the portion other than the protrusion 31, the temperature distribution is as shown in FIG. 1 (B), and no grain boundary is generated in the silicon layer inside 21 below the protrusion 31. (FIG. 3 (B)). In other words, by forming this temperature distribution, the place where the nucleus growth starts was defined, and at the same time, the size of the crystal grain was defined.

Then, the energy ray absorbing layer 4 is peeled off (FIG. 3 (C)).

Then, after the exposed heat conduction control layer 3 (FIG. 1A) is doped with an ion implantation mask to form source and drain regions (FIG. 3D), the control layer 3 is peeled off. To do.

Next, the elements are separated and the gate oxide film 6 is formed (FIG. 3 (E)).

Finally, the gate electrode 6 having a width narrower than the region 21 where the crystal grain boundaries do not exist is formed, and the LDD portions 8 and 9 are formed using this as a mask (FIG. 3 (F), FIG. 2).

That is, the LDD portion is formed by self-alignment using the gate electrode. In this LDD (Lightly Doped Drain) part, the amount of impurities is about 1/100 of that of the drain.

After that, it is completed as a product by the same process as a normal MOSFET.

〔The invention's effect〕

As described above, according to the present invention, it is possible to form a region in the silicon layer in which the generation of grain boundaries is prevented during the recrystallization process.

Therefore, the grain boundary can be eliminated from below G between S and D,
Since the enhanced diffusion of the dopant or the scattering of carriers does not occur, the electrical characteristics are not adversely affected.

[Brief description of drawings]

FIG. 1 is a view showing an embodiment of the present invention (No. 1), FIG. 2 is a view showing an embodiment of the present invention (No. 2), FIG. 3 is a process chart according to the present invention, and FIG. FIG. 1 ... Insulator substrate, 2 ... Silicon layer, 3 ... Heat conduction control layer, 4 ... Energy ray absorption layer, 21 ... Region where no grain boundaries exist, 31 ... Protrusion.

Claims (1)

[Claims] 1. A heat conduction control layer having a protrusion is further formed on an upper surface of a silicon layer formed on an insulating substrate, and an energy ray absorbing layer is formed thereon. Is applied to form a region where no crystal grain boundary exists in the silicon layer region corresponding to the lower part of the protrusion, and then the energy ray absorbing layer is removed, and the exposed heat conduction control layer is used as a mask to form the source and drain. In order to do so, the source and drain regions are formed, then the heat conduction control layer is peeled off, a gate oxide film is formed, and a gate electrode narrower than the width of the region where no crystal grain boundary exists is provided. A method for manufacturing an SOI-type MOSFET, characterized in that the LDD portion is formed by self-alignment with doping as a mask.