JPH0738453B2 - Stacked semiconductor device - Google Patents
Stacked semiconductor deviceInfo
- Publication number
- JPH0738453B2 JPH0738453B2 JP59237073A JP23707384A JPH0738453B2 JP H0738453 B2 JPH0738453 B2 JP H0738453B2 JP 59237073 A JP59237073 A JP 59237073A JP 23707384 A JP23707384 A JP 23707384A JP H0738453 B2 JPH0738453 B2 JP H0738453B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- semiconductor device
- laminated
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/17—Photovoltaic cells having only PIN junction potential barriers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Landscapes
- Recrystallisation Techniques (AREA)
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は非晶質半導体と微結晶質半導体の積層体から
なる積層半導体素子に関するものである。TECHNICAL FIELD The present invention relates to a laminated semiconductor device including a laminated body of an amorphous semiconductor and a microcrystalline semiconductor.
半導体素子の材料として、非晶質シリコン（以下、ａ−
Siと称する）は、次のような長所と欠点を有する材料と
して知られている。Amorphous silicon (hereinafter a-
Si) is known as a material having the following advantages and disadvantages.
（長所） （１）低温（250℃以下）で形成できる （２）低コスト基板（合成樹脂、ガラス、金属、セラミ
ックス）が使用できる。(Advantages) (1) Can be formed at low temperature (250 ° C or lower) (2) Low cost substrate (synthetic resin, glass, metal, ceramics) can be used.
（３）大面積化が容易である。(3) It is easy to increase the area.
（４）光の吸収係数が大であるため、薄膜で光電変換素
子などが構成できる。(4) Since the absorption coefficient of light is large, a photoelectric conversion element or the like can be formed with a thin film.
（５）光電導度が大である。(5) The photoconductivity is high.
（欠点） （１）キャリアの移動度が小さい。(Disadvantage) (1) The mobility of carriers is small.
（２）光電変換効率が低い。(2) The photoelectric conversion efficiency is low.
一方、微結晶シリコン（以下、μｃ−Siと称する）は、
次のような長所と欠点を有する材料として知られてい
る。On the other hand, microcrystalline silicon (hereinafter referred to as μc-Si) is
It is known as a material having the following advantages and disadvantages.
（長所） （１）ａ−Siに比べて、キャリア移動度、不純物ドーピ
ング効率が良い。(Advantages) (1) Carrier mobility and impurity doping efficiency are better than those of a-Si.
（２）ｎ型層は、電気伝導度が良く、電導度の活性化エ
ネルギが小さいので、pin構造やショットキー構造の半
導体装置に利用されている。(2) The n-type layer has a good electric conductivity and a small activation energy of the electric conductivity, and therefore is used for a semiconductor device having a pin structure or a Schottky structure.
（欠点） （１）光電導度、キャリアの寿命が小さく、かつ欠陥密
度が大であるため、真正層あるいはノンドープ層として
は利用されていない。(Defects) (1) It is not used as a genuine layer or a non-doped layer because it has a small photoconductivity, a short carrier life, and a large defect density.
なお、結晶シリコン（以下、ｃ−Siと称する）は、次の
ような長所と欠点を有する。Crystalline silicon (hereinafter referred to as c-Si) has the following advantages and disadvantages.
（長所） （１）欠陥が少なく、キャリアの移動度が大である。(Advantages) (1) Fewer defects and higher carrier mobility.
（２）光電変換素子に応用した場合、大きい光電変換効
率を得ることができる。(2) When applied to a photoelectric conversion element, a large photoelectric conversion efficiency can be obtained.
（欠点） （１）溶融する必要があるため、製造工程に高温工程が
含まれ、また大面積化が困難である。(Disadvantages) (1) Since it needs to be melted, the manufacturing process includes a high temperature process, and it is difficult to increase the area.
（２） 光の吸収係数が小さい。(2) The absorption coefficient of light is small.
この発明は、ａ−Si、μｃ−Si、ｃ−Siの上記のごとき
諸特性にかんがみ、ａ−Siおよびμｃ−Siを用いて好ま
しい特性、特にμτ積（キャリアの移動度μと寿命τの
積）の大きい半導体素子を提供することを目的とするも
のである。In view of the various characteristics of a-Si, μc-Si, and c-Si, the present invention uses a-Si and μc-Si to obtain preferable characteristics, particularly the μτ product (carrier mobility μ and lifetime τ. It is intended to provide a semiconductor device having a large product).
この発明は、上記の目的を達成するために、図１に示す
ように、基板１上に順にｐ型ａ−Siまたはｐ型ａ−SiC
（非晶質炭化シリコン）でなるｐ型層２、ｉ型ａ−Si層
３、μｃ−Si層４とａ−Si層５からなる単位積層体６を
繰返し数が２〜10回の範囲で積層したｉ型多層積層体、
ｉ型μｃ−Si最終層４、ｉ型ａ−Si層７、およびｎ型μ
ｃ−Si層８を順次積層した構造を採用したものである。In order to achieve the above-mentioned object, the present invention is, as shown in FIG.
The p-type layer 2 made of (amorphous silicon carbide), the i-type a-Si layer 3, the unit laminate body 6 made up of the μc-Si layer 4 and the a-Si layer 5 is repeated in the range of 2 to 10 times. A laminated i-type multilayer laminate,
i-type μc-Si final layer 4, i-type a-Si layer 7, and n-type μ
This is a structure in which the c-Si layer 8 is sequentially laminated.
また、上記単位積層体６の繰返し数をｍ（ｍは２〜10の
間の整数）、μｃ−Si層の厚さをμｄ、ａ−Si層の厚さ
をadとしたとき、 ｍ（μｄ＋ad）＝2000Å − の関係にある。When the number of repetitions of the unit laminate body 6 is m (m is an integer between 2 and 10), the thickness of the μc-Si layer is μd, and the thickness of the a-Si layer is ad, m (μd + ad ) = 2000Å-
なお、第１図において符号９で示した範囲の各層はｉ型
層を形成する。In addition, each layer in the range indicated by reference numeral 9 in FIG. 1 forms an i-type layer.
上記のａ−Si層およびμｃ−Si層は、例えば次のごとき
方法によって作られる。The above-mentioned a-Si layer and μc-Si layer are formed by the following method, for example.
（１）プラズマCVD法 少なくともSiH4、SiH6、SiF4などのSi化合物ガスを含む
ガスをグロー放電分解させることによりａ−Siが得ら
れ、このときSi化合物ガスを水素などで希釈し、或いは
グロー放電分解の際の投入パワーを大きくすることより
μｃ−Siが得られる。(1) Plasma CVD method a-Si is obtained by glow discharge decomposition of a gas containing at least Si compound gas such as SiH 4 , SiH 6 , and SiF 4 , and at this time, the Si compound gas is diluted with hydrogen or the like, or By increasing the input power during glow discharge decomposition, μc-Si can be obtained.
（２）スパッタ法 Siターゲットを水素、フッ素などを含むガスでスパッタ
ーすることによりａ−Siが得られ、このときスパッター
のパワーを大きくすることによりμｃ−Siが得られる。(2) Sputtering method A-Si is obtained by sputtering a Si target with a gas containing hydrogen, fluorine, etc. At this time, μc-Si is obtained by increasing the sputtering power.
図１の構造において、ｉ型層９の全体の厚さを6000Åと
することができる。このときμｄは50Å、adは前記式
からｍが２〜10の範囲で950Å（ｍ＝２）〜150Å（ｍ＝
10）となる。In the structure of FIG. 1, the total thickness of the i-type layer 9 can be set to 6000Å. At this time, μd is 50Å and ad is 950Å (m = 2) to 150Å (m =
10).
第２図は実験結果を示すものであり、本発明の場合の繰
返し数ｍに対するキャリア（正孔と電子）のμτ積の総
和を黒丸で示している。また、比較のために、単層のａ
−Si、μｃ−Siの場合を白丸で示している。FIG. 2 shows the experimental results, and the total sum of μτ products of carriers (holes and electrons) with respect to the number of repetitions m in the present invention is shown by black circles. For comparison, a single layer a
In the case of -Si and μc-Si, white circles are shown.
このグラフからわかるように、２≦ｍ≦10（但し、ｍは
整数）の範囲で単層のものより高μτ積が得られること
がわかった。As can be seen from this graph, it was found that a higher μτ product can be obtained in the range of 2 ≦ m ≦ 10 (where m is an integer) than that of the monolayer.
なお、ｉ型層９の両端のａ−Si層３、７の厚さをそれぞ
れ100〜5000Åとすることができ、また、μｄを20〜500
Åとし、前記式よりｍが２〜10の範囲でadを50Å（ｍ
＝10、μｄ＝150Å）〜980Å（ｍ＝２、μｄ＝20Å）と
することができる。The thickness of each of the a-Si layers 3 and 7 at both ends of the i-type layer 9 can be set to 100 to 5000Å, and μd can be set to 20 to 500.
From the above formula, ad is 50Å (m
= 10, μd = 150Å) to 980Å (m = 2, μd = 20Å).
この発明は、上記のごときのものであるから、キャリア
のμτ積を大きくすることができ、その結果、光起電力
素子や発光素子に使用した場合に、光電変換効率の高い
素子を得ることができる。また、キャリアの移動速度が
大であるため、薄膜トランジスタや光電導素子に使用し
た場合応答速度の速い素子を得ることができる。Since the present invention is as described above, it is possible to increase the μτ product of carriers, and as a result, it is possible to obtain an element with high photoelectric conversion efficiency when used in a photovoltaic element or a light emitting element. it can. Further, since the moving speed of carriers is high, it is possible to obtain an element having a high response speed when used in a thin film transistor or a photoconductive element.
第１図は実施例の積層半導体素子の積層構造を拡大して
示した説明図、第２図は実験結果のグラフである。 １……基板、２……ｐ型層、３……ａ−Si層、４……μ
ｃ−Si層、５……ａ−Si層、６……単位積層体、７……
ａ−Si層、８……ｎ型層、９……ｉ型層FIG. 1 is an explanatory view showing an enlarged laminated structure of a laminated semiconductor element of an example, and FIG. 2 is a graph of experimental results. 1 ... Substrate, 2 ... p-type layer, 3 ... a-Si layer, 4 ... μ
c-Si layer, 5 ... a-Si layer, 6 ... Unit laminated body, 7 ...
a-Si layer, 8 ... n type layer, 9 ... i type layer
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 電子材料 1982年９月号 第35〜40頁 電気学会雑誌 第102巻 第12号、第 1117〜1122頁（1982、12) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Bibliography Electronic materials September 1982, pages 35-40, The Institute of Electrical Engineers of Japan Volume 102, No. 12, 1117-1122 (1982, 12)
Claims (3)
Cでなるｐ型層、ｉ型ａ−Si層、μｃ−Si層とａ−Si層
からなる単位積層体を繰返し数が２〜10回の範囲で積層
したｉ型多層積層体、ｉ型μｃ−Si最終層、ｉ型ａ−Si
層、およびｎ型μｃ−Si層を順次積層した構造であり、
上記単位積層体の繰返し数をｍ（ｍは２〜10の間の整
数）、μｃ−Si層の厚さをμｄ、ａ−Si層の厚さをadと
したとき、ｍ（μｄ＋ad）＝2000Åの関係にある積層半
導体素子。1. A p-type a-Si or a p-type a-Si on a substrate in order.
An i-type multilayer laminate in which a unit laminate composed of a p-type layer made of C, an i-type a-Si layer, a μc-Si layer and an a-Si layer is laminated in the range of 2 to 10 times, i-type μc -Si final layer, i-type a-Si
A layer and an n-type μc-Si layer are sequentially laminated,
When the number of repetitions of the unit laminate is m (m is an integer between 2 and 10), the thickness of the μc-Si layer is μd, and the thickness of the a-Si layer is ad, m (μd + ad) = 2000Å Laminated semiconductor device having a relationship of.
が20〜500Å、ａ−Siの厚みがadが50〜980Åである特許
請求の範囲第１項に記載の積層半導体素子。2. Only the μc-Si layer constituting the unit laminate is μd.
Is 20 to 500Å, and the thickness of a-Si is ad is 50 to 980Å, The laminated semiconductor element according to claim 1.
層の厚みが100〜5000Åである特許請求の範囲第１項又
は第２項に記載の積層半導体素子。3. An i-type a-Si provided on both ends of an i-type multilayer laminate.
The laminated semiconductor device according to claim 1 or 2, wherein the layer has a thickness of 100 to 5000 Å.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59237073A JPH0738453B2 (en) | 1984-11-10 | 1984-11-10 | Stacked semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59237073A JPH0738453B2 (en) | 1984-11-10 | 1984-11-10 | Stacked semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61115319A JPS61115319A (en) | 1986-06-02 |
| JPH0738453B2 true JPH0738453B2 (en) | 1995-04-26 |
Family
ID=17010012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59237073A Expired - Lifetime JPH0738453B2 (en) | 1984-11-10 | 1984-11-10 | Stacked semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0738453B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5131249B2 (en) * | 2008-06-25 | 2013-01-30 | 富士電機株式会社 | Thin film solar cell |
| KR101106480B1 (en) * | 2009-06-12 | 2012-01-20 | 한국철강 주식회사 | Method of manufacturing photovoltaic device |
-
1984
- 1984-11-10 JP JP59237073A patent/JPH0738453B2/en not_active Expired - Lifetime
Non-Patent Citations (2)
| Title |
|---|
| 電子材料１９８２年９月号第３５〜４０頁 |
| 電気学会雑誌第１０２巻第１２号、第１１１７〜１１２２頁（１９８２、１２） |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61115319A (en) | 1986-06-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |