JPH0738682B2 - Image signal processing processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing processor, and in particular, a component necessary for the image signal processing processor is a 1-chip LS.
The present invention relates to an image signal processor housed in I (large-scale integrated circuit).

[Background of the Invention]

Image signal processing in products equipped with photoelectric conversion reading sensors such as facsimiles, OCRs, high-function copiers, and hand scanners varies depending on the product and the model. Therefore, these products have a dedicated image signal processing circuit suitable for each image signal processing, and this image signal processing circuit cannot be applied to another product or model.

For example, in the field of facsimiles, (1) the size of the transmitted document and the size and linear density of the received recording paper (2) the relative position of the transmitted document and the reading sensor (3) the amplitude of the image signal from the reading sensor (4) in terms of performance (image quality The image signal processing mode differs depending on the values such as the setting values in (above). CCIT
At the recommendation of T (International Telegraph and Telephone Advisory Committee), Group III (G
In III), the facsimile machine is defined as a standard mode in which 1728 pixels are transmitted / received line by line from the left side of the screen using the MH code or the MR code at a line density (main scanning direction) of 8 lines / mm. This is for sending and receiving A4 size or letter size originals with a paper width of 216 mm. However, in reality, there is also communication between a transmitter that can send a B4 size document with a paper width of 257 mm and an A4 size receiver. Regarding linear density, not only 8 / mm, but also 12 / mm, 16 / mm or 200 / inch, 240 / inch, 300 / inch, 400 / inch, etc. are manufactured. It has been developed or is being developed, and it is desirable that these faxcimiles can communicate freely. For this purpose, each facsimile must have a function of reducing or expanding image data.

As for the output of the image signal of a photoelectric conversion reading sensor such as a commercially available CCD sensor, there are different channels for each pixel, a single channel, a waveform-shaped output, and the like. Further, the amplitude of the image signal also varies depending on the luminance variation of the light source and the sensitivity variation of the sensor, and changes depending on the document density. Because of these, the amplitude of the image signal changes more than 10 times, so matching is necessary.

Further, as a method of reading a halftone image, there is an organized dither method. This is a method of switching the level for slicing an image signal for each pixel according to a certain pattern. It is necessary to set this pattern and determine the set value of γ correction at the time of reading.

Further, the facsimile has a function of changing the scanning pitch in the sub-scanning direction to fast-forward an area having a small amount of information. Therefore, a linear density determination function for determining the information amount of the original to be transmitted is necessary.

Furthermore, the sensor has a variation in sensitivity for each pixel, and a function for correcting this is required.

In the conventional image signal processor, it has been recognized that each function is different depending on the usage conditions as described above, and that a dedicated circuit configuration must be adopted for each function, so that the image signal processor has one chip. In the case of configuring with LSI, each component such as an analog signal processing section and its related control section, a digital signal processing section and its related control section are individually separated.
It was made into an LSI, and those LSIs were used in an appropriate combination.

Therefore, every time the product or model of the image signal processor is different, a new LSI for performing the processing is designed,
Since it has to be developed, the conventional image signal processor has a problem that the product cost is increased due to the increase in development cost and the miniaturization is hindered by the use of a plurality of LSIs.

Therefore, the present invention has been made to eliminate such problems.

[Object of the Invention]

One of the objects of the present invention is to make most of the various components required in the image signal processor 1
An object of the present invention is to provide an image signal processor adapted to be housed in a chip LSI.

Another object of the present invention is to deal with the change of one or more functions executed in the image signal processor with the change of the externally connected sensor etc. only by changing the value of the internal register. An image signal processor is provided.

[Outline of Invention]

In order to achieve the above object, the present invention specifies an analog signal processing unit that corrects distortion of an analog signal input from a sensor and outputs the digital signal, and main and sub-scanning line densities of the digital signal. Digital signal processing unit for each conversion into scanning line density, sensor driving unit for driving sensor, timer and sequencer for setting operation timing of each unit, and coupling to externally connected control unit via data bus and control bus Each of the interfaces described above,
A register that sets an operation mode, various commands, and various parameter values in the LSI in correspondence with an address, a controller that writes the address of the register based on data supplied from the externally connected control device, and the digital signal An image signal processor including a bus buffer for supplying an output digital signal from a processing unit to the externally connected control device, and an image signal processor constituted by a one-chip LSI is obtained. The signal processor can be used in various ways.

Example of Invention

An embodiment of the present invention will be described in detail below. First
The figure shows an example of the circuit configuration of the processor 10 and its peripherals according to the present invention. 1 is an analog signal processing unit, 2 is a digital signal processing unit, 3 is a line memory, 4 is a sensor driver interface (sensor I / F), 5 is a timer, 6 is a sequencer, and 7 is a μCPU interface (μCPUI / F). , 8
Is a μCPU.

The processor 10 of the present invention is made as a one-chip LSI,
This LSI is an analog signal processing unit 1, digital signal processing unit
It is equipped with 2, sensor I / F 4, timer 5, sequencer 6, and μCPU I / F 7.

A timing signal for driving a sensor (CCD line sensor or the like) is generated by the sensor I / F 4, and an analog image signal synchronized with the timing signal is input to the analog signal processing unit 1.

The analog signal processing unit 1 is almost the same as that described in JP-A-56-157575. The analog signal processing unit 1 stores the signal distortion characteristics caused by an optical system, such as a lens or a light source, so that the image signal coming from the sensor is properly digitized. The digitalized image signal is input to the digital signal processing unit 2. The digital signal processing unit 2 converts the digital signal into an information form necessary for a device such as a facsimile, and
It is sent to the bus line of μCPU8 through CPUI / F7 and output as serial information.

The functions of the digital signal processing unit 2 include linear density conversion (mainly reduction) in the main scanning direction and the sub scanning direction, or the above-described linear density determination. In order to convert the line density in the sub-scanning direction, it is necessary to store the information of the preceding line or the preceding line. The line memory 3 is connected for this purpose.

The digital signal processing unit 2 can also receive information from the bus line of the μCPU 8 through the μCPU I / F 7 and output it as serial information. This can serve as an interface for outputting data to the recording device when receiving a signal such as facsimile.

The timer 5 generates a timing signal or the like for determining a repeating time for driving the sensor and for cutting out an effective portion of an image signal from the sensor.

The sequencer 6 generates a timing signal for operating the entire processor.

FIG. 2 is an embodiment in which the block diagram of the LSI 10 shown in FIG. 1 is described in more detail.

11 is a sample hold circuit, 12 is a peak hold circuit,
13 is an A / D / D / A conversion circuit, 14 is a differential modulation / demodulation circuit, and 15 is RA
M and 16 are circuit blocks of the A / D conversion circuit, which correspond to the analog signal processing unit 1. 21 is a main scanning line density conversion circuit, 22 is an address counter, 23 is a video bus buffer,
Reference numeral 24 is a sub-scanning line density conversion circuit, 25 is a line density determination circuit, 26 is a serial output circuit, and 27 is each circuit block of a latch circuit, which correspond to the digital signal processing unit 2. 31 is
The distortion characteristic signal is stored in RAM. 71 is a controller, 72 is a system bus buffer, and 73 is a register.
Configure UI / F7. 91 is the control bus of μCPU8, 92
Is a data bus. A system bus 93 is connected to the data bus 92 through a system bus buffer. 94 is a video bus.

FIG. 3 is an operation time chart for each block shown in FIG. The operation of the processor 10 shown in FIG. 2 will be described with reference to FIG.

The image signal processor according to the present invention stores the program of the externally connected μCPU8 in the internal register 73 of the μCPU I / F7.
By writing the data as data to the processor, the operation mode of the processor is determined, and functions such as start and stop of required operations of the upper processor are achieved. An example of the operation of the processor 10 will be described below.

First, the μCPU 8 inputs a reset signal (RESET) to the processor 10 in order to reset registers and counters. After that, the register 73 is set through the controller 71 to determine the operation mode of this processor.
Next, the work enable register in the same register 73 is rewritten. That is, the processor enable signal (PR
By setting CE), the processor 10 starts the operation in the already defined mode. At this time, first the sensor
The sensor drive pulse starts from I / F4. The first input image signal usually cannot be correct read data. After driving the sensor a plurality of times, the peak hold enable signal (PEAKE) in the register 73 is set. This starts the operation of the peak hold circuit 12,
The maximum white value of the image signal (minimum value in the time chart of FIG. 3; the white signal of the image signal from the sensor is output to the lower side) is detected. The sample and hold circuit
11 starts operating when the PRCE signal is output. Next, the white information is read over one line, and the signal distortion amount included in the white image information is stored in the RAM 15. The signal distortion storage command signal (WCOM) for this purpose is set by rewriting the register 73.

When a CCD line sensor is used, the signal distortion often has a shape as shown in FIG. 3 due to a decrease in the amount of light around the lens, unevenness of the light source, or variation in sensitivity of the sensor itself. This signal distortion is generally called a shading waveform.

When the WCOM signal rises, the sensor drive is repeated a plurality of times (23 times in this embodiment) to detect the initial value of the image signal output from the sample hold circuit 11. Initial value in the A / D / D / A conversion circuit 13 (minimum value in a plurality of pixels at the beginning of the image signal, 8 pixels in this embodiment; output value from black)
To detect. A / D / D / A at the next image signal (24th time)
The conversion circuit 13 executes A / D conversion by the follow-up comparison method,
Further, the differential modulation / demodulation circuit 14 modulates to a differential signal. Then, this difference signal is stored in the RAM 15.

By using the output voltage of the peak hold circuit 12 as the reference voltage of the A / D / D / A conversion circuit 13, the variation in the output amplitude of the image signal from the sensor is corrected.

In addition, each pixel correction sensitivity correction mode specification bit (AADJ), which is the 0th bit of the work enable register (one of the registers shown in Table 8) that specifies the mode for correcting the sensitivity of the image signal for each pixel, is set to 1. If set,
At the 25th time of the image signal, a distortion signal for each pixel is created by the analog signal processing unit 1, and this is RA through the video bus.
Store in M31. The RAM 31 is connected to the outside of this LSI processor 10.

After that, when an image signal including image information is input from the sensor, the waveform of the image signal is shaped by the sample hold circuit 11, and the peak value is detected by the peak hold circuit 12. This peak value is used as the reference voltage of the A / D / D / A conversion circuit 13. The signal read from the RAM 15 is demodulated by the differential modulation / demodulation circuit 14 and D / A converted by the A / D / D / A conversion circuit 13 to reproduce the shaded waveform signal. The reproduced shading waveform signal is input as the reference voltage of the A / D conversion circuit 16. As a result, the A / D conversion circuit 1
6 can output a digital signal without distortion.

Even when the sensitivity correction for each pixel of the image signal is executed, the RAM 31 is read in synchronization with the image signal from the sensor, and the output is D / A converted by the A / D / D / A conversion circuit 13.
Reproduce the distortion for each pixel. Correction is performed by inputting distortion for each pixel to the reference voltage of the A / D conversion circuit 16.

The sensitivity-corrected digital image signal is input to the digital signal processing unit 2, subjected to signal processing in synchronization with the digital image signal, and output to the μCPU 8 via the system bus buffer 72 of the μCPU I / F 7. The serial output circuit 26 converts the serial signal into a serial signal and outputs the serial signal to the outside of the processor 10.

In the processor 10, the output of the A / D conversion circuit 16 is divided into a multi-value (4-bit binary) mode and a binary mode. The output of the halftone information by the dither method is included in the binary mode.

In the multi-valued mode, a 4-bit binary signal for 2 pixels can be collected into 8 bits and output to the line memory 3. At this time, the corrected information for each pixel of the sensor is
It is also possible to output to the line memory 3.

In the binary mode, the output is output to the main scanning line density conversion circuit 21.
To the line memory 3 through the video bus buffer 23 to perform the linear density conversion by the operation defined in the register 73. At this time, the address signal of the line memory 3 is generated by the address counter 22 in the processor 10. Binary data of the previous line and the line before two read from the line memory 3 in synchronization with the binary data of the current line output from the main scanning line density conversion circuit 21 are input to the sub scanning line density conversion circuit 24. . The sub-scanning line density conversion circuit 24 executes the line density conversion operation according to the instruction from the register 73. The result is output to the μCPU 8 through the system bus buffer 72.

The timer 5 controls the sensor driving cycle and the clipping of the effective portion of the digital image signal output from the processor 10. The sequencer 6 also generates timing signals and the like necessary for executing the operations described so far.

The circuit block of FIG. 2 will be described in detail below.

FIG. 4 is a schematic circuit diagram of the sample hold circuit 11. FIG. 5 is a time chart of each part of FIG. Table 1 shows the sample hold circuit from register 73 to FIG.
This is a summary of the register allocation for signals input to each of the 11 circuits. 110 is a decoder TrC ₁ , TrC ₂ , TrS ₁ ,, Tr
S ₂ , TrS, TrC, TrI ₁ , TrI ₂ , and TrIO are MOS transistors.
Although an actual LSI uses a C-MOS (complementary MOS), it is represented by a single MOS for simplicity of illustration. The positive logic is such that the MOS transistor is turned on when the gate input is at a high level. ANDS1, AN
DS2, ANDC1, ANDC2 are AND gates, IN1 is an inverter, OP
-S is an operational amplifier, and C ₁ , C ₂ and C ₃ are capacitors. Image signal 1 (Image Sig. 1) and image signal 2 (Image Sig. 1)
ig.2) is the input signal from the sensor, V _BL is the DC voltage that indicates the black level, and is input from the outside. Image signal output (Im
age Sig.0) is the output signal sampled and held.

Output of decoder 110 R111, R112, R113, R114, R115, R116, R11
The circuit operation of this circuit is determined by the signals of 7, R118 and R119. These signals are the 3-bit register SM of register 73.
It can be obtained by decoding D0, SMD1 and SMD2 with the decoder 110. The input signals R111 to 119 are defined as shown in Table 1. The sample hold circuit 11 operates in six modes. The first mode is to input the image signal from the sensor with 1-channel output as Image Sig.1, sample and hold the waveform as shown in Fig. 5 (1), and set the black level to V _BL . Hold down. Operational amplifier O
Output the P-S output as an image signal output (Image Sig. 0) that is sampled and held. In FIG. 5, φ _S1 is a sampling pulse, and φ _C1 is a clamp pulse for matching the black level of the image signal with the voltage V _BL .

The second mode operates the same as the first mode, but MO
The S-transistor TrIO is set to high impedance and the sample-and-hold signal is output as an image signal (Image
Sig.0) is not output.

In the third mode, the output sensor output of 2 channels is Imag
Input as e Sig.1,2 and execute sample hold and black level clamp at the timing as shown in Fig. 5 (2). φ _S2 is a sampling pulse, and φ _C2 is a clamp pulse. At this time, the sample hold signal is Image Sig.0.
Is output to.

The fourth mode is similar to the third mode, but the sampled and held image signal (Image Sig. 0) is not output.

The fifth mode is a mode in which the image signal sampled and held by the external circuit is input to the operational amplifier OP-S from the terminal of the image signal 1, and the sampling pulse φ _S is given to the external circuit from the terminal of Image Sig. A clamp pulse φ _C is applied to the external circuit from the 0 terminal. φ _S is the same signal as φ _{S1 in} FIG. 5 (1), and φ _C is the same signal as φ _{C1 in} FIG. 5 (1).

The sixth mode is a mode in which φ _S and φ _C are output similarly to the fifth mode, and the image signal of Image Sig.1 is directly supplied to the inside of the processor 10 as an image signal (Image Sig.). is there.

FIG. 6 is an example of a detailed circuit block of the peak hold circuit 12. 120 is a counter, 121 is a decoder, 122 is a bus switch, 123 is a digital comparator, and ANP1 to 3
Is an AND gate, INP1 to 3 are inverters, TrPO, TrPP, Tr
PI and TrP0 to n (n = 255 in this embodiment) are MOS transistors and are described in positive logic. COMPP is an analog comparator, OP-2 is an operational amplifier, and RP is a resistor string.

FIG. 7 is a time chart for explaining the operation of the peak hold circuit 12 shown in FIG. The image signal (Image Sig. 0) is input in synchronization with the sensor start signal φ _TG . At this time, assuming that the counter 120 is reset, the decoder 121 selects the MOS transistor TrPO.
Therefore, the output PEAK of the operational amplifier OP-2 shows V ₀ volt.
(However, the input signal APEAKE from the register 73 is at low level.) Next, when the signal PAPW from the timer 5 goes high, the counter 120 is driven in UP mode until the output signal of the analog comparator COMPP is inverted. It As a result, the peak value (white peak) of the image signal (Image Sig.0) is obtained at the output PEAK of the operational amplifier OP-2.
(However, the output PEAKE of the register 73 is low level) The sensor start signal φ _TG is input to the down clock (DOWNCLK), and the peak value is lowered by one resistor string.

The resistor string R-P defines the voltage at each node as represented by the following equation.

That is, V _{0 to} Vn are geometric series. This is because the quantization error has a constant rate regardless of the magnitude of the peak value of the image signal.

In this LSI10, the V _BL voltage is 3.5 V maximum with an external input signal.
Allow up to. If V _BL = 3.5V, V ₀ = 3.4V, V ₂₅₅ = 1.
Set to 5V. If this interval is divided according to the equation (1), the quantization error of the peak value output PEAK of the image signal is 1.
It will be less than 1%.

The output signal of the counter 120 is given to the system bus 93 through the bus switch 122. This allows the μCPU 8 to read the output signal of the counter 120. Also μCPU8
It is also possible to set the peak value output PEAK to a constant value by writing the signals of PEAK0 to PEAK7 to the register 73 and loading this value into the counter 120.

Value of PDM2 to 7 written in register 73 and counter 120
The values of Q _{2 to} Q ₇ of are compared by the digital comparator 123,
When the output of the counter 123 becomes smaller than the value of PDM2 to 7, the increment of the counter 123 can be stopped. That is, it is possible to prevent the peak value output PEAK from falling below the values of PDM2 to 7. This is necessary to prevent the peak value output PEAK from following up to the black level when reading a black original, and to detect black information as black.

When the output PEAKE of the register 73 is set to the high level, the operation of the counter 120 is stopped and the peak value output PEAK holds a constant value. When APEAKE is set to high level, the selected voltage of the resistor string R-P is output to PEAKO, and at the same time, the voltage input to PEAKI is output to the A / D / D / A conversion circuit 13 as a PEAK signal.

The output FLEXG of the digital comparator 123 is input to the register 73 and can inform the μCPU 8 whether the peak value of the image signal is lower or higher than the value set by PDM2 to 7.
If this function is used, the μCPU8 can judge the decrease in the brightness of the light source.

FIG. 8 is an example of a detailed circuit block of the A / D / D / A conversion circuit 13.

130 is a counter, 131 is an adder circuit, 132 and 133 are decoders, 1
34 is an initial value register. This initial value register 134
Latches the outputs of the initial value setting registers FD0 to FD7 shown in the register name column of Table 8. 135 is a bus switch, RA is a resistor string, TrA0 to n ', TrAH, TrAS, T
rAA is a MOS transistor, COMPA is a comparator, OP3-4
Is an operational amplifier.

FIG. 9 is a time chart for explaining the operation of the A / D / D / A conversion circuit 13 shown in FIG.

As described in FIG. 3, the A / D / D / A conversion circuit 13 performs the A / D conversion operation, as shown in FIG.
It's time to stand. At that time, first, the SMSK signal is input from the timer 5, and the rising edge of the image signal for 8 pixels from the SMSK is detected as an initial value. This operation may be performed by giving a gate signal for eight pixels (created by the sequencer 6) to the counter 130 and performing the same operation as the peak hold in FIG.
The output of the counter 130 at this time is latched in the initial value register 134. The initial value register 134 can be written and read from the μCPU 8 through the system path 93.

When the initial value is determined, that value is output to the decoder 132. One of the MOS transistors TrA0 to TrAn 'is selected and turned on, and its output voltage and image signal Im
age Sig.0 is compared by the comparator COMPA. The counter 130 repeatedly increments or decrements according to the output of the comparator COMPA, and the operational amplifiers OP-3 and OP-3
The shaded waveform is output to the output of -4. That is, this A / D conversion operation is a so-called follow-up comparison type A / D conversion method. The output of the comparator COMPA is input to the differential modulation / demodulation circuit 14.

Next, when the image signal Image Sig.0 is input, the A / D / D / A conversion circuit 13 performs a D / A conversion operation in synchronization with this. The demodulated signal demodulated from the differential modulation / demodulation circuit 14 is the counter 130.
When input to, the same operation as controlled by the output of the comparator COMPA is performed at the time of writing. As a result, almost a shaded waveform can be reproduced as the output signals DAO and OP4-0 of the operational amplifiers OP-3 and OP-4.

The voltages V _{0 to} Vn ′ (n ′ at each node of the resistor string RA)
= 127) is expressed in the same manner as the equation (1) obtained by the resistor string R-P, and is a geometric series. The voltage ratio of the resistor string R-A across the output signals PEAK and V _BL of the peak hold circuit 12 is given to the, PEAK-V ₀ and V ₀ -V _BL is
Designed for 6: 4. That is, the shading waveform can be corrected by following the peak value up to 60%.

The decoder 133 receives the signal ADMODE0,1 from the register 73.
Output is determined, and as a result, the A / D / D / A conversion circuit 13 operates in the three modes shown in Table 2.

In the first and third modes, the transistor TrAA shown in FIG. 8 is on. As a result, the output OP4 of the operational amplifier OP-4
The reproduced shading waveform is output to -0.

In the second mode, the transistor TrAS turns on. In the fourth mode, the transistor TrAH is turned on, the input signals from the input terminals SLICE and HTONE are input to the operational amplifier OP4, and the impedance-converted signal is output to OP4-0. The signal of the output OP4-0 is input to the A / D conversion circuit 16.

The first and third modes have exactly the same movement in the A / D / D / A conversion circuit 13, but are different modes in the A / D conversion circuit 16.

FIG. 10 is an example of a circuit block of the differential modulation / demodulation circuit 14 and the RAM 15.

Reference numeral 141 is a differential modulation circuit, 142 is a differential demodulation circuit, and 143 is a bus switch.

When storing the shaded waveform in the timing chart of FIG. 3, the comparator COMPA of the A / D / D / A conversion circuit 13 is used.
The differential modulation circuit 141 is operated, the differential data is stored in the RAM 15 as a binary signal. The differential modulation circuit 141 is configured by using an up-down counter.
The data from the RAM 15 is received by the differential demodulation circuit 142 except when the shading waveform is stored, and a demodulation signal that approximates the differential value with a substantially straight line is generated.

The contents of the RAM 15 are passed through the bus switch 143, the system bus 93, the bus buffer 72, and the shading waveform registers SD0 to SD7 shown in the register name column of Table 8, respectively, and the μCPU8
Can be informed. Also, the shading waveform registers SD0 to S shown in the register name column of Table 8 from the μCPU8.
By writing to D7, it is possible to write the shading data to RAM15.

FIG. 11 is an example of a detailed circuit block of the A / D conversion circuit 16.

161 is a decoder, 162 is a binary encoder, 163 is 4-
8-bit conversion decoder, 164 selector, 165 dither pattern RAM, 166 decoder, 167 γ-correction MOS transistor group, 168 switching switch, OP5 operational amplifier, COMP
_AD0- n are comparators (n = 15 in this LSI), R-AD
1 and 2 are resistor strings. TrAD0 to _n are MOS transistors.

This A / D conversion circuit 16 is a comparator COM connected in parallel.
_Flash type A / D conversion is performed by PAD 0- _n . First, the range for A / D conversion is determined as follows. A / DD / A
The output OP40 of the operational amplifier OP4 of the conversion circuit 13 and the DC voltage V _DAL (usually V _DAL = V _BL ) from the outside are connected to the resistor string R-AD1.
Partial pressure with. The voltage division value is obtained by decoding the signals DAL0 to DAL3 from the register 73 by the decoder 166 and selecting one of the TrAD0 to _n , and becomes the output impedance-converted by the operational amplifier OP5.

The signals DAL0 to DAL3 of this LSI 10 are 4-bit binary signals. From the above, the reference voltage of the resistor string R-AD2 is the output OP40 of the operational amplifier OP4 and the output OP of the operational amplifier OP5.
Determined by 50.

Further, instead of linearly dividing the voltages of the outputs OP40 and OP50 of the operational amplifiers OP4 and OP5 and inputting them to the comparators COMPAD0 to _n , in order to obtain a better image quality, this LSI10 has eight kinds of γ correction (linear Can be included). The value of this γ correction can be selected by decoding the outputs γ CONT ₀ to _{2 of the} register 73 by the decoder 161 and controlling the γ correction MOS transistor group 167.

The outputs of the comparators COMPAD0- _n-1 are converted by the binary encoder 162 into 4-bit binary signals,
Further, the 4-8 bit conversion circuit 163 converts it into an 8 bit signal in which two 4 bits are arranged. This 8-bit signal is connected to the video bus 94.

Also output SLICE0 ~ 3 from register 73 and dither pattern
The switching switch 168 which selects the output of the RM 165 and supplies it to the selector 164 is controlled by the combination of the outputs ADMODE 0 and 1 of the register 73. This control corresponds to the mode shown in Table 2. Modes 1 and 2 output binary data, and modes 3 and 4 output dither signals. When outputting binary data, the selector 164 is driven by the 4-bit SLICE signal, and the comparator COMPAD
_One of the outputs of 0 to _n is binary data PDATA. To output dither, use μCP via system bus 93
The binary data PDATA sliced at the slice level according to the contents of the RAM 165 written from U8 can be output. The RAM 165 stores 4 bits of information (64 bits in total) in a 4 × 4 matrix. The image signal can be read with an arbitrary dither pattern according to the information input to the RAM 165.

FIG. 12 is an example of a detailed circuit block of the main scanning line density conversion circuit 21.

The linear density conversion command pulse generation circuit comprises an m / (m + 1) command generation circuit 211 and a (m-1) / m command generation circuit 212. 213
Is a selector, 214 is a linear density arithmetic circuit, 214A, 214B and 214C are shift registers, 215 is a selector, 216 and 217 are counters,
Reference numeral 218 is a selector, and 219 is a serial-parallel conversion circuit. ANDE is an AND gate.

From register 73, the binary signal m0, m whose value of m is 3 bits
As 1, m2, m / (m + 1) command generation circuit 211 and (m-1) /
It is given to the m command generation circuit 212. (M + of clock CCK synchronized with binary data PDATA generated in A / D conversion circuit 16
1) pulse every 1 time m / (m + 1) command generation circuit
It occurs at 211. Similarly, the (m-1) / m command generation circuit 212 generates a pulse once every m times of the clock signal CCK.
Now, assuming that _one pulse is repeated (m + 1) times N ₁ times and one pulse is repeated m ₂ times N ₂ times, (m + 1) N ₁ + mN ₂
(N ₁ + N ₂ ) pulses are generated during each clock pulse CCK. If the binary data PDATA at the time of generation of this pulse is reduced, the linear density conversion (reduction) represented by the following equation is performed.

Next, binary data PDAT synchronized with (N ₁ + N ₂ ) pulses generated during (m + 1) N ₁ + mN ₂ clock pulses CCK.
If only A is valid data, the reduction rate P ₂ is given by the following equation.

Conversely, (m + 1) N ₁ + mN occurs between ₂ clock pulses CCK (N ₁ + N ₂ occurs between pulse CCK (N ₁ + N
₂ ) Expansion is possible by increasing the bivalent data PDATA during the pulse generation period of 2 times. This enlargement factor Q is given by the following equation.

The value of N ₁ + N ₂ is given as a 4-bit binary signal of k ₀ to k ₃ of the register 73, and this is used as the load signal of the counter 217. The signals l _{0 to} l ₁₅ of the register 73 are input to the selector 218, for example, with N ₁ at high level and N ₂ at low level.

For example, when N ₁ = 4 and N ₂ = 5, “9” is given to k _{0 to} k ₃ as a binary signal. And for l ₀ to ₈ , l ₀ = 0, l ₁ = 1, l ₂ = 0,
l ₃ = 1, l ₄ = 0, l ₅ = 1, l ₆ = 0, l ₇ = 1, l ₈ = 0 (1: m / (m + 1) pulse at high level, 0: (m + 1) at low level / m
It is assumed that the pulse of is selected by the selector 213. )give. As a result, the signals l ₀ to l ₈ are repeatedly applied to the selector 213, and the output pulses of m / (m + 1) and (m + 1) / m are sequentially obtained as the TMSK signal.

From equations (2), (3) and (4) It is possible to reduce or expand the range of.

P ₁ and P ₂ are distinguished by the LDCM signal in register 73. P ₁
The relation between P ₂ and P ₂ is only that TMSK signals have opposite polarities.

The reduction operation circuit 214 and the register 214A according to the TMSK signal.
~ C executes reduction processing. 2 given in register 73
According to the bit signal LDL, the binary data PDATA is reduced while performing the calculation as shown in Table 3, and the reduction (linear density conversion) process is performed. The 2-bit signal LDL can be set to 4 from A to D, and the calculation can be sequentially switched.

The reduced data is converted into an 8-bit signal by the serial-parallel conversion circuit 219 and output to the video bus 94.

The enlargement factors Q ₁ and Q ₂ expressed by the equation (3) can be achieved by supplying the TMSK signal to the serial output circuit 26. However,
Binary data PDATA cannot be enlarged and output.
Expansion will be described later.

FIG. 13 is an example of a circuit block around the sub-scanning line density conversion circuit 24 and the video bus 94.

Reference numeral 240 is a sub-scanning line density calculation circuit, and 241A to C are 8-bit latch circuits, which constitute the sub-scanning line density conversion circuit 24. 94A is a video read bus, 94B is a video write bus, 941,944,945 are selectors, 942,943 are latch circuits, 94
6 is a bus switch.

The circuit of FIG. 13 operates in four modes as shown in Table 4 by the 2-bit signal of VMODE0,1 of the register 73.

In the first mode, the selectors 944 and 941 and the latch circuit 942 output the multivalued information of the A / D conversion circuit 16 and the output of the 4-8 conversion circuit 163 to the video read bus 94A. The multi-valued information is written in the memory 3 under the address signal from the address counter 22.

In the second mode, the binary data from the main scanning line density conversion circuit 21 is output to the video read bus 94A through the selector 944, the latch circuit 942, and the selector 941 and simultaneously latched as the current line data to the latch circuit 241C. . The output signal of the video read bus 94A is stored in the line memory 3. Then, the data of the previous line and the data of the previous two lines are read from the line memory 3, and the latch circuits 241B and 241A respectively
Latch on. The arithmetic circuit 240 simultaneously calculates binary data of 8 pixels. The arithmetic circuit 240 executes the three operations shown in Table 5 according to SSMODE0 and 1 of the register 73, and outputs the results to the latch circuit 943. The data of the latch circuit 943 is stored in the line before the line of the line memory 3. Latch circuit 24
The data on the line before the one latched to 1A is already in the arithmetic circuit.
As a result of being calculated by 240, this is output to the system bus 93 through the selector 945 and the bus switch 946. And μC
It can be read to the data bus 92 of PU8. This second
In this mode, the sensitivity of each pixel of the sensor cannot be corrected.

In the third mode, the distortion sensitivity of each pixel of the sensor is corrected, and the reduced data in the main scanning direction is output to the data bus 92 of the μCPU 8 through the main scanning line density conversion circuit 21. Binary data from the main scanning line density conversion circuit 21 is input to the selector 945 through the selector 944 and the latch circuit 942. The binary data is selected by the selector 945 and output to the system bus 93 by the bus switch 946. Then, the data is output to the data bus 92 of the μCPU8.

In the fourth mode, binary data that is not reduced by the main scanning line density conversion circuit 21 is selected by a selector 944, a latch circuit 942, and a selector 94.
1 to the video read bus 94A and the latch circuit 241C. Then, the data subjected to the sub-scanning line density calculation is output to the data bus 92 through the selector 945, the bus switch 946, and the bus buffer 72. At this time, the sensitivity of each pixel of the sensor can be corrected.

As described above, the third and fourth modes can operate only when the sensor is driven at a frequency of 1/4 with respect to the input clock signal CLK to the LSI 10. As will be described later, there are two ways to drive the sensor: 1/2 and 1/4 of the clock signal CLK.

The address counter 22 generates an address signal for the line memory 3 and the RAM 31.

FIG. 14 is an example of a detailed circuit block of the serial output circuit 26.

261 is an 8-bit parallel-in / serial-out shift register, 262 is a counter, and 263 and 264 are selectors.

First, as the serial output mode, the data read by the sensor is output as binary data that is synchronized with the sensor drive frequency as SDATA, and the μCPU8 data bus 9
There is a mode to output the data from 2 (usually the reception signal in the case of facsimile).

What distinguishes the above modes is the signal at the output R / T of the register 73. In the former mode, the binary data PDATA and the clock signal TCLK are input from the main scanning line density conversion circuit 21, pass through the selectors 264 and 263, and output as the data SDAT.
A and clock signal SCLK. The data SDATA at this time can output the data reduced in the main scanning line density conversion circuit 21, but cannot be expanded.

In the latter mode, shift registers from the system bus 93
The data written in 261 becomes the data output SDATA together with the clock signal SCLK synchronized with the external clock signal RCLKI. The selector 263 selects the clock signal RCLKI and outputs it to the counter 262. The counter 262 stops its operation when it receives the TMSK signal from the main scanning line density conversion circuit 21, and also stops the clock pulse SFCLK to the shift register 261. At this time, the output of the clock signal SCLK does not stop. By doing so, the same data can be output as the SDATA signal multiple times. This is the expanded data.
When the counter 262 is incremented and counted eight times, it means that all the contents of the 8-bit shift register 261 are output as the SDATA signal. Therefore, the data request signal DREQ for the μCPU8 is set. 8 when receiving DACK signal
The bit data is taken into the shift register 261 from the data bus 92 through the bus buffer 72, and at the same time the counter 2
62 is reset. The above operation is repeated by an external clock RCLKI. This operation is based on the so-called DMAC (Direct Memory Access Controller).

FIG. 15 is an example of a circuit block of the linear density determination circuit 25.

251B and 251C are parallel-in / serial-out shift registers, 252 is a change point detection circuit, 253 is a down pulse generation circuit, 254 is a counter, 256 is a decision number generation circuit, and 257 is a digital comparator.

The 8-bit parallel data from the latch circuits 241B and 241C of the sub scanning line density conversion circuit 24 are shift registers 251B and 251C.
Is converted into serial data. Shift register
The contents of 251C are the current line data, and the contents of the shift register 251B are the data of the previous line. A change point from white to black and a change from black to white existing between these two data is detected by the detection circuit 252, and the number thereof is counted by the counter 254. The above is for detecting the change point in the sub-scanning direction. When the output VR0 of the register 73 is set to "1", the shift register 251C
When VR1 is set to "1" before the previous line data of 1, the change point from white to black or black to white is detected in the data of the previous line of the shift register 251B and output to the counter 254.

The down clock signal DOWN is input to the counter 254. This is for distinguishing the number of change points due to small characters from the number of change points due to large characters. The down clock signal DOWN is the counter 25 over the entire line.
If you enter in 4, it will be impossible to distinguish between the change points when large characters are written on the paper and the change points when small characters are written on a part of the paper. In determining the line density, it is desirable that the former large character has a coarse linear density and the latter small character has a dense linear density.

The downclock signal DOWN is generated as shown in Table 6 by the signals LEAK0, 1, 2 from the register 73.

Further, according to the signals LDTH0 to 3 from the register 73, the decision number generating circuit 256 generates binary signals as shown in Table 7. This output signal and the output of the counter 254 are compared by the comparator 257, and when the output of the counter 254 increases, it is input to the register 73 as the signal LDD8. The μCPU 8 determines the linear density to be transmitted by reading this signal.

FIG. 16 is an example of a circuit block of the sensor I / F4. 41,4
4 is a divider that halves the cycle of the clock signal CLK, 42 is a selector, and 43 is a sensor timing generation circuit.

An input clock signal CLK from the outside of the processor 10 is divided into halves by the dividers 41 and 44. Signal SDRV from register 73
Accordingly, the selector 42 selects either CLK / 2 or CLK / 4 signal and inputs it to the sensor timing generation circuit 43. This input signal CCK is synchronized with the frequency of the image signal. SDR
The sensor drive frequency is divided into a high speed mode and a low speed mode according to the V signal. The high speed mode drives the sensor at twice the speed of the low speed mode.

The sensor timing generation circuit 43 includes a sensor start signal φ _TG , a clock signal φ _I , and a sensor reset signal φ for the sensor.
_R or sample hold circuit 11 in this processor 10
Sampling pulse φ _S and clamp pulse φ _C required for Sensor start signal φ _TG is external trigger signal TR
It is generated in synchronization with the longer pulse of either IG or the output signal SMSK of timer 5.

FIG. 17 is a detailed circuit block of the timer 5. 51 is a counter, 52-56 and 60 are digital comparators, 57-59
Is a flip-flop with set reset. counter
51 has 13 bits, and counts the clock signal CCK synchronized with the sensor pixel frequency output from the sensor I / F 4.
The counter 51 can count from the sensor start signal φ _TG to 8K pixels.

FIG. 18 is a time chart for explaining the operation of the timer 5 shown in FIG. The counter 51 operates in response to the clock signal CCK after the sensor start signal φ _TG is input, and normally generates the following signals.

First, when the output of the counter 51 becomes equal to the set value DMB0-5 from the register 73, which means the number of dummy bits of the sensor, a pulse is generated from the comparator 52 and the flip-flop 57 is set. This is the beginning of the SMSK signal. When the output of the counter 51 becomes equal to the set value TIME7 to 12 from the register 73, the flip-flop 57
Is reset and the SMSK signal ends. Input the SMSK signal to the sensor I / F 4 and generate the next sensor start signal φ _TG . However, the external trigger signal TRIG is set to low level.

Similarly, the VMSK signal is generated according to the set values VMST0 to 11 of the register 73. By the way, a signal to end this VMSK signal
TC is obtained as follows. Video address counter 22
Output and the set value of register 73 VMEND2 to 11 are compared.
A comparison is made at 60, and when both are equal, a TC signal is generated, and the flip-flop 58 is reset by this signal.

Exactly the same, the flip-flop 59 is driven according to the set values PAPWL5-12 and PAPWR5-12 to generate the signal PAPW.

As described above, the PAPW signal is input to the peak hold circuit 12, and the peak hold operation is performed only during the high level period.

The VMSK signal represents the effective portion of the image signal, and only the signal in the high level period is output to the system bus 93.

The rising edge of the SMSK signal is input to the A / D / D / A conversion circuit 13 and used to set the initial value. The end is input to the sensor I / F 4, and the sensor start signal φ _TG is generated in synchronization with the longer side than the TRIG signal.

The sequencer 6 generates a timing signal for each circuit block. The sequencer 6 is composed of a counter, a shift register, a gate circuit and the like.

The controller 71 of the μCPU I / F7 receives signals from the control bus 91 of the μCPU8, writes / reads data to / from the register 73, and generates interrupt signals to the μCPU8. Similar to Face. Also, in facsimile machines and the like, the driving cycle of the sensor and the actually required data are often not synchronized. For example, the drive synchronization with a pulse motor for paper feeding does not match the sensor drive cycle. for that reason,
When the data request signal SCAN is input from the outside of the processor 10, the controller 71 includes a control circuit that digitizes the image signal following the next sensor start signal and outputs it to the data bus 92 as information.

Table 8 summarizes the contents of the register 73 as described above.

The controller 71 has a 5-bit address counter for selecting the register 73, and the contents are written in or read from the register 73 according to the set value.

▲ ▼ is the chip select signal and μCP
Data can be exchanged between the U8 and this LSI. RS
Is a register select signal, which selects a Madres register at a low level and a command register at a high level.

The address register is selected when ▲ ▼ and RS are at low level. At this time, when the low level of the write command signal (R / W) is input to the controller 71, the address data of the data bus 92 is written in the address registers AR0 to AR4. Next, when RS is set to the high level, the command register at the address written in AR0-4 is selected. The write / read command signal (R / W) enables writing / reading of the contents to / from the command register.

In this processor, if the write command signal and write data are input in synchronization after inputting the general reset signal (RESET), the command register address will switch from "0" to "1D" in sequence, and all commands Data can be written to the register.

The contents of the command register will be described below.

Address "0" is the mode selection register. Table 2 for ADM0 and ADM1
Corresponding to ADMODE0,1 explained in step SSM0,1 is SSMODE in Table 5.
This corresponds to 0,1 and VM0,1 corresponds to VDMODE0,1 in Table 4. LML
The system (R that does not have the line memory 3 connected to the ESS
If you cannot add AM31), enter "1". In this case, the binarized (or dither signal is also possible) image information is output from the system bus 93, the system bus buffer 72 to the system bus 92, or is output from the serial output circuit 26 as serial data. At this time, it is possible to reduce the data in the main scanning direction.

R / T is a command signal indicating whether the processor operates in the reading mode (T) or the receiving mode (R).
It is used in the serial output circuit 26 in the figure.

The work enable register is stored in the address "1". MAGE executes enlargement with "1" with enlargement permission signal. REDE
Is a reduction permission signal, and reduction is executed by "1". INTE is μCP
It is an interrupt enable signal to U8. When it is "0", no interrupt signal is generated. DMAE is a data request signal (DREQ) enable signal in the DMA mode.

When PRCE becomes "1" by the operation enable signal of this processor, this processor starts its operation.

WCOM is a write command signal of a grading waveform to RAM15. When set to "1", write operation is executed only once.

VBST has not been explained in the text, but it has the following contents. This processor can transfer the information for one line stored in the line memory 3 to the outside in the burst mode. This is used when transferring data at the highest speed, and when VBST is set, the operation in this mode is executed.

AADJ is a register that permits execution of sensitivity correction of each pixel of the sensor.

Addresses "2" to "7" are set values related to the timer described in FIGS. 17 and 18.

VR0,1, LEAK0,1,2, LDTH1 to 4 at addresses "8" and "9" are 15th
The present invention relates to the linear density determination described in the figures, Tables 6 and 7. In addition, SMD0 to 2 relate to the sensor I / F4 described in Table 1,
SDRV is for setting the sensor drive frequency and is described in FIG.

Address "A" relates to the peak hold circuit 12 and has been described with reference to FIG.

DAL0-3, SLICE0-3, and .gamma.CONT at the addresses "B" and "C" are related to the A / D conversion circuit 16 and have been described in FIG.

ALLR0 and 1 are registers for sensitivity correction for each pixel of the sensor, which will be described later.

The addresses "D", "E", and "F" relate to the linear density conversion and are described in FIG.

Addresses "10" to "17" are halftone registers HS1 to HS16
As shown in FIG. 11, it is a register for setting a value in the dither pattern RAM 165, and an arbitrary pattern can be written.

LDLA to D at the address "18" are for setting the input signal to the selector 215 in FIG. 12 and determine the operation operation.

Addresses "19" and "1A" are registers for creating a TC signal indicating the end of the VMSK signal, which are described in FIG.

Address 1B is a register for calling and setting the peak value, which is described in FIG.

The address "1C" relates to the initial value of the seeding waveform, which is explained in FIG.

The "1D" address is for reading / writing the contents of RAM15 for storing the waveform waveform, and the contents of RAM15 of about 1.5K bits can be seen.

Next, the operation of sensitivity correction for each pixel of the sensor will be described.

When the operation is started by setting AADJ of the work enable register in Table 8, the RAM1 in the timing chart in FIG.
There is no change until the writing operation of the shielding waveform to 5. The sensitivity is corrected in synchronization with the input of the next image signal. FIG. 19 shows an example of the waveform at the time of sensitivity correction.
For the peak value PEAK of the image signal, A / D and D / A in Fig. 8
The output OP4-0 of the operational amplifier OP4 in the conversion circuit 13 becomes the envelope of the image signal. It cannot follow the sensitivity variation as shown in FIG.

When the OP4-0 signal is input to the A / D conversion circuit 16 shown in FIG. 11, the signal DAL0 to 3 from the register 73 causes the operational amplifier to operate.
The output OP5-0 of OP5 has a waveform as shown in FIG. The output signals OP4-0 and OP5-0 are set to OP4− by the γ correction switch 167.
As 0 side of the voltage step increases to the comparator COMPAD comparison voltage _{0 to n (in} this LSI n = 15). The voltage between the output signals OP4-0 and OP5-0 is not divided into n equal parts, but divided so as to be close to the equal comparison class. Output signal
The sensitivity variation of the image signal in the range of OP4-0 and OP5-0 is converted into the digital signal and the binary encoder
162,4-8 signal is converted by the decoder 163 from the video bus 94
It is stored in RAM31.

Next, the data read from the RAM 31 enters the latch circuit 27 through the video bus 94, and the latch circuit 27 outputs the data shown in FIG.
It is input to the adder circuit 131 in the A / D / D / A conversion circuit 13.
At this time, the signal from the RAM 31 is a binary signal. A digital signal corresponding to the output signal OP4-0 in FIG. 19 is obtained from the output of the counter 130, and the digital signal from the latch circuit 27 relating to the sensitivity variation is added to this by the adder circuit 131. As a result, the image signal having the sensitivity variation shown in FIG. 19 is reproduced as the output signal OP4-0. If the image signal is converted into a digital signal by the A / D conversion circuit 16 based on this signal, a digital signal in which sensitivity variations are corrected can be obtained.

The operation by ALLR0,1 at address "C" of the command register is as follows.

By setting DAL0-3 shown in FIG. 11,
The output value of OP5-0 can be selected. That is, the range in which the sensitivity can be corrected can be changed. When changing this range, the original image signal cannot be reproduced unless the value of the input to the adder circuit 131 in FIG. 8 is changed. In the present processor 10, the range can be changed to three states by changing the digit from the latch circuit 27 of the adder circuit 132. If the smallest range is "1",
You can select the range of "2", "4" times.

By making the PEAK value in FIG. 19 larger than the peak value of the image signal (input to the input PEAKI by an external circuit), it is possible to correct the sensitivity protruding above the envelope OP4-0 in FIG. .

As described above, according to the present embodiment, the minimum necessary part in the image signal processor is a 1-chip LSI except for the relatively large capacity parts such as the externally connected control device, the line memory, and the main RAM. And, since the change of the function can be achieved only by changing the value of the register inside the interface, even if there is a difference in the product or model, the hardware can be shared,
The cost can be reduced and the size can be reduced.

Further, even when the image signal processor of the present embodiment is used in a facsimile, (1) image transmission when the size of a transmission original is different from the size of a received recording.

(2) Image transmission when the transmitted original reading pitch (linear density) and the received recording pitch are different.

(3) Image reading when the document transmission start position is different from the sensor position.

(4) Image reading when a sensor having different control signals and clock waveforms for photoelectric conversion is used.

(5) Image reading in the case of using a sensor in which the size of the image signal after photoelectric conversion and the output format are different.

(6) Image reading when distortion correction in 1-bit units is required.

Each operation such as can be achieved simply by changing the value of the register inside the interface.

Further, this processor can be applied to various devices having an optical reading function as well as the reading operation for facsimile described above. The effect of applying this processor will be briefly described below.

(1) Intelligent Copy Machine By using the linear density conversion circuit of the present processor, it is possible to easily realize enlargement / reduction hardware of arbitrary magnification. In addition, since the data processed by this processor can be managed by the microprocessor, by writing the symbols and frames specified in the drawings, it is possible to realize a device for advanced editing operations by changing only the software. There is a merit.

(2) OCR Conventionally, OCR used many high-speed processors to improve the recognition rate. Also, OCR is different from Huaximiri,
It also has the function of changing the binarization level and retrying for unreadable characters. By using this processor even for these high-grade reading operations,
In addition to changing the binarization level, the linear density is automatically determined, and the operation of reading only the desired portion in detail can be easily realized.

(3) Hand scan scanner This processor is aimed at LSI, and it is fully necessary for the device such as hand scan scanner that is desired to be small, lightweight, low power consumption and low cost. It can be dealt with.

As described above, the processor of the present invention can be applied to a wide range of applications other than the facsimile.

〔The invention's effect〕

According to the image signal processing processor of the present invention, the minimum necessary portion of the image signal processing processor is configured by a one-chip LSI, except for the components that occupy a relatively large capacity, and the change of the function is performed by the interface. Since it is configured so that it can be achieved only by changing the value of the register inside the, even if there are differences in the products and models to which it is applied, it is possible to standardize the hardware, and with that, the image There is an effect that the product cost of the signal processor can be reduced, and a downsized image signal processor can be obtained, and further, the reliability of the product can be increased.

[Brief description of drawings]

Fig. 1 is a schematic block diagram of the processor, Fig. 2 is a detailed block diagram of the processor, Fig. 3 is a timing chart, Fig. 4 is a circuit diagram of a sample hold unit, and Fig. 5 (1) and (2) are Timing chart, Fig. 6 is a block diagram of the peak hold unit, Fig. 7 is a timing chart, Fig. 8 is a block diagram of the A / D / D / A conversion unit, Fig. 9 is a timing chart, and Fig. 10 is a modulation / demodulation unit. Block diagram of part, No.
Figure 11 is a block diagram of the A / D converter, Figures 12 and 13 are block diagrams of the linear density converter, and Figure 14 is a block diagram of the output section.
Fig. 15 is a block diagram of the linear density determination unit, and Fig. 16 is the sensor I /
Block diagram of F, Fig. 17 is a block diagram of the timer section, 18
The figure is a timing chart, and FIG. 19 is an input / output waveform diagram. 1 ... Analog signal processing unit, 2 ... Digital signal processing unit, 4 ... Sensor I / F unit, 5 ... Timer unit, 6 ... Sequencer unit, 7 ... μCPU I / F unit, 10 ... Signal processing Processor SLI, 71 …… Controller, 73 …… Register.

Front page continuation (72) Keisuke Nakajima 3-1-1, Saiwaicho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Nagaharu Hamada 3-1-1, Saiwaicho, Hitachi City, Ibaraki Prefecture No. Stock Company Hitachi, Ltd.Hitachi Research Laboratory (72) Inventor Noboru Suemori 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Ltd. Totsuka Plant (72) Inventor Taka Kubo 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address within Hitsuritsu Communication System Co., Ltd. (56) Reference JP 58-172062 (JP, A) JP 57-119561 (JP, A) JP 58-177063 (JP, A) JP 58 -21970 (JP, A) Yasuhiko Yasuda "Basics and Applications of New Edition Facsimile" 2nd edition (Sho 58-8-25) IEICE P. 292-296

Claims (4)

[Claims] 1. An image signal processor comprising a one-chip LSI, which corrects distortion of an analog signal input from a sensor,
An analog signal processing unit for outputting as a digital signal, a digital signal processing unit for converting each of the main and sub-scanning line densities of the digital signal into a specified scanning line density, a sensor driving unit for driving a sensor, and each of the units. A timer and a sequencer for setting operation timing, and an interface coupled to an externally connected control device via a data bus and a control bus, respectively,
Further, the interface is based on an operation mode in the LSI, a register in which various commands or various parameter values are set corresponding to an address, and the operation mode based on address data supplied from the externally connected control device. Alternatively, it is provided with a controller that writes various commands or various parameter values to the register, and a bus buffer that supplies an output digital signal from the digital signal processing unit to the externally connected control device. Image signal processing processor. 2. Registers in the interface are:
The image signal processor according to claim 1, comprising an address register and a mode register, a command register, and a parameter register selected according to the address of the address register. 3. The analog signal processing section, a peak hold circuit for peak-holding an input analog signal, analog-digital (A / D) conversion of the input analog signal using the peak-held value as a reference signal, and Distortion correction by differential modulation / demodulation of the A / D / D / A conversion circuit that performs digital-analog (D / A) conversion of the distortion-corrected digital signal and the output digital signal of the A / D / D / A conversion circuit Differential modulation / demodulation circuit and memory (RA
M) and an A / D conversion circuit that performs analog-digital (A / D) conversion of an input analog signal using the distortion-corrected digital signal as a reference signal. Image signal processor. 4. The main and sub-scanning line density conversion circuit, wherein the digital signal processing unit performs density conversion of each main scanning line and sub-scanning line in accordance with an instruction of a register in the interface, and the main and sub-scanning lines. A line bus having a video bus coupled to the density conversion circuit, a latch circuit coupled to the video bus, and an externally connected line memory and RAM connectable to the video bus via a bus buffer. The binary data for several lines which have been subjected to the scanning line density conversion by the main scanning line density conversion circuit, and the RAM
The image signal processing processor according to claim 1, wherein each of the digital signal processing means stores at least digital data indicating a variation in sensor sensitivity in the analog input signal.