JPH073872B2 - Method of manufacturing semiconductor device using thin film transistor - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device using a thin film transistor (hereinafter referred to as TFT), and more particularly, to improving the yield of TFT and stabilizing the manufacturing process. The present invention relates to a method for manufacturing a semiconductor device using a TFT intended for simplification and the like.

The TFT adopted in the present invention is applied to, for example, a switching transistor of an active liquid crystal display element, a transfer transistor in a photo sensor of an image reading apparatus such as a facsimile, and the like.

[Prior Art] A conventional TFT has been manufactured by the following manufacturing method.

FIGS. 6A to 6C are vertical cross-sectional views showing a schematic manufacturing process of a conventional TFT.

First, as shown in FIG. 6 (A), a gate electrode 2 is formed on an insulating substrate 1 such as glass, and an insulating layer 3 and a semiconductor layer 4 are sequentially deposited on the gate electrode 2. Since the thin film deposition method for each of these layers is simple in process and advantageous in performance,
It is often performed continuously using a plasma CVD method. In order to make good contact between the semiconductor layer 4 and a source electrode 5 and a drain electrode 6 described later, it is often performed to provide an impurity semiconductor layer to which an impurity such as phosphorus is added on the semiconductor layer 4.

Next, as shown in FIG. 6 (B), the semiconductor layer is selectively left in the part where the channel of the TFT is formed, and the other part is removed by etching. The remaining semiconductor layer region is
As shown in Japanese Patent Laid-Open No. 59-9941, the upper and lower wirings are often extended to a portion where the upper and lower wirings are routed in order to reduce short circuits between the upper and lower wirings.

Next, as shown in FIG. 6C, the source electrode 5 and the drain electrode 6 are formed, and then a part of the insulating layer 3 is removed to expose a part of the gate electrode 2.

[Problems to be Solved by the Invention] In the above-described method for manufacturing a TFT, in the step of selectively leaving the semiconductor layer 4, selective etching that leaves the semiconductor layer 4 and leaves the insulating layer 3 is required.

However, the selective etching of the semiconductor layer and the insulating layer deposited by the plasma CVD method or the like has almost no selectivity, and the determination of the end point of the etching is not clear, so it is difficult to control the thickness of the insulating layer to be left. In addition, there is a problem that etching often progresses greatly to the insulating layer.

In addition, the above-mentioned selectively left semiconductor layer 4 and the source electrode 5 and the drain electrode 6 formed on the semiconductor layer 4 are required to have high accuracy in alignment and dimensions. Due to an alignment error in the photolithography process, the position and size of the pattern overlapping are likely to be displaced, and the position of the source electrode 5 or the drain electrode 6 often deviates from the selectively left semiconductor layer 4 and the electrode However, there is a problem in that the portion drops from the stepped portion of the semiconductor layer 4 toward the insulating layer to cause disconnection of the wiring, which lowers the reliability of the wiring and eventually the yield of the TFT.

Therefore, also in a semiconductor device using such a TFT and a capacitor, similarly, high precision is required in the manufacturing process,
There is a problem that it is difficult to improve reliability and yield is reduced.

[Means for Solving the Problems] The problems described above include the step of forming a control electrode of a thin film transistor and a lower electrode of a capacitor on an insulating substrate, and a first insulating layer on the control electrode and the lower electrode. A step of sequentially laminating a semiconductor layer and a second insulating layer, and a step of forming an opening in the second insulating layer, and forming a main electrode of the thin film transistor and an upper layer electrode of the capacitor through the opening. And a step of patterning the first insulating layer, the semiconductor layer, and the second insulating layer after the formation of the main electrode and the upper electrode, and the thin film transistor and the capacitor are simultaneously formed by these steps. This is solved by a method for manufacturing a semiconductor device using a thin film transistor, which is characterized by the above.

[Action]

In the method for manufacturing a semiconductor device using the TFT of the present invention, by patterning the first insulating layer, the semiconductor layer and the second insulating layer after the formation of the main electrode of the TFT and the upper electrode of the capacitor, the semiconductor The selective etching of removing the layer except a part and leaving the insulating layer can be eliminated, and an unstable manufacturing process can be eliminated. In addition, since the number of fixings that require highly precise pattern alignment is reduced, the manufacturing process is simplified and the wiring reliability, that is, TFT
The yield can be improved. Needless to say, etching that removes the second insulating layer and leaves the semiconductor layer can be easily performed.

Further, in the method for manufacturing a semiconductor device of the present invention, since the thin film transistor and the capacitor can be formed simultaneously in the same process, the thin film transistor and the capacitor can be stably formed without damaging or contaminating the semiconductor layer.

Further, since the step of removing the first insulating layer, the semiconductor layer, and the second insulating layer at the same time is a step which also serves to expose a part of the control electrode, in the conventional TFT manufacturing method, The number of steps can be reduced by eliminating the etching step which was added to expose a part of the electrode.

Examples and Reference Examples Hereinafter, examples and reference examples of the present invention will be described in detail with reference to the drawings. In the following examples and reference examples,
The same members as those in the figure are designated by the same reference numerals.

1 (A) to 1 (E) are longitudinal sectional views showing a reference example of a schematic manufacturing process of a TFT used in the present invention.

First, as shown in FIG. 1A, a gate electrode 2 serving as a control electrode is formed on an insulating substrate 1. A first insulating layer 3 made of silicon nitride, silicon oxide or the like is formed on the gate electrode 2 and the insulating substrate 1, and a semiconductor layer 4 made of polycrystalline silicon, amorphous silicon or the like is formed thereon, and further silicon nitride is formed. , A second insulating layer 8 for insulating and protecting silicon oxide or the like is continuously laminated by a film forming apparatus.

Next, as shown in FIG. 1B, the semiconductor layer 4 is provided with an opening for connecting to a source electrode and a drain electrode described later.

Next, as shown in FIG. 1C, the semiconductor layer 4 and the source electrode and the drain electrode are in ohmic contact.
For example, the impurity semiconductor layer 7 doped with an element such as phosphorus
Is formed, and a conductive layer for an electrode is further deposited.

Next, as shown in FIG. 1D, the conductive layer is etched to form the source electrode 5 and the drain electrode 6 which are main electrodes. Further, the unnecessary impurity semiconductor layer 7 is removed by using the source electrode 5 and the drain electrode 6 as a mask.

Next, as shown in FIG. 1 (E), the first insulating layer 3, the semiconductor layer 4, and the second insulating layer 8 are simultaneously patterned in the same pattern to form a TFT.

In this reference example, the selective etching of the semiconductor layer and the insulating layer, which was performed in the conventional example, is not necessary, and there is no instability associated with the selective etching, and the manufacturing process is stable.

Further, after the source electrode and the drain electrode are formed, the first insulating layer, the semiconductor layer, and the second insulating layer are simultaneously removed in the same pattern. Therefore, the source electrode and the drain electrode and the first insulating layer, the semiconductor layer, and the first insulating layer are removed. Even if the pattern with the second insulating layer is misaligned, the phenomenon that the source electrode and the drain electrode fall from the step portion does not occur, the highly accurate pattern alignment is reduced, and the manufacturing process is simplified.
In addition, the reliability of wiring, that is, the yield of TFT can be improved. Further, in this reference example, since the surface of the portion corresponding to the channel of the TFT is covered with the second insulating layer from the beginning of the process, it is not affected by various damages and contaminations during the process, The great advantage is that stable transistor characteristics can always be obtained.

FIGS. 2A to 2D are vertical cross-sectional views showing an example of a schematic manufacturing process when the TFT used in the present invention is used in an active liquid crystal display element.

First, as shown in FIG. 2A, the gate electrode 2 and the pixel electrode 9 are formed on the insulating substrate 1. Next, the first insulating layer 3, the semiconductor layer 4, and the second insulating layer 8 for insulation and protection.
Are laminated.

Next, as shown in FIG. 2B, an opening portion for connecting the source electrode and the drain electrode to the semiconductor layer 3 and an opening portion for connecting the drain electrode to the pixel electrode 9 are provided.

Next, as shown in FIG. 2C, the impurity semiconductor layer 7 and the electrode conductive layer are deposited, and the conductive layer is patterned in the same manner as in the step of FIG. 1D described above. ,
The source electrode 5 and the drain electrode 6 are formed, and the unnecessary impurity semiconductor layer is removed. In the case where the driving circuit portion of the liquid crystal display element has a matrix wiring, an opening portion can be similarly provided at this time to form the electrode wiring.

The order of the step of providing the opening and the step of depositing the impurity semiconductor shown in FIGS. 2 (B) and 2 (C) can be interchanged, so that the connection portion between the pixel electrode and the drain electrode can be changed. A structure in which the impurity semiconductor layer is not left is also possible.

Next, as shown in FIG. 2 (D), the first insulating layer 3, the semiconductor layer 4, and the second insulating layer 8 were simultaneously patterned in the same pattern to be applied to an active liquid crystal display device. TFT is formed.

This example has the following advantages in addition to the advantages described in the reference example shown in FIG. Note that FIG. 3 is a vertical cross-sectional view of a conventional TFT used for an active liquid crystal display device.

As shown in FIG. 3, conventionally, the insulating layer 3 is present on the pixel electrode 9, but in the present embodiment shown in FIG. 2D, the insulating layer is almost present on the pixel electrode 9. Therefore, the voltage for driving the liquid crystal can be reduced, and the load on the drive circuit power supply can be reduced.

4 (A) to 4 (D) are vertical sectional views showing an embodiment of a schematic manufacturing process when the TFT adopted in the present invention is used for a transfer element of a photo sensor of an image reading apparatus such as a facsimile. Is.

First, as shown in FIG. 4 (A), a TFT is formed on the insulating substrate 1.
The gate electrode 2 and the lower electrode 10 of the image signal storage capacitor are formed. Although not shown, a control electrode may be provided below the photo sensor at this time. Next, the insulating layer 3, the photoconductive semiconductor layer 4a, and the second insulating layer 8 are laminated.

Next, as shown in FIG. 4 (B), an opening for connecting the source electrode and the drain electrode of the TFT and an opening for connecting the upper electrode of the storage capacitor are formed on the photoconductive semiconductor layer 4a. And an opening for connecting the upper part of the photo sensor. The opening for connecting the upper electrode of the storage capacitor may not be provided.

Next, as shown in FIG. 4C, an impurity semiconductor layer and a conductive layer for an electrode are deposited, and the conductive layer is patterned in the same manner as the step of FIG. 1D described above. ,
Power supply line 11, sensor individual electrode 12, storage capacitor upper layer electrode 13, TFT source electrode 5, drain electrode 6, signal extraction line 14, and wiring for connecting each are formed, and unnecessary impurity semiconductor layers are removed. To do.

Next, as shown in FIG. 4 (D), the first insulating layer 3, the photoconductive semiconductor layer 4, and the second insulating layer 8 are patterned at the same time at the same time to form a photo-resistor having a transfer TFT. A sensor is formed.

This embodiment has the following advantages as compared with the conventional photo sensor. Fig. 5 shows the conventional transfer
It is a longitudinal cross-sectional view of a photo sensor having a TFT.

As in the reference example shown in FIG. 1, selective etching of the semiconductor layer and the insulating layer is not necessary, there is no instability associated with selective etching, and a stable manufacturing process is achieved, and a source electrode and a drain electrode are formed. After that, the first insulating layer, the semiconductor layer and the second insulating layer are simultaneously removed in the same pattern, so that the source electrode, the drain electrode and the first insulating layer,
Even if the patterns of the semiconductor layer and the second insulating layer are misaligned, the phenomenon that the source electrode and the drain electrode do not fall from the step portion does not occur, and highly accurate pattern alignment becomes unnecessary, which simplifies the manufacturing process. And the reliability of wiring, that is, the yield can be improved.

In addition, since the surface of the part corresponding to the channel of the TFT is covered with the protective layer from the beginning of the process, it is not affected by various damages and contamination during the process, and the transistor characteristics and sensor are always stable. There is a great advantage that the characteristics can be obtained.

[Effects of the Invention] As described in detail above, according to the method for manufacturing a semiconductor device using the TFT of the present invention, after forming the main electrode and the upper electrode of the capacitor, the first insulating layer, the semiconductor layer, and the The patterning of the second insulating layer eliminates the need for an unstable process of selective etching of the semiconductor layer and the insulating layer, and also reduces the number of highly precise processes such as alignment required, thus stabilizing the manufacturing process. It can be simplified and simplified, and the manufacturing yield can be significantly improved. Furthermore, stable and good transistor characteristics can be obtained without damaging or contaminating the semiconductor layer.

Further, in the method for manufacturing a semiconductor device of the present invention, since the thin film transistor and the capacitor can be simultaneously formed in the same process, it is possible to obtain an effect that the thin film transistor and the capacitor can be stably formed without damaging or contaminating the semiconductor layer. To be

[Brief description of drawings]

1 (A) to 1 (E) are longitudinal sectional views showing a reference example of a schematic manufacturing process of a TFT used in the present invention. 2 (A) to 2 (D) are vertical sectional views showing an example of a schematic manufacturing process when the TFT used in the present invention is used in an active liquid crystal display device. Figure 3 shows a conventional TFT used in an active liquid crystal display device.
FIG. 4 (A) to 4 (D) are vertical sectional views showing an embodiment of a schematic manufacturing process when the TFT adopted in the present invention is used for a transfer element of a photo sensor of an image reading apparatus such as a facsimile. Is. FIG. 5 is a vertical sectional view of a conventional photosensor having a transfer TFT. FIGS. 6A to 6C are vertical cross-sectional views showing a schematic manufacturing process of a conventional TFT. 1 ... Insulating substrate 2 ... Gate electrode 3 ... First insulating layer 4 ... Semiconductor layer 5 ... Source electrode 6 ... Drain electrode 7 ... Impurity semiconductor layer 8 ... Second insulating layer 10 ... Capacitor lower layer electrode 13 …… Capacitor upper layer electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-57-30882 (JP, A) JP-A-61-51972 (JP, A) JP-A-61-90193 (JP, A)

Claims (1)

[Claims] 1. A step of forming a control electrode of a thin film transistor and a lower electrode of a capacitor on an insulating substrate, and a step of forming a first insulating layer, a semiconductor layer and a second insulating layer on the control electrode and the lower electrode. A step of laminating in sequence, a step of forming an opening in the second insulating layer and forming a main electrode of the thin film transistor and an upper layer electrode of the capacitor through the opening, and after forming the main electrode and the upper layer electrode A semiconductor device using a thin film transistor, comprising a step of patterning the first insulating layer, the semiconductor layer, and the second insulating layer, wherein a thin film transistor and a capacitor are simultaneously formed by these steps. Manufacturing method.