JPH073940B2 - Arbiter circuit - Google Patents
Arbiter circuitInfo
- Publication number
- JPH073940B2 JPH073940B2 JP62292831A JP29283187A JPH073940B2 JP H073940 B2 JPH073940 B2 JP H073940B2 JP 62292831 A JP62292831 A JP 62292831A JP 29283187 A JP29283187 A JP 29283187A JP H073940 B2 JPH073940 B2 JP H073940B2
- Authority
- JP
- Japan
- Prior art keywords
- req
- input
- arbiter circuit
- gate
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Electronic Switches (AREA)
- Multi Processors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、非同期的に発生する複数の要求の競合を裁
定するアービタ回路に関するものである。Description: TECHNICAL FIELD The present invention relates to an arbiter circuit that arbitrates contention of a plurality of requests that occur asynchronously.
互いに非同期的に動作する複数のデジタルサブシステム
（例えば、マルチプロセッサシステム）が一つの資源
（例えば、ディスク装置）を共有する場合、サブシステ
ムからの共有資源使用要求は時間的にランダムに発生す
るので、この競合を裁定する必要がある。例えば、ある
サブシステムから共有資源使用要求があった時、共有資
源が他のサブシステムによって既に使用中であれば、使
用終了までその要求を待機させておく処理が必要であ
る。このような競合裁定処理を行うのがアービタ回路で
ある。When a plurality of digital subsystems (for example, a multiprocessor system) that operate asynchronously with each other share one resource (for example, a disk device), shared resource use requests from the subsystems occur randomly in time. , This conflict needs to be arbitrated. For example, when a shared resource use request is issued from a certain subsystem, if the shared resource is already in use by another subsystem, it is necessary to wait for the request until the use ends. The arbiter circuit performs such a competitive arbitration process.
第４図は、例えば、「ISCC85、ダイジェスト オブ テ
クニカル ペーバーズ（P45）（ISCC85 DIGEST OF T
ECHNICAL PAPERS（P45））」に示された従来のアービ
タ回路である。信号REQ−Ａ及びREQ−Ｂは、それぞれサ
ブシステムからの要求を表わす信号であり、信号▲
▼及び▲▼はそれぞれ要求信号REQ−
Ａ及びREQ−Ｂの要求を承認したことを表わす信号であ
る。1aは要求信号REQ−Ａと承認信号▲▼を
入力とし、承認信号▲▼を出力とするNANDゲ
ート、1bは要求信号REQ−Ｂと承認信号▲▼
を入力とし、承認信号▲▼を出力とするNAND
ゲートである、NANDゲート1a,1bはRSフリップフロップ
を構成している。Fig. 4 shows, for example, "ISCC85, Digest of Technical Pavers (P45) (ISCC85 DIGEST OF T
It is a conventional arbiter circuit shown in "ECHNICAL PAPERS (P45)". Signals REQ-A and REQ-B are signals representing requests from subsystems, respectively.
▼ and ▲ ▼ are request signals REQ-
This is a signal indicating that the A and REQ-B requests have been approved. 1a is a NAND gate that inputs the request signal REQ-A and the approval signal ▲ ▼ and outputs the approval signal ▲ ▼, and 1b is the request signal REQ-B and the approval signal ▲ ▼.
NAND that receives as input and outputs approval signal ▲ ▼
The NAND gates 1a and 1b, which are gates, form an RS flip-flop.
次に第４図に示す回路の動作を第５図を参照して説明す
る。REQ−Ａ及びREQ−Ｂには第５図に示す波形が入力さ
れる。▲▼及び▲▼はその時の出
力である。Next, the operation of the circuit shown in FIG. 4 will be described with reference to FIG. The waveforms shown in FIG. 5 are input to REQ-A and REQ-B. ▲ ▼ and ▲ ▼ are outputs at that time.
要求信号REQ−A,REQ−Ｂからの要求がない時、つまり両
信号が“L"の時、NANDゲート1aの一方の入力REQ−Ａは
“L"であるから、出力▲▼は他方の入力の状
態にかかわらず“H"となり、同様にNANDゲート1bの出力
▲▼も“H"となる。承認信号▲
▼，▲▼はロウアクティブの信号であるか
ら、共に“H"であることは、承認していないことを意味
する（時刻t0）。When there is no request from the request signals REQ-A and REQ-B, that is, when both signals are "L", one input REQ-A of the NAND gate 1a is "L", so the output ▲ ▼ is the other. Regardless of the input state, it becomes "H", and similarly the output ▲ ▼ of the NAND gate 1b also becomes "H". Approval signal ▲
Since ▼ and ▲ ▼ are low active signals, both being “H” means that they are not approved (time t 0 ).
要求信号REQ−Ｂが“H"となって要求を行ない、要求信
号REQ−Ｂが“L"で要求を行なっていないとき、NANDゲ
ート1bの出力▲▼は“H"となって承認を行な
わず、NANDゲート1aの出力▲▼は“L"となっ
て要求を承認する（時刻t1）。When the request signal REQ-B is "H" and the request is made, and when the request signal REQ-B is "L" and the request is not made, the output ▲ ▼ of the NAND gate 1b becomes "H" and the approval is made. not, the output of NAND gate 1a ▲ ▼ to approve the request becomes "L" (time t 1).
反対に要求信号REQ−Ａが“L"となって要求を行なわ
ず、要求信号REQ−Ｂが“H"となって要求を行なってい
るとき、NANDゲート1aの出力▲▼は“H"とな
って承認を行なわず、NANDゲート1bの出力▲
▼は“L"となって要求を承認する（時刻t2）。On the contrary, when the request signal REQ-A is "L" and the request is not made and the request signal REQ-B is "H" and the request is made, the output ▲ ▼ of the NAND gate 1a is "H". Without approval, the output of NAND gate 1b ▲
▼ becomes “L” to approve the request (time t 2 ).
要求信号REQ−Ａが“H"、REQ−Ｂが“L"となり、それに
応じて承認信号▲▼が“L"、▲▼
が“H"となった（時刻t3）後に、要求信号REQ−Ｂも要
求を行なってREQ−A,REQ−Ｂが共に“H"となっても、NA
NDゲート1aの出力▲▼は“L"のままであり、
NANDゲート1bの出力▲▼は“H"のままであ
り、要求信号REQ−Ｂの要求は承認されない（時刻
t4）。その後、要求信号REQ−Ａの要求が終了してREQ−
Ａが“L"、REQ−Ｂが“H"となると、NANDゲート1aの出
力▲▼は“H"となって承認を終了し、NANDゲ
ート1bの出力▲▼は“L"となり要求信号REQ
−Ｂの要求が承認される（時刻t5）。The request signal REQ-A becomes "H" and the REQ-B becomes "L", and accordingly the approval signal ▲ ▼ becomes "L", ▲ ▼.
After There was a "H" (time t 3), the request signal REQ-B be the requesting REQ-A, even if that the REQ-B both "H", NA
The output ▲ ▼ of the ND gate 1a remains "L",
The output ▲ ▼ of the NAND gate 1b remains "H", and the request of the request signal REQ-B is not approved (time
t 4 ). After that, the request of the request signal REQ-A is completed and REQ-
When A becomes "L" and REQ-B becomes "H", the output ▲ ▼ of the NAND gate 1a becomes "H" and the approval is completed, and the output ▲ ▼ of the NAND gate 1b becomes "L" and the request signal REQ
-B's request is approved (time t 5 ).
上記のような従来のアービタ回路において、要求信号RE
Q−A,REQ−Ｂの要求が同時に起こって共に“L"から“H"
に変化したときのことを考える（第５図、時刻t6）。変
化の前、つまりREQ−A,REQ−Ｂが共に“L"であったとき
は、▲▼，▲▼は共に“H"であっ
た。従って、NANDゲート1aの出力▲▼は、RE
Q−Ａが“H"で、▲▼も“H"であることか
ら、“L"になろうとする。同様にNANDゲート1bの出力▲
▼も“L"になろうとする。一方、REQ−A,REQ
−Ｂが共に“H"の場合、RSフリップフロップの性質より
▲▼と▲▼は互いに反転した値を
とろうとする。ゆえに、共に“H"から“L"へ変化しよう
とする▲▼，▲▼は同時に相手を
“L"から“H"に変えようとする。このことにより、承認
信号▲▼，▲▼は共に“H"でも
“L"でもない中間電位になってしまい、競合裁定の処理
が行えなくなる可能性が生じるという問題点があった。In the conventional arbiter circuit as described above, the request signal RE
Q-A and REQ-B requests occur at the same time, and both are "L" to "H".
Consider the change to (at time t 6 in Fig. 5). Before the change, that is, when both REQ-A and REQ-B were "L", both ▲ ▼ and ▲ ▼ were "H". Therefore, the output ▲ ▼ of NAND gate 1a is
Since Q-A is "H" and ▲ ▼ is also "H", it tries to become "L". Similarly, output of NAND gate 1b
▼ also tries to become “L”. On the other hand, REQ-A, REQ
When both −B are “H”, due to the nature of the RS flip-flop, ▲ ▼ and ▲ ▼ try to take mutually inverted values. Therefore, both ▲ ▼ and ▲ ▼ who try to change from "H" to "L" try to change their partner from "L" to "H" at the same time. As a result, the approval signals ▲ ▼ and ▲ ▼ both have an intermediate potential that is neither “H” nor “L”, and there is a possibility that the competitive arbitration process cannot be performed.
この発明は上記のような問題点を解消するためになされ
たもので、第１及び第２の要求信号が同時に活性化して
も競合裁定の処理を行うことがてできるアービタ回路を
得ることを目的とする。The present invention has been made to solve the above problems, and an object thereof is to obtain an arbiter circuit capable of performing a competitive arbitration process even when the first and second request signals are simultaneously activated. And
この発明に係るアービタ回路は、フリップフロップの２
つの出力が中間電位になった場合に、これを検出し、一
方の出力ノードを強制的に“H"又は“L"にして第1,第２
の承認信号を得るようにしたものである。The arbiter circuit according to the present invention includes a flip-flop circuit 2
When two outputs have an intermediate potential, this is detected and one of the output nodes is forcibly set to "H" or "L".
The approval signal of is obtained.
この発明においては、フリップフロップの２つの出力が
共に中間電位になった時には、いずれか一方の出力ノー
ドが強制的に“L"又は“H"になるので、フリップフロッ
プからの承認信号を正しく出力することができる。According to the present invention, when the two outputs of the flip-flops are both at the intermediate potential, one of the output nodes is forcibly set to "L" or "H", so that the approval signal from the flip-flop is correctly output. can do.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図はこの発明の第１の実施例によるアービタ回路を
示し、図において、1a,1bはRSフリップフロップを構成
するNANDゲートであり、NANDゲート1aはREQ−ＡとNAND
ゲート1bの出力を入力とし、NANDゲート1bはREQ−ＢとN
ANDゲート1aの出力を入力としている。２はNANDゲート1
a,1bの出力を入力とするNORゲート、３はNANDゲート1b
の出力を接地電位にするためのスイッチング素子、4a,4
bは遅延回路である。FIG. 1 shows an arbiter circuit according to a first embodiment of the present invention. In the figure, 1a and 1b are NAND gates forming an RS flip-flop, and a NAND gate 1a is a REQ-A and a NAND.
The output of the gate 1b is used as an input, and the NAND gate 1b uses REQ-B and N
The output of the AND gate 1a is input. 2 is NAND gate 1
NOR gate 3 that receives the outputs of a and 1b is NAND gate 1b
Switching element to set the output of the to the ground potential, 4a, 4
b is a delay circuit.
次に動作について説明する。Next, the operation will be described.
要求信号REQ−ＡとREQ−Ｂが同時に発生されない場合
は、従来技術の説明で示したように、NANDゲート1a,1b
によって構成されるRSフリップフロップは安定した状態
を持ちREQ−A,REQ−Ｂの信号に応じて、▲
▼，▲▼を出力する。When the request signals REQ-A and REQ-B are not generated at the same time, the NAND gates 1a and 1b are used as described in the description of the prior art.
The RS flip-flop configured by has a stable state, and according to the REQ-A and REQ-B signals,
Output ▼ and ▲ ▼.
次にREQ−ＡとREQ−Ｂが同時に変化した場合について説
明する。第２図はREQ−ＡとREQ−Ｂが同時に変化した場
合の第１図の各ノードの電圧波形を示す。以下、第２図
に基づいて説明する。Next, a case where REQ-A and REQ-B change simultaneously will be described. FIG. 2 shows the voltage waveform of each node in FIG. 1 when REQ-A and REQ-B change simultaneously. Hereinafter, description will be given with reference to FIG.
時刻T1にREQ−ＡとREQ−Ｂが同時に変化し始めたとす
る。それに従がってノードA,ノードＢはそれぞれ“H"か
ら“L"へ変化しようとするが、途中でつり合ってしまい
中間電位となる。NORゲート２の閾値をこの中間電位の
レベルより少し高く設定しておけば、ノードＡとノード
Ｂが中間電位になった時点でノードＣが“H"になり始め
る（時刻T2）。ノードＣが“H"になるとトランジスタ３
が導通し、ノードＢを接地電位に落とす（時刻T3）。ノ
ードＢが“L"になるとノードＡは“H"になり、ノードＡ
が“H"になるとノードＣは“L"になる（時刻T4）。▲
▼，▲▼は、遅延回路4a,4bを通っ
ているので、ノードＡの電位変化は、遅延の中に隠れて
しまい、表には現れない。It is assumed that REQ-A and REQ-B start to change simultaneously at time T 1 . Accordingly, the nodes A and B each try to change from "H" to "L", but they are balanced in the middle and have an intermediate potential. If the threshold value of the NOR gate 2 by setting slightly higher than the level of the intermediate potential, the node C is at the time when the node A and the node B becomes the intermediate potential begins to "H" (time T 2). Transistor 3 when node C goes to "H"
Becomes conductive, and the node B is dropped to the ground potential (time T 3 ). When the node B becomes "L", the node A becomes "H", and the node A
There "H" becomes the node C becomes "L" (time T 4). ▲
Since ▼ and ▲ ▼ pass through the delay circuits 4a and 4b, the potential change of the node A is hidden in the delay and does not appear in the table.
このように、本第１の実施例では、ノードA,Bが中間電
位になった時、トランジスタ３によりノードＢの電位を
強制的に“L"に落とすようにしたので、REQ−ＡとREQ−
Ｂが同時に活性化しても、▲▼，▲
▼を正常に出力することができる。As described above, in the first embodiment, when the nodes A and B become the intermediate potential, the potential of the node B is forcibly dropped to "L" by the transistor 3, so that REQ-A and REQ −
Even if B are activated at the same time, ▲ ▼, ▲
▼ can be output normally.
第３図はこの発明の第２の実施例によるアービタ回路を
示す。本第２の実施例は、RSフリップフロップを２入力
のNORゲート1c,1dを用いて構成したものである。図にお
いて、2bはNORゲート1c,1dからの出力を２つの入力とす
るNANDゲート、2cはインバータである。NORゲートで構
成されるRSフリップフロップは要求信号がロウアクティ
ブであり、承認信号は“H"になった時に承認を示す。す
なわち、▲▼＝“L",▲▼＝“H"
の時、ACK−Ａ＝“H"となって▲▼の承認を
示し、▲▼＝H,▲▼＝“L"の時、
ACK−Ｂ＝“H"となって▲▼の承認を示す。FIG. 3 shows an arbiter circuit according to the second embodiment of the present invention. In the second embodiment, an RS flip-flop is constructed by using 2-input NOR gates 1c and 1d. In the figure, 2b is a NAND gate having two inputs from the outputs from the NOR gates 1c and 1d, and 2c is an inverter. The request signal of the RS flip-flop composed of the NOR gate is low active, and the approval signal indicates approval when it becomes "H". That is, ▲ ▼ ＝ “L”, ▲ ▼ ＝ “H”
When, ACK-A = "H", indicating approval of ▲ ▼, when ▲ ▼ = H, ▲ ▼ = "L",
ACK-B = "H", indicating the approval of ▲ ▼.
このような本第２の実施例でも、▲▼と▲
▼が同時に“L"になったとすると、ノードＤと
ノードＥは共に“H"になろうとし、ノードＦが“L"とな
り、トランジスタ３がオンして、ノードＥを“L"に落と
す。こうして、ACK−Ａが“H"となって▲▼
が承認され、正常な出力を得ることができる。Also in the second embodiment as described above, ▲ ▼ and ▲
If ▼ becomes "L" at the same time, the nodes D and E both try to become "H", the node F becomes "L", the transistor 3 is turned on, and the node E is dropped to "L". In this way, ACK-A becomes "H".
Is approved and you can get normal output.
なお、上記第1,第２の実施例では、中間電位になったノ
ードの片方を“L"に落とすようにしたが、これは“H"に
するようにしてもよく、同様の効果を奏する。In the first and second embodiments, one of the nodes at the intermediate potential is dropped to "L", but this may be set to "H", and the same effect is obtained. .
以上のように、この発明のアービタ回路によれば、フリ
ップフロップの２つの出力が中間電位になった場合に、
これを検出し、一方の出力ノードを強制的に接地電位又
は電源電位にして第1,第２の承認信号を得るようにした
ので、要求信号が同時に活性化しても、競合裁定の処理
を行うことができる効果がある。As described above, according to the arbiter circuit of the present invention, when the two outputs of the flip-flop are at the intermediate potential,
Since this is detected and one of the output nodes is forcibly set to the ground potential or the power supply potential to obtain the first and second approval signals, the competitive arbitration processing is performed even if the request signals are activated at the same time. There is an effect that can be.
第１図はこの発明の第１の実施例によるアービタ回路を
示す回路図、第２図は該第１の実施例回路の動作を説明
するための波形図、第３図はこの発明の第２の実施例を
示すアービタ回路を示す回路図、第４図は従来のアービ
タ回路を示す回路図、第５図は該従来例のアービタ回路
の動作を説明するための波形図である。 図において、1a,1b,2bはNANDゲート,1c,1d、２はNORゲ
ート、３はスイッチング素子（トランジスタ）、4a,4b
は遅延回路である。 なお図中同一符号は同一又は相当部分を示す。1 is a circuit diagram showing an arbiter circuit according to a first embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the circuit of the first embodiment, and FIG. 3 is a second diagram of the present invention. FIG. 4 is a circuit diagram showing an arbiter circuit showing the embodiment of FIG. 4, FIG. 4 is a circuit diagram showing a conventional arbiter circuit, and FIG. 5 is a waveform diagram for explaining the operation of the conventional arbiter circuit. In the figure, 1a, 1b and 2b are NAND gates, 1c and 1d, 2 is a NOR gate, 3 is a switching element (transistor), and 4a and 4b.
Is a delay circuit. The same reference numerals in the drawings indicate the same or corresponding parts.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−140028（ＪＰ，Ａ) 特開 昭63−143654（ＪＰ，Ａ) 特開 平１−134557（ＪＰ，Ａ) 米国特許4423384（ＵＳ，Ａ) ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-57-140028 (JP, A) JP-A-63-143654 (JP, A) JP-A-1-134557 (JP, A) US Patent 4423384 (US , A)
Claims (3)
し、第1,第２の承認信号をそれぞれ出力し、RSフリップ
フロップを構成する第1,第２の２入力ゲート素子を備え
てなるアービタ回路において、 上記第1,第２の２入力ゲート素子の出力が共に中間電位
となったのを検出する検出素子と、該検出素子の出力を
受け、上記第1,第２の２入力ゲート素子の出力の内いず
れか一方を接地電位又は電源電位にクランプするスイッ
チング素子と、 上記第1,第２の２入力ゲート素子の出力を、それぞれ上
記スイッチング素子によるクランプに要する時間以上遅
延させ、第1,第２の承認信号として出力する第1,第２の
遅延回路とを備えたことを特徴とするアービタ回路。1. A first and second two-input gate element which forms an RS flip-flop and which receives a first and a second request signal respectively as one input and outputs a first and a second approval signal respectively. In the arbiter circuit configured as described above, a detection element that detects that both outputs of the first and second input gate elements have an intermediate potential, and an output of the detection element, A switching element that clamps one of the outputs of the input gate element to the ground potential or the power supply potential, and delays the outputs of the first and second input gate elements by the time required for clamping by the switching element or more. An arbiter circuit comprising: a first delay circuit and a second delay circuit for outputting the first and second approval signals.
力NANDゲートであり、 上記検出素子は、２入力NORゲートであることを特徴と
する特許請求の範囲第１項記載のアービタ回路。2. The first and second two-input gate elements are two-input NAND gates, and the detection element is a two-input NOR gate. Arbiter circuit.
力NORゲートであり、 上記検出素子は、２入力NANDゲートであることを特徴と
する特許請求の範囲第１項記載のアービタ回路。3. The first and second two-input gate elements are two-input NOR gates, and the detection element is a two-input NAND gate. Arbiter circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292831A JPH073940B2 (en) | 1987-11-19 | 1987-11-19 | Arbiter circuit |
| US07/286,921 US4962379A (en) | 1987-11-19 | 1988-11-18 | Arbiter circuit for processing concurrent requests for access to shared resources |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292831A JPH073940B2 (en) | 1987-11-19 | 1987-11-19 | Arbiter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01134558A JPH01134558A (en) | 1989-05-26 |
| JPH073940B2 true JPH073940B2 (en) | 1995-01-18 |
Family
ID=17786917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62292831A Expired - Lifetime JPH073940B2 (en) | 1987-11-19 | 1987-11-19 | Arbiter circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4962379A (en) |
| JP (1) | JPH073940B2 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02242469A (en) * | 1989-03-16 | 1990-09-26 | Fujitsu Ltd | Opposite device monitoring system |
| US5263171A (en) * | 1990-03-27 | 1993-11-16 | Cybex Corporation | Device for interfacing two keyboards to one computer and for automatically connecting the active keyboard to the computer |
| US5218552A (en) * | 1990-07-30 | 1993-06-08 | Smart House, L.P. | Control apparatus for use in a dwelling |
| US5175731A (en) * | 1990-12-11 | 1992-12-29 | International Business Machines Corporation | Arbitration circuit for a multimedia system |
| US5341052A (en) * | 1991-12-04 | 1994-08-23 | North American Philips Corporation | Arbiter with test capability and associated testing method |
| DE69224427T2 (en) * | 1991-12-04 | 1998-08-13 | Koninkl Philips Electronics Nv | Arbiter with a direct signal changeable under priority conflict control |
| DE59208273D1 (en) * | 1992-01-29 | 1997-04-30 | Siemens Nixdorf Inf Syst | Input / output system for data processing systems |
| JP2716911B2 (en) * | 1992-06-05 | 1998-02-18 | 三菱電機株式会社 | Priority selection circuit |
| IE922761A1 (en) * | 1992-10-21 | 1994-05-04 | Digital Equipment Internat Ltd | Port controller |
| US5713025A (en) * | 1993-10-21 | 1998-01-27 | Sun Microsystems, Inc. | Asynchronous arbiter using multiple arbiter elements to enhance speed |
| US5875339A (en) * | 1993-10-21 | 1999-02-23 | Sun Microsystems, Inc. | Asynchronous arbiter using multiple arbiter elements to enhance speed |
| US5541582A (en) * | 1994-01-13 | 1996-07-30 | Datascape, Inc. | Apparatus for data communication switching |
| FR2797971A1 (en) * | 1999-08-31 | 2001-03-02 | Koninkl Philips Electronics Nv | ACCESS TO A COLLECTIVE RESOURCE |
| JP2002092738A (en) * | 2000-09-19 | 2002-03-29 | Matsushita Electric Ind Co Ltd | Cash drawer control device and cash drawer control method |
| CN109547011B (en) * | 2017-09-22 | 2022-11-29 | 智原科技股份有限公司 | Arbitration circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4423384A (en) | 1981-12-21 | 1983-12-27 | Motorola, Inc. | Asynchronous multi-port arbiter |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3824409A (en) * | 1972-06-12 | 1974-07-16 | Massachusetts Inst Technology | Arbiter circuits |
| US4249093A (en) * | 1978-09-06 | 1981-02-03 | Lockheed Electronics Co., Inc. | Multiple request arbitration circuit |
| US4314164A (en) * | 1979-11-05 | 1982-02-02 | Gte Automatic Electric Labs Inc. | Computer channel access circuit for multiple input-output devices |
| US4339808A (en) * | 1980-03-04 | 1982-07-13 | Motorola, Inc. | Asynchronous event prioritizing circuit |
| US4612542A (en) * | 1984-12-20 | 1986-09-16 | Honeywell Inc. | Apparatus for arbitrating between a plurality of requestor elements |
| US4815039A (en) * | 1988-01-11 | 1989-03-21 | Texas Instruments Incorporated | Fast real-time arbiter |
-
1987
- 1987-11-19 JP JP62292831A patent/JPH073940B2/en not_active Expired - Lifetime
-
1988
- 1988-11-18 US US07/286,921 patent/US4962379A/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4423384A (en) | 1981-12-21 | 1983-12-27 | Motorola, Inc. | Asynchronous multi-port arbiter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01134558A (en) | 1989-05-26 |
| US4962379A (en) | 1990-10-09 |
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