JPH0740440B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of simultaneously performing a functional test on a plurality of memory cells.

[Conventional technology]

FIG. 5 is a schematic block system diagram mainly showing an electrical configuration of an output circuit (reading circuit) of a conventional dynamic semiconductor memory device having a plurality of parallel data inputs / outputs. In FIG. 5, the memory cell array 1 is composed of a plurality of memory cells arranged two-dimensionally, for example. Further, in the figure, four memory cells are selected from a plurality of memory cells included in the memory cell array 1, and signals I / O0, ▲ ▼, I / O1, and ▲ corresponding to respective stored contents are selected.
▼, I / O2, ▲ ▼, I / O3, ▲ ▼ are output to the preamplifiers and write buffers 2 to 5, and these preamplifiers and write buffers 2 to 5 are respectively
Signal I / O0 read from the memory cell array 1, ▲
▼, I / O1, ▲ ▼, I / O2, ▲ ▼, I / O3, ▲
The signals RD0 to RD3 are output based on ▼. The signals RD0 to RD3 output from the preamplifiers and the preamplifiers of the write buffers 2 to 5 are given to the input terminals of four input buffers and output buffers (hereinafter simply referred to as "buffers") 6 to 9, respectively. These input signals RD0-RD3 are
After being amplified by the buffers 6 to 9, they are given to the external input / output terminals DQ0 to DQ3 as external output signals.

Next, the outline of the operation at the time of the function test of the device shown in FIG. 5 will be described. Generally, in a conventional semiconductor memory device, a functional test of a memory cell is performed in a wafer state before the semiconductor memory device is packaged. This functional test is executed by exchanging signals between a memory test device (not shown) and the semiconductor memory device. For example, first, a constant logical value, for example, "0" is written in all the memory cells forming the semiconductor memory device by the memory testing device. Next, the stored content of the memory cell is read bit by bit, and it is determined whether or not the memory cell is functioning normally by checking whether or not it matches the previously written logical value.

The above test operation will be described with reference to FIG. In FIG. 5, it is assumed that "0" has been written in advance in all the memory cells forming the memory cell array 1 by the memory testing device. A 4-bit memory cell is selected from these memory cells, and the logic value, that is, "0" held therein is read out to the preamplifier and the write buffers 2 to 5, respectively.

The preamplifier and the write buffers 2 to 5 are logical data I / O0 read from the memory cell array, ▲
▼, I / O1, ▲ ▼, I / O2, ▲ ▼, I / O3, ▲
▼ is output as signals RD0 to RD3. The signals RD0 to RD3 are applied in parallel to the input terminals of the four buffers 6 to 9, respectively. These input signals RD0 to RD3 are buffers 6 to 9
After being amplified by the external output signal DQ
0 to DQ3 are given in parallel.

In this way, since the logic data written in the memory cell for the functional test is output in parallel from the four external input / output terminals DQ0 to DQ3, the memory testing device requires four comparators.

[Problems to be solved by the invention]

In the conventional semiconductor memory device having a plurality of external input / output terminals, as described above, as many comparators as the number of external input / output terminals are required, and the number of semiconductor memory devices capable of performing a functional test at the same time is the number of comparators / external There was a problem that the number of input / output terminals was reduced and the number of input / output terminals decreased.

The present invention has been made in view of the above circumstances, and an object thereof is to enable a functional test of a semiconductor memory device having a plurality of external input / output terminals to be performed by one comparator, and at the same time, to perform the functional test. It is an object of the present invention to provide a semiconductor memory device capable of increasing the number of semiconductor memory devices that operate.

[Means for solving problems]

In order to achieve such an object, the present invention provides a semiconductor memory device having a plurality of parallel data input / output functions,
Output means for decompressing the function test contents of a plurality of bits of a memory cell into one signal and outputting the same from one external input / output terminal during a function test of a plurality of memory cells, and an external input / output terminal during a function test of a plurality of memory cells. And an input means for decompressing a plurality of bits of data input from the above into one signal and inputting it into the inside.

[Action]

In the present invention, the logical data read in parallel is
It is output as one test external output data during the function test.

〔Example〕

FIG. 1 is a schematic block system diagram showing an embodiment of a semiconductor memory device according to the present invention.

First, the case of data output will be described. The signals R0a to R3a output from the preamplifiers and the write buffers 2 to 5 are input to the test mode circuit 10. Test mode circuit 10
2 (a), (b), 3 (a), (b)
Shown in. This FIG. 2 (a), (b), FIG. 3 (a),
The circuit of (b) constitutes an output means.

In FIG. 2, test mode signals RTH and RTL are created. Therefore, an AND gate 12 and a NOR gate 13 which receive the signals R0a to R3a are provided. When the signals R0a to R3a are all "1", RTH is "H", RTL is "L", and the signal Q2 shown in FIG. 3A is "H". Also, the signal R0
When all of a to R3a are "0", RTH is "L", RTL is "H", and the signal Q2 is "L". In addition, the signal R0
When a to R3a are other than the above, RTH is "L", RTL is "L"
And the signal Q2 becomes high impedance.

In FIG. 3 (a), a signal TE is a signal from an external memory testing device (not shown), which is a test mode switching signal which becomes a high level during a functional test. Signal ▲
▼ is a signal obtained by inverting the test mode switching signal TE. The transistors 15a and 15b are conductive when the test mode switching signal TE is "L", and the transistors 16 and 17 are conductive when the test mode switching signal TE is "H". The inverter 14 outputs the signal R2 output from the preamplifier and the write buffer 4.
Input a and output the inverted signal ▲ ▼.

In FIG. 3 (b), the inverter 18 inputs the output signals R0a, R1a, R3a from the preamplifiers and the write buffers 2, 3, 5 and outputs inverted signals ▲ ▼, ▲ ▼, ▲ ▼. One input of the 2-input NOR gate 19 is the test mode switching signal TE, and the other 1 inputs are ▲ ▼, ▲.
▼, ▲ ▼, NOR gate 19 outputs signals R0, R1, R3, and inverter 20 provides ▲ ▼, ▲ ▼, ▲.
Output ▼.

The circuit operation of FIGS. 3A and 3B will be described. The signal R2a from the preamplifier and the write buffer 4 is cut off in the test mode by the transistors 15a and 15b,
Instead, due to the conduction of the transistors 16 and 17, the test mode signals RTH and RTL become the signals R2 and ▲ ▼, respectively.
This signal R2, ▲ ▼ is input to the buffer 23, amplified by the buffer 23, and output as the external output signal Q2 to the external input / output terminal.
Given to DQ3.

In FIG. 3B, in the test mode, that is, when the test mode switching signal TE is at high level, the signals R0a, R1a, R3
a is cut off by NOR gate 19, and signals R0 and R
1, R3 are all "L". During normal operation, that is, when the test mode switching signal ▲ ▼ is at high level, the NOR gate 19 becomes conductive, and the signals R0a, R1a, R3a become signals R0, R1, R3, respectively.

That is, in test mode, external input / output terminals DQ1, DQ2, DQ
The four signals Q0, Q1, Q3 are at "L" level regardless of the output signals R0a, R1a, R3a from the preamplifier and the write buffer.

Next, the case of data input will be described with reference to FIGS. FIG. 4 is a circuit diagram showing the inside of the test mode circuit 11, showing the input means. In FIG. 1, in the input test mode from the external input / output terminals DQ1 to DQ4, if "H" or "L" is input from the terminal DQ2,
As shown in the figure, the signal W0a
~ W3a are all "H" or "L". At this time, the other external input / output terminals DQ1, DQ3, DQ4 are connected to the transistors 25, 26, 27
Is cut off from the semiconductor memory device. In the test mode, the output signals W0a to W3a from the test mode circuit 11 are buffers 21, 22, 23, 24, preamplifiers and write buffers 2, 3,
The write buffers 4 and 5 (FIG. 1) write the same level signal “H” or “L” to the memory cell array 1.

As described above, the storage content of the 4-bit memory cell is set to 1
External input / output terminals by combining into one output signal
It can be judged that the logical data output from DQ3 is stored in all 4-bit memory cells,
If the logical data value is equal to the logical data value previously written in the memory cell from the terminal DQ2 in the test mode, 4
All bit memory cells can be considered to be functioning correctly. Further, when no logical data is output, that is, when the external input / output terminal DQ3 is in a high impedance state, a memory cell storing "L" and a memory storing "H" in the 4-bit memory cell. Cells and that at least one memory cell is defective.

Therefore, even in the semiconductor memory device having a plurality of external input / output terminals, the quality of the memory cell can be determined by observing one external input / output terminal DQ3 in the test mode.
Only one comparator is needed. As a result, many semiconductor memory devices can be tested simultaneously.

Although the input terminal of the test mode switching signal TE is not shown in the above embodiment, the external input / output terminal DQ1 or DQ4 which is not used in the test mode may be used.

〔The invention's effect〕

As described above, according to the present invention, when a function test of a plurality of memory cells is performed, the function test content of a plurality of bits of memory cells is degenerated into one signal and output from one external input / output terminal. By decompressing input multi-bit data into one signal and inputting it into one signal, even in a semiconductor memory device having a plurality of external input / output terminals,
Since the quality of the memory cell can be determined by observing the two external input / output terminals, the number of required comparators is sufficient, and many semiconductor memory devices can be tested simultaneously.

[Brief description of drawings]

FIG. 1 is a schematic block system diagram showing an embodiment of a semiconductor memory device according to the present invention, FIGS. 2, 3, and 4 are circuit diagrams showing the inside of a test mode circuit, and FIG. It is a schematic block system diagram which shows a semiconductor memory device. 1 ... Memory cell array, 2-5 ... Preamplifier and write buffer, 10,11 ... Test mode circuit, 21-24 ...
... Input and output buffers, DQ1 to DQ4 ... External input / output terminals.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsumi Dosaka 4-chome, Mizuhara, Itami City, Hyogo Prefecture, LS Electric Research Institute, Inc. (72) Inventor Yasuhiro Konishi 4-chome, Mizuhara, Itami City, Hyogo Prefecture Address Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Shuji Miyatake 4-1, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Laboratory (72) Inventor Masaki Kumanoya Itami Hyogo Prefecture Mizuhohara, 1-chome, Mitsubishi Electric Co., Ltd. LSE Research Laboratory (72) Inventor Masayoshi Shimoda 4-1-1, Mizuhara, Itami-shi, Hyogo Prefecture Mitsubishi Electric Co., Ltd. Kita Itami Works (72) Inventor Yama ▲ ▼ Hiroyuki 4-1, Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSI Research Laboratory (56) References JP-A-61-51700 (JP, A)

Claims (5)

[Claims] 1. A memory cell array having a plurality of memory cells each storing 1-bit data, and a plurality of output terminals to which the data stored in a corresponding selected selected memory cell in the memory cell array are output, respectively. A semiconductor memory device comprising: output means for outputting 1-bit test result data to one output terminal based on a plurality of data stored in a plurality of selected memories corresponding to the plurality of output terminals in response to a test signal. 2. The output means receives a test signal and a plurality of data stored in a plurality of selected memory cells, and outputs a coincidence signal having a predetermined level when the logics of the plurality of data are all equal according to the test signal. A test mode means for performing the above, and a buffer means provided corresponding to one output terminal for outputting 1-bit test result data corresponding to the coincidence signal to the corresponding one output terminal. 2. A semiconductor memory device according to claim 1. 3. Output means are provided corresponding to a plurality of selected memory cells, respectively.
A plurality of preamplifier means for receiving a storage signal according to the data stored in the corresponding selected memory cell and outputting a read signal according to the storage signal, provided corresponding to each output terminal, each having an input node. A plurality of buffer means for receiving the read signal from the corresponding preamplifier means at the input node and outputting the data corresponding to the signal given to the input node to the corresponding output terminal, the test signal and the preamplifier. Receiving a read signal and outputting a match signal having a predetermined level when the logics of the read signals are all equal according to the test signal, to the input node of one of the plurality of buffer means, A test mode means for cutting off the application of the read signal to the device. The semiconductor memory device according to 1, wherein. 4. A memory cell array having a plurality of memory cells each storing 1-bit data, a plurality of input terminals to which data to be written to a corresponding selected memory cell in the memory cell array is input, and a test signal. Accordingly, a semiconductor memory device having an input terminal for writing data input from one input terminal to a plurality of selected memories corresponding to the plurality of input terminals. 5. The input means is provided corresponding to a plurality of selected memory cells, respectively.
A plurality of write buffer means having an input node for writing data given to the input node to the selected memory cell; provided for each input terminal; One of a plurality of input buffer means for outputting to an input node of the buffer means, a test signal and one of the plurality of input buffer means
And outputs the data output from one of the plurality of input buffer means to all the nodes of the plurality of write buffer means in response to a test signal and to the other input buffer. 5. The semiconductor memory device according to claim 4, further comprising a test mode means for blocking application of data output from the other input buffer means to an input node of the corresponding write buffer means.