JPH0740589B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor technology and a technology particularly effective when applied to an electrode formation of a semiconductor device. For example, the invention is effectively applied to an electrode structure of a memory cell in a bipolar static RAM. Related technology.

[Background Art] Static RAM composed of bipolar transistors
As a structure of a memory cell in (random access memory), for example, there is an emitter-coupled type memory cell as shown in FIGS. 3 and 4 (Japanese Patent Application No. 58-151551 and Japanese Patent Application Laid-Open No. 58-222488). ).

Of these, in the memory cell shown in FIG. 3, the Schottky barrier diodes SBD ₁ and SBD ₂ are connected in parallel with the load resistances R ₁ and R ₂ , so that the Schottky barrier diode with a small forward resistance is used for reading. A current bypass path is formed. Therefore, the read current can be increased, which enables high-speed read.

However, the Schottky barrier diode increases the cell area and the node within the cell.
As can be seen from FIG. 5 showing the relationship between the electric potentials Vco and Vc ₁ of n ₁ and n _{2 and} the electric current, the electric potentials Vco and Vc ₁ are determined by the load resistances R ₁ and R _{2 in} the range of minute current. , Vco decreases with decreasing current and Vc ₁
The potential difference between Vco and Vco becomes smaller and smaller, and the operating margin of the memory cell decreases. Therefore, the memory cell of the type shown in FIG.
It is necessary to pass Ist to secure the cell margin.

On the other hand, the memory cell of FIG. 4 using the PNP transistor as a load element (hereinafter referred to as PNP load type memory cell) has a Schottky barrier, which has a relatively large element size.
Do not use diodes. Further, since the cell structure is the same as that of I ² L (Integrated Injection Logic), the element isolation region is unnecessary.
Therefore, the PNP load type memory cell has a cell area of about one-third of that of the memory cell of FIG. 3, and high integration and large capacity can be achieved. Moreover, the potential Vco in the cell is determined by the base-emitter voltage V _{BE of the} PNP load transistor. Therefore, even if the current is reduced as shown in FIG. 5, the holding voltage V _MC, that is, the cell operation margin can be secured. Therefore, the holding current is about 1/10 of that of the memory cell in FIG. 3, and there is an advantage that the current consumption of the entire circuit is very small.

However, in the PNP load type memory cell, the transistors are both saturated (the number of accumulated carriers increases) in the holding state and the holding voltage cannot be set to V _BE of the PNP transistor or less, so that the cell inversion does not easily occur at the time of writing. Therefore, there is an inconvenience that the writing time is long.

[Object of the Invention] An object of the present invention is to shorten the access time and increase the writing speed in a static RAM composed of emitter-coupled memory cells using PNP transistors as load elements.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention] The outline of a typical invention disclosed in the present application will be described below.

That is, it is known that the decrease in access time and writing speed due to the miniaturization of the memory cell is caused by the structure of the emitter electrode of the transistor, and the emitter electrode contacted with the surface of the semiconductor region serving as the emitter region is By using a silicide (PtSi) of a refractory metal such as platinum as the bottom electrode layer and forming an aluminum silicon layer on this metal silicide layer, the contact resistance of the electrode part of the transistor is reduced. At the same time, the _hFE (DC current amplification factor) of the PNP load transistor is reduced to make the saturation of the PNP load transistor in the holding state shallow, thereby improving the switching speed of memory cell selection / non-selection. It is intended to achieve the above-mentioned object of facilitating cell inversion and improving access time and write speed.

Furthermore, by interposing a barrier layer such as titanium and tungsten between the emitter electrode and the laminated structure of the platinum silicide layer and the aluminum silicon layer, the PNP load transistor is Of course, the contact resistance of the emitter electrode in the NPN drive transistor is also reduced to increase the switching speed of the memory cell and further shorten the access time.

[Embodiment 1] FIG. 1 shows an embodiment of a cell structure when the present invention is applied to a PNP load type memory cell. However, the figure shows only the transistors Q ₁ and Q ₃ (or Q ₂ and Q ₄ ) on one side of the circuit-symmetrical memory cell. Transistors Q ₂ and Q ₄ on the opposite side have the same structure and drive transistors Q ₃ and
A flip-flop circuit type memory cell is constructed by cross-connecting the base and collector of Q ₄ with aluminum wiring.

An N ⁺ type buried layer 2 is partially formed on one semiconductor substrate 1 such as P type single crystal silicon. The N ⁺ type buried layer 2 is formed by forming an oxide film on the surface of the semiconductor substrate 1 and then forming a hole for a buried diffusion pattern at an appropriate position of the oxide film, and using this oxide film as a mask, arsenic or It is formed by thermally diffusing N-type impurities such as antimony.

Then, an N ⁻ type epitaxial layer 4 is formed on the N ⁺ type buried layer 2 by a vapor phase growth method. An N ⁺ type semiconductor region 5 serving as a collector pull-up port is formed in a part of the N ⁻ type epitaxial layer 4 so as to penetrate the N ⁻ type epitaxial layer 4 to reach the N ⁺ type buried layer 2 by an ion implantation method or the like. There is.

In addition, P-type impurities such as boron are introduced into the main surface of the epitaxial layer 4 by ion implantation or the like, and NP
A P ⁺ type semiconductor region 6a, which serves as a base region of the N drive transistor Q ₃ (Q ₄ ) is formed. Adjacent to the P ⁺ type semiconductor region 6a, on the main surface of the epitaxial layer 4, a P ⁺ type semiconductor 6b which becomes an emitter region of the PNP load transistor Q ₁ (Q ₂ ) is formed.
Are formed. As a result, a PNP load transistor is formed which operates laterally with the P ⁺ type semiconductors 6a and 6b as the emitter and collector regions and the N ⁺ type buried layer 2 as the base region. The P ⁺ type semiconductor regions 6a and 6b can be formed in the same process.

Further, on the surface of the P ⁺ type semiconductor region 6a, a pair of N ⁺ type semiconductor regions 7a and 7b to be emitter regions are formed adjacent to each other. As a result, an NPN drive transistor Q ₃ (Q ₄ ) having a multi-emitter structure that operates in the vertical direction is formed. An insulating film 8 such as a silicon oxide film is formed on the surface of the epitaxial layer 4. This insulating film 8
An opening is formed corresponding to the emitter regions 7a and 7b, and polysilicon electrodes 9a and 9b are formed inside the opening. An interlayer insulating film 10 such as a silicon oxide film or a silicon nitride film is formed by a CVD method or the like from above the polysilicon electrodes 9a, 9b to above the insulating film 8. The interlayer insulating film 10 has the above-mentioned polysilicon electrodes. 9a, 9b
Openings 10a, 10b, 10c and 10d are formed corresponding to the N ⁺ type semiconductor region 5 and the P ⁺ type semiconductor region 6b.

Then, in this embodiment, on the surfaces of the polysilicon electrodes 9a, 9b inside the openings 10a, 10b and the semiconductor regions 5, 6b inside the openings 10c, 10d, a silicide of refractory metal such as platinum ( Compound of metal and silicide PtSi) Layer 11a, 11b, 11
c and 11d are formed. In this case, when the platinum layer is vapor-deposited over the entire surface after forming the openings 10a to 10d and then heat treatment called sintering is performed, the silicide layers 11a to 11d are formed in such a manner that platinum penetrates into the silicon layer. . Therefore, the underlying polysilicon electrodes 9a and 9b and the semiconductor regions 5 and 6b are slightly thinned.

After forming an aluminum silicon (AlSi) layer by a sputtering method on the platinum silicide layers 11a to 11d, patterning is performed to form aluminum electrodes 12a, 12b,
12c and 12d are formed.

In the above embodiment, since the platinum silicide layers 11a to 11d are formed under the aluminum electrodes 12a to 12d, the contact resistance of each electrode portion is reduced. That is, as shown in FIG. 6, the semiconductor region 5 (6
b) Alternatively, if the aluminum electrode is formed directly on the surface of the polysilicon electrode, the foreign matter 20 such as a silicon oxide film or alumina often remains on the interface with the underlying semiconductor layer. Therefore, the substantial contact area of the aluminum electrode has been reduced. In particular, as the area of the openings 10a to 10d is made finer for higher integration, the influence becomes larger.
Switching speed of the load transistor Q _1, the emitter resistor and NPN drive Q ₂ 'transistor Q _3, a memory cell emitter resistance increases the Q ₄ has been slowed.

Furthermore, when the electrode 12c made of aluminum silicon (AlSi) is brought into direct contact with the surface of the emitter region (6b) of the PNP load transistor, the silicon in the aluminum moves even at a low temperature such as 200 ° to 300 ° C. Silicon is deposited on the surface of the ⁺ type semiconductor region 6b to form a solid phase epitaxial layer. As a result, a Schottky barrier diode is formed at the boundary between the P ⁺ type semiconductor region 6b and the aluminum electrode 12c on the P ⁺ type semiconductor region 6b, the emitter resistance suddenly increases, and the reliability decreases. When aluminum containing no silicon is used as the electrode material, the silicon in the semiconductor region contacting the electrode may be sucked up into the aluminum electrode and cause a spike, which may destroy the PN junction. It is not preferable to do.

On the other hand, in the above embodiment, the platinum silicide layers 11a to 11d are formed under the aluminum electrodes 12a to 12d. Therefore, when platinum is silicidized, foreign substances attached to the interface are taken into the silicide layer.
As a result, the substantial contact area of each electrode is increased and the contact resistance is reduced. As a result, the switching speed of the memory cell is improved.

Moreover in this embodiment, the platinum silicide layer 11 a to 11 d, in particular when 11c is formed, the impurity in the P ⁺ -type semiconductor regions 6b (boron) is taken within the silicide, the emitter region serving as the P ⁺ -type semiconductor As the impurity concentration of the region 6b decreases, the thickness thereof also decreases as described above. As a result, the base current easily flows from the P ⁺ type semiconductor region 6b toward the N ⁺ type buried layer 2, which is the base region thereunder, and the h _{FE of the} PNP load transistors Q ₁ and Q ₂ is lowered. However, when h _{FE of} PNP load transistors Q ₁ and Q ₂ goes down,
The saturated amount in the holding state becomes shallow, and it becomes difficult for accumulated carriers to accumulate. As a result, the inversion of the memory cell is likely to occur during writing, and the writing speed is increased.

Further, in the above-described embodiment, since the platinum silicide layer 11c is formed on the surface of the P ⁺ type semiconductor 6b, even if the electrode 12c made of aluminum silicon is formed on the platinum silicide layer 11c, the silicon in the aluminum is the platinum silicide layer 11c. Since it does not deposit on the surface of the device, there is no risk of lowering the reliability.

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.

In this embodiment, the contact resistance of the emitter electrode of the NPN drive transistor Q ₃ (Q ₄ ) in the first embodiment is reduced.

That is, in the first embodiment, the surface of the polysilicon electrode 9a, 9b, etc. on the P ⁺ type semiconductor region 6b which is the emitter region of the PNP load transistor and the N ⁺ type semiconductor region 7a, 7b which is the emitter region of the NPN drive transistor. On platinum silicide layer 1
1 is formed, and the height φ _B of the contact barrier between the platinum silicide layer and silicon is smaller than that of P ⁺ type silicon, so the contact resistance is small and there is no problem.

However, the platinum silicide layer 11a of the embodiment described above is used.
Aluminum electrodes 12a-12 made of aluminum silicon on 11d
When d is formed, a compound PtAl ₂ Si of platinum, aluminum and silicon is formed at the boundary between the _two . This compound P
The height φ _B of the contact barrier of tAl ₂ Si is small for N ⁺ type silicon but large for P ⁺ type silicon. In the above embodiment, the PNP load transistor Q ₁
The emitter regions 6a and 6b of (Q ₂ ) are P ⁺ type. Therefore, P
The contact resistance at the emitter electrode of the NP load transistor is
It is considered that the contact resistance at the emitter electrode of the NPN drive transistor may not be sufficiently reduced.

Therefore, in the second embodiment, as shown in FIG.
Barrier layers 13a to 13d made of a refractory metal such as titanium-tungsten (TiW) are formed between the platinum silicide layers 11a to 11d and the aluminum electrodes 12a to 12d. The other structure is the same as that of the first embodiment.

According to this embodiment, the platinum silicide Pt of the bottom layer of the electrode portion is
The reaction between Si and aluminum silicon AlSi in the uppermost layer of the electrode part
It is suppressed by the intermediate barrier layers 13a-13d. Therefore, a compound such as PtAl ₂ Si having a large barrier height φ _B against P ⁺ type silicon is not formed at the boundary of the electrode layers. As a result, the contact resistance at the emitter electrode portion of the PNP load transistor is reduced, and the switching speed of the memory cell is further increased.

In the above embodiment, the platinum silicide layer is used as the lower layer of the electrode portion, aluminum silicon is used as the upper layer of the electrode portion, and titanium / tungsten is used as the intermediate barrier layer. However, each electrode material is not limited to these. Needless to say, other materials having equivalent properties may be used.
For example, palladium silicide PdSi ₂ is used instead of the platinum silicide layers (11a to 11d), molybdenum, titanium, tungsten, or a compound thereof is used for the barrier layers 13a to 13d, and aluminum and copper are used instead of the aluminum electrodes 12a to 12d. Alternatively, a compound of silicon such as AlCuSi may be used.

Further, in order to improve the access time and the writing speed, which are the objects of the present invention, at least the emitter resistance of the PNP load transistor and the emitter resistance of the emitter of the NPN drive transistor connected to the data line can be reduced. It is only necessary that these electrodes have the structure as in the above-mentioned embodiment, and other electrodes can have a different structure.

Further, in the above embodiment, the polysilicon electrodes 9a and 9b are formed on the surfaces of the N ⁺ type semiconductor regions 7a and 7b which are the emitter regions of the NPN drive transistor, and the platinum silicide layer 11 is formed thereon.
Although it has a structure in which a and 11b are formed, the emitter regions 7a and 7b are formed by forming the polysilicon electrodes 9a and 9b.
The shallowly, raising the h _FE of the NPN drive transistor, it is possible to increase the operating speed.

[Effects] (1) In a static RAM composed of an emitter-coupled memory cell having a PNP transistor as a load element, the electrode layer at the bottom of the emitter electrode in contact with the surface of the semiconductor region serving as the emitter region of the transistor forming the memory cell As a silicide of a refractory metal such as platinum (Pt, S
Since i) is used and a laminated structure in which an aluminum silicon layer is formed on this metal silicide layer is used, foreign matter at the interface with the semiconductor region is taken in when the metal silicide layer is formed. The substantial contact area of the electrodes is increased and the contact resistance of the electrode portion of the transistor is reduced. This has the effect of improving the switching speed for selecting / deselecting the memory cells and shortening the access time.

(2) In a static RAM composed of an emitter-coupled memory cell having a PNP transistor as a load element, platinum is used as the lowermost electrode layer of the emitter electrode in contact with the surface of the semiconductor region serving as the emitter region of the transistor constituting the memory cell. Refractory metal silicide (Pt, S
Since i) is used and the aluminum silicon layer is formed on the metal silicide layer, the silicon and P-type impurities in the emitter region of the PNP load transistor are taken in when the metal silicide layer is formed. As a result of the growth, the impurity concentration in the emitter region is reduced and the thickness of the emitter region is reduced, so that _hFE (DC current amplification factor) of the PNP load transistor is reduced, and the PNP load transistor in the holding state is reduced. Is made shallower, which makes it easier to invert the memory cell and speeds up the writing speed.

(3) In a static RAM composed of an emitter-coupled memory cell having a PNP transistor as a load element, platinum is used as the lowermost electrode layer of the emitter electrode which is in contact with the surface of the semiconductor region which becomes the emitter region of the transistor constituting the memory cell. Refractory metal silicide (Pt, S
Since i) is used and the aluminum silicon layer is formed on this metal silicide layer, and the barrier layer is interposed between the two, the reaction between the platinum silicide and the aluminum silicon depends on the barrier layer. By the action of being suppressed, not only PNP load transistor but also N
The contact resistance of the emitter electrode of the PN drive transistor is also effectively reduced, which has the effect of increasing the switching speed of the memory cell and further shortening the access time.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, the feature of the present invention lies in the electrode structure, and in the embodiments, only the most general device structure is shown. In other words, the element structure is not limited to that shown in FIG. 1 or FIG.
P ⁺ type semiconductor region 6b, which is the emitter region of the load transistor
May be deeply formed so as to reach the N ⁺ type buried layer 2 thereunder. In addition, the base region 6a of the NPN drive transistor
It is possible to optimize each h _FE by contacting a part of it with the N ⁺ type buried layer 2 or changing the base thickness directly under the emitter regions 7a and 7b. .

[Field of Use] In the above description, the invention mainly made by the present inventor is described as being applied to a static RAM composed of PNP load type memory cells which is the field of use in the background, but the present invention is not limited thereto. I ²
It can be used for an electrode structure of an element in a semiconductor integrated circuit or a MOS integrated circuit using L.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the structure of a PNP load type memory cell according to the present invention, FIG. 2 is a sectional view showing a second embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing a configuration example of a conventional emitter-coupled memory cell, FIG. 4 is a circuit diagram showing a configuration example of a PNP load type memory cell which is an object of the present invention, and FIG. FIG. 6 is an explanatory diagram showing current-voltage characteristics, and FIG. 6 is a sectional view showing a general electrode structure in a conventional semiconductor integrated circuit device. 1 ... Semiconductor substrate, 2 ... N ⁺ type buried layer, 5 ... collector pull-up port, 6a ... NPN transistor base region / PNP transistor collector region, 6b ... PNP transistor emitter region, 7a, 7b ...... NPN transistor emitter region, 9a, 9b …… Polysilicon electrode, 11a to 11d …… Metal silicide layer (platinum silicide layer), 12a to 12d …… Aluminum silicon layer, 13a to 13d …… Barrier layer, Q ₁ , Q ₂ ... PNP load transistor, Q ₃ , Q ₄ ... NPN drive transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenzo Matsumura 1448, Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra ESI Engineering Co., Ltd. Address: Hitachi Ultra EPS Engineering Co., Ltd. (72) Inventor Seiichi Haruto 1448, Kamimizuhoncho, Kodaira-shi, Tokyo Address: Hitachi Ultra EPS Engineering Co., Ltd. (72) Norika Okuda Tokyo 1448, Kamimizuhonmachi, Kodaira-shi, Tokyo Within Hitachi Ultra ESL Engineering Co., Ltd. (72) Inventor Katsumi Ogigami 2326, Imai, Ome-shi, Tokyo Inside Hitachi Device Works Development Center (72) Masato Iwabuchi 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device development The printer (56) References Patent Sho 54-71564 (JP, A)

Claims (2)

[Claims] 1. A pair of multi-emitter NPN drive transistors having a base and a collector cross-coupled to each other, a first emitter connected to a data line, and a second emitter connected to a holding current source, and their driving. A pair of PNPs whose bases are connected to the collectors of the transistors and whose collectors are connected to the bases of the drive transistors.
In a semiconductor memory device comprising an emitter-coupled memory cell including a load transistor, the NPN drive transistor has an N-type emitter region, a P-type base region, and an N-type base region in a depth direction from a surface of a semiconductor substrate. The PNP type load transistor has a vertical structure in which a collector region is sequentially formed, and the PNP type load transistor has a horizontal structure in which a P type emitter region, an N type base region and a P type collector region are sequentially formed along a surface of a semiconductor substrate. The N-type base region is formed as a common semiconductor region with the N-type collector region of the NPN-type drive transistor, and the P-type collector region of the load transistor is formed as a common semiconductor region with the P-type base region of the NPN-type drive transistor. In addition, the PNP type load transistor emitter electrode is heat-treated by depositing a refractory metal film on the bottom layer. As a result, a silicided refractory metal silicide layer is formed, and a conductive layer composed mainly of aluminum is formed on the refractory metal silicide layer. In the 2 emitter electrode, a polysilicon layer is formed in the lowermost layer, and a refractory metal silicide layer silicided by depositing a refractory metal film and heat treatment is formed on the polysilicon layer. A semiconductor memory device having a structure in which a conductive layer composed mainly of aluminum is formed on the refractory metal silicide layer. 2. A barrier layer made of a refractory metal is formed between the refractory metal silicide layer and the conductive layer containing aluminum as a main component. Semiconductor memory device.