JPH0740594B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device, and particularly effective when applied to a semiconductor integrated circuit device (hereinafter referred to as SRAM) having a static random access memory. It is about technology.

[Conventional technology]

A memory cell of SRAM is composed of a transfer MISFET and a flip-flop circuit having a drive MISFET. this
In order to improve reliability in the information reading operation and to achieve high integration, SRAM needs to prevent soft error caused by α-rays.

Therefore, Japanese Patent Application No. 59-21 previously filed by the applicant of the present application
The techniques described in Japanese Patent Application No. 8470 and Japanese Patent Application No. 59-260744 are effective in preventing soft errors.

The former first technique is that, in the lower part of the high-concentration n-type drain region of the driving MISFET used as an information storage capacitive element,
A high-concentration p-type semiconductor region is provided in contact with it.
In other words, this p-type semiconductor region can increase the pn junction capacitance, that is, the amount of charge accumulated as information, and can prevent the inversion of information due to minority carriers. The p-type semiconductor region is formed by introducing a p-type impurity by ion implantation and is self-aligned with the gate electrode of the driving MISFET.

In the latter second technique, a high-concentration p-type semiconductor region is provided at a deep position below a driving MISFET used as an information storage capacitive element. That is, this p-type semiconductor region is
Since the potential barrier region for the minority carriers generated by α rays is formed, it is possible to prevent the minority carriers from entering the information storage capacitive element and prevent the inversion of information. p
The p-type semiconductor region is formed in substantially the entire area of the memory cell by introducing p-type impurities by high-energy ion implantation.

[Problems to be solved by the invention]

The present inventor has found that the following problems occur as a result of examining the electrical reliability against a soft error by using each of the above-mentioned first and second techniques.

In the above-mentioned first technique, the p-type semiconductor region can be used as the potential barrier region, but it cannot be formed in the channel forming region below the gate electrode. For this reason, although the amount of accumulated electric charge as information is increased, minority carriers intrude from the channel formation region portion by the increased amount or more, so that the soft error cannot be sufficiently prevented.

In addition, in the above-mentioned second technique, p used as the potential barrier region in order to sufficiently prevent the soft error.
It is necessary to configure the type semiconductor region with a high concentration. However, when the impurity concentration of the p-type semiconductor region is increased, the p-type impurity diffuses into the channel formation region, and the transfer and drive MISFs are formed.
It changes the threshold voltage of ET and lowers the electrical reliability.

An object of the present invention is to provide a technique capable of preventing a soft error and improving electrical reliability in a semiconductor integrated circuit device having a memory function.

Another object of the present invention is to provide a technique capable of reducing the memory cell area and improving the degree of integration in a semiconductor integrated circuit device having a memory function.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The following is a brief description of the outline of the typical inventions among the inventions disclosed in the present application.

A high-concentration second-conductivity-type first semiconductor region which is in contact with the high-concentration first conductive drain region of the drive MISFET forming the memory cell of the SRAM is provided below the drive-MISF.
A second conductivity type second semiconductor region having a high impurity concentration is provided at a position deeper than the first semiconductor region in the channel formation region portion of the ET.

[Action]

According to the above-mentioned means, the amount of charge accumulated as information in the first semiconductor region can be improved, so that a soft error can be prevented and the potential barrier region for minority carriers can be formed in the second semiconductor region as a driving MISFET.
Since the impurity concentration does not affect the threshold voltage of, it is possible to prevent soft error and improve electrical reliability.

〔Example〕

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to an SRAM including a memory cell that forms a flip-flop circuit with a high resistance load element and a driving MISFET.

A memory cell of an SRAM, which is an embodiment of the present invention, is shown in FIG. 1 (equivalent circuit diagram).

In all the drawings of the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

In FIG. 1, the SRAM memory cell is a pair of data lines.
It is provided at the intersection of DL and the word line WL. That is, the memory cell is composed of a flip-flop circuit having a pair of input / output terminals and transfer MISFETs Qs ₁ and Qs ₂ .

The transfer MISFET Qs has one end portion which is an input / output terminal of a flip-flop circuit, the other end portion which is a data line DL, and a gate electrode which is a word line.
Each is connected to WL.

The flip-flop circuit is composed of driving MISFETs Q ₁ and Q ₂ and high resistance load elements R ₁ and R ₂ . The drain region of the driving MISFET Q is connected to the power supply voltage line Vcc via the high resistance load element R. The source region of the driving MISFET Q is connected to the reference voltage wiring Vss.

For the power supply voltage wiring Vcc, for example, the operating voltage of the circuit is 5.0
[V] is applied to the reference voltage wiring Vss, for example,
The ground potential 0 [V] of the circuit is applied.

C is an information storage capacitance (parasitic capacitance), which is configured to store electric charges that become "1" and "0" information.

Next, a specific configuration of this embodiment will be described.

A memory cell of an SRAM according to an embodiment of the present invention is shown in FIG. 2 (plan view of relevant parts), and a cross section taken along line III-III of FIG. 2 is shown in FIG. In addition, FIG. 2, FIG. 5 and FIG.
In the figure, in order to make the structure of the SRAM of this embodiment easy to understand,
Insulating films other than the field insulating film provided between the conductive layers are not shown.

In FIGS. 2 and 3, 1 is an n ⁻ type semiconductor substrate made of single crystal silicon, and 2 is ap ⁻ type well region provided on a predetermined main surface portion of the semiconductor substrate 1. Well area 2
Is constituted by an impurity concentration of, for example, about 10 ¹⁶ [atoms / cm ³ ] as indicated by reference numeral 2 in FIG. 4 (impurity concentration distribution chart).

A field insulating film 3 and a p-type channel stopper region 4 are provided on the main surface of the well region 2 between the semiconductor element forming regions. Each of the field insulating film 3 and the channel stopper region 4 is particularly designed to electrically isolate the semiconductor elements, as shown in detail in FIG. 5 (plan view of the main part of the memory cell in a predetermined manufacturing process). It is configured.

The transfer MISFETs Qs ₁ and Qs ₂ and the drive MISFETs Q ₁ and Q ₂ , respectively,
In particular, as shown in detail in FIG. 6 (plan view of the main part of the memory cell in a predetermined manufacturing process), it is provided on the main surface of the well region 2 in the region surrounded by the field insulating film 3. That is, the MISFETQs, Q are composed of a well region 2 used as a channel formation region, a gate insulating film 6, a gate electrode 7, a pair of n-type semiconductor regions 8 and a pair of n ⁺ -type semiconductor regions 10. .

The gate electrode 7 is composed of, for example, a polycide film in which a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film is provided on the polycrystalline silicon film. As the gate electrode 7, a single-layer polycrystalline silicon film, a refractory metal silicide film, a refractory metal (Mo, Ti, Ta, W) film, or a refractory metal film is provided on the polycrystalline silicon film. It may be composed of a composite membrane.

One end of the gate electrode 7 of the driving MISFET Q is connected to the semiconductor region 10 through a connection hole 6A formed in the gate insulating film 6, so-called direct contact.

A word line (WL) 7A extending in the column direction on the field insulating film 3 is integrally formed with the gate electrode 7 of the transfer MISFET Qs.

Further, a reference voltage wiring (Vss) 7B formed of the same conductive layer as the gate electrode 7 is connected to the semiconductor region 10 used as the source region of the driving MISFETQ through the connection hole 6A.

The high-concentration semiconductor region 10 is used as a source region or a drain region. The semiconductor region 10 is configured by the impurity introduction mask 9 provided on the side portion of the gate electrode 7. The semiconductor region 10 is shown in FIG.
As indicated by the reference numeral 10, it is composed of n-type impurities (for example, arsenic) having a concentration of about 10 ²¹ [atoms / cm ³ ] and has a concentration of 0.25 [μm].
It is composed of a junction depth.

The low-concentration semiconductor region 8 is provided between the high-concentration semiconductor region 10 and the channel forming region (well region 2). Semiconductor region 8, so-called, LDD (L ightly D oped D r
ain) structure of MISFET.

In the memory cell configured in this manner, a p ⁺ type semiconductor region is formed on the main surface of the well region 2 of a portion (a portion forming the information storage capacitor C) that contributes to the improvement of the amount of stored charge of information.
11 are provided. That is, the semiconductor region 11 is
The semiconductor region 10 is formed on the main surface of the well region 2 below the semiconductor region 10 used as the drain region of the driving MISFETQ.
Configured to contact. In addition, the semiconductor region 11
Is a transfer MISF that contributes to the improvement of the amount of charge accumulated as information.
It may be provided below and in contact with the semiconductor region 10 used as a source region or a drain region of ETQs.

As shown by reference numeral 11 in FIG. 4, the semiconductor region 11 is made of p-type impurities (for example, boron) having a concentration of about 10 ¹⁸ [atoms / cm ³ ] and has a concentration of about 0.4 [μm]. It is configured to have a peak value of the impurity concentration at the depth of. That is, the semiconductor region 11 is configured so that the pn junction capacitance with the semiconductor region 10 can be sufficiently increased and the pn junction breakdown voltage can be sufficiently ensured. The semiconductor region 11 is formed in a self-aligned manner with respect to the gate electrode 7 with the impurity introduction mask 9 interposed in a region surrounded by a dashed line and denoted by reference numeral 11 in FIGS. 2 and 6. .

Since the semiconductor region 11 is provided at a shallow position so that the peak value of the impurity concentration is in contact with the drain region (semiconductor region 10), it is preferable not to actively provide it in the channel formation region. That is, the substrate effect constant increases, so that the threshold voltage increases, the write voltage decreases, and a stable write operation cannot be performed. The semiconductor region 11
In order to prevent the short channel effect, may be configured to positively wrap around the channel formation region side.

Thus, at least the p ⁺ -type (high concentration) contacting the main surface of the well region 2 below the semiconductor region 10 used as the drain region of the driving MISFETQ of the memory cell is in contact therewith.
By providing the semiconductor region 11, a high-concentration semiconductor region
Since the pn junction capacitance can be configured by 10 and the high-concentration semiconductor region 11, it is possible to improve the amount of charge accumulated as information.

Therefore, when minority carriers generated by α rays in the well region 2 enter the information storage capacitive element C, it is possible to prevent the inversion of information. Therefore, by preventing the soft error, the memory cell area is reduced. Since it can be reduced, the integration density of SRAM can be improved.

Further, a buried p ⁺ type semiconductor region is formed in the main surface portion of the well region 2 at a position deeper than the semiconductor region 11 in a portion forming the information storage capacitance C, at least a channel formation region portion of the driving MISFETQ. 5 are provided. The semiconductor region 5 is used for transfer and driving in order to reduce the substrate effect constant, reduce the threshold voltage, and improve the information writing voltage.
The MISFETs Qs, Q are formed at such a deep impurity concentration that they do not particularly affect the channel formation region. Specifically, the semiconductor region 5 is formed of p-type impurities (for example, boron) having a concentration of about 10 ¹⁷ to 10 ¹⁸ [atoms / cm ³ ] as shown by reference numeral 5 in FIG. , 0.7 [μm] in depth to have a peak value of the impurity concentration.

The semiconductor region 5 is formed, for example, in the substantially entire region of the memory cell (a region except under the field insulating film 3) by introducing p-type impurities using the field insulating film 3 as an impurity introduction mask. The semiconductor region 5 may be formed in a peripheral circuit other than the memory cell array, but in particular, it may not be formed in a portion in which it is desired to reduce the threshold voltage to increase the operating speed.

As described above, since the high-concentration semiconductor region 5 is provided at least in the main surface portion of the well region 2 at a position deeper than the semiconductor region 11 in the channel formation region of the driving MISFETQ, the threshold voltage of the driving MISFETQ is increased. Without any fluctuation
Since the potential barrier region (barrier) can be formed for the minority carriers generated by α rays, it is possible to prevent the minority carriers from entering the information storage capacitor C. Therefore, it is possible to prevent the SRAM soft error and improve the electrical reliability.

That is, in the SRAM of the present embodiment, the high-concentration semiconductor region 11 that improves the amount of charge storage and the high-concentration semiconductor region that is used as the potential barrier region are provided in the portion of the memory cell that constitutes the information storage capacitive element C. Since 5 and 5 are provided respectively,
It is possible to further prevent the soft error and improve the electrical reliability.

An interlayer insulating film 12 is provided on the MISFETQ and Qs to cover them. A connection hole 13 is provided in the interlayer insulating film 12 above the predetermined semiconductor region 10.

A power supply voltage wiring (Vcc) 14A and a high resistance load element (R ₁ , R ₂ ) 14B are provided on the interlayer insulating film 12 in the memory cell.

One end of the high resistance load element 14B is connected to the power supply voltage wiring 14A. The other end of the high resistance load element 14B has a connection hole 1
3 through MISFET Qs ₁ , Qs ₂ semiconductor region 10 and MISFET
It is electrically connected to the gate electrodes 7 of Q ₁ and Q ₂ .

The power supply voltage wiring 14A, each of the high resistance load element 14B,
It is composed of a conductive layer whose resistance value can be controlled by introducing impurities, for example, a polycrystalline silicon film. Power supply voltage wiring 14A
Is composed of a polycrystalline silicon film into which an n-type impurity (arsenic or phosphorus) for reducing the resistance value is introduced. The high resistance load element 14B is composed of a so-called non-doped polycrystalline silicon film in which the impurity for reducing the resistance value is not introduced. The high resistance load element 14B is configured in a region (showing a pattern of an impurity introduction mask) surrounded by a chain line indicated by reference numeral 14B in FIG.

Reference numeral 15 is an interlayer insulating film covering each of the power supply voltage wiring 14A and the high resistance load element 14B, and 16 is a connection hole provided by removing the insulating films 6, 12, 15 above the semiconductor region 10 of the MISFET Qs.

Reference numeral 17 is a data line DL, ▲ ▼, and MIS is passed through the connection hole 16.
Interlayer insulating film 1 electrically connected to the semiconductor region 10 of FETQs
The upper part of 5 is configured to extend in the row direction. The data line 17 is an aluminum film, a predetermined additive (Si, Cu)
Is formed of an aluminum film or the like.

Next, the manufacturing method of this embodiment will be briefly described with reference to FIGS. 7 to 11 (cross-sectional views of the essential part of the memory cell in each manufacturing process).

First, on the n ⁻ type semiconductor substrate 1 made of single crystal silicon,
A p ^- type well region 2 is formed.

Thereafter, the field insulating film 3 and the p-type channel stopper region 4 are formed on the main surface of the well region 2 between the semiconductor element forming regions.

Then, as shown in FIG. 7, a gate insulating film 6 is formed on the main surface of the well region 2 in the semiconductor element forming region.

After the step of forming the gate insulating film 6 shown in FIG. 7, a p ⁺ type semiconductor region 5 is formed in the main surface portion of the well region 2 as shown in FIG. The semiconductor region 5 uses, for example, 10
It is formed by introducing boron of about ¹³ [atoms / cm ² ] by ion implantation with energy of about 300 [KeV].

After the step of forming the semiconductor region 5 shown in FIG. 8, the predetermined gate insulating film 6 is removed and the connection hole 6A for direct contact is formed. After the step of forming the connection hole 6A, a p-type impurity for forming a p ⁺ -type semiconductor region may be introduced into the connection hole 6A portion. This connection hole
The 6A portion is used as a source region or a drain region of MISFETQs, Q, but since it is below the gate electrode 7, a semiconductor region 11 described later is not formed, so a p-type impurity is previously introduced. . That is, the introduction of p-type impurities is
This is performed in order to further increase the junction capacitance of the source region or the drain region of the MISFET Qs, Q and to improve the amount of charge storage that becomes information.

After that, the gate electrode 7 is formed on a predetermined upper portion of the gate insulating film 6, and the word line 7A and the reference voltage wiring 7B are formed. Gate electrode 7, word line 7A and reference voltage wiring
Each of 7B is composed of, for example, a polycide film in which a refractory metal silicide film 7b is formed on the polycrystalline silicon film 7a. The polycrystalline silicon film 7a is formed by CVD, for example, and the refractory metal silicide film 7b is formed by sputtering, for example.
Although not shown, the impurities diffused in the polycrystalline silicon film 7a to reduce the resistance value diffuse into the main surface of the well region 2 through the connection hole 6A and are used as a part of the source region or the drain region. To form an n-type semiconductor region.

Then, as shown in FIG. 9, an n-type semiconductor region 8 for forming an LDD structure is formed on the main surface of the well region 2 on the side of the gate electrode 7. The semiconductor region 8 is mainly
It is formed by using the gate electrode 7 and the field insulating film 3 as a mask for introducing impurities and introducing an n-type impurity (for example, phosphorus) by ion implantation.

After the step of forming the semiconductor region 8 shown in FIG. 9, an impurity introduction mask 9 is formed on the side portion of the gate electrode 7. The impurity introduction mask 9 can be formed, for example, by subjecting a silicon oxide film formed by CVD to anisotropic etching such as reactive ion etching.

After this, the gate electrode 7 with the impurity introduction mask 9 interposed
An n ⁺ type semiconductor region 10 used as a source region or a drain region is formed on the main surface of the well region 2 on the side of the. Further, as shown in FIG. 10, a p ⁺ type semiconductor region which is in contact with the main surface portion of the well region 2 on the side of the gate electrode 7 with the impurity introducing mask 9 interposed therebetween is formed below the semiconductor region 10. Forming 11.

The semiconductor region 10 is, for example, an n-type impurity (eg, arsenic).
Are formed by ion implantation. Semiconductor area
11 is, for example, boron of about 10 ¹³ [atoms / cm ² ]
It is formed by ion implantation with energy of about 130 [KeV].

Further, the semiconductor region 11 may be performed before the step of forming the semiconductor region 10.

After the step of forming the semiconductor region 11 shown in FIG. 10, an interlayer insulating film 12 is formed, a predetermined portion of the interlayer insulating film 12 is removed, and a connection hole 13 is formed.

Thereafter, as shown in FIG. 11, the power supply voltage wiring 14A and the high resistance load element 14B are formed on the interlayer insulating film 12.
Wiring 14A for power supply voltage and high resistance load element 14B consist of interlayer insulation film
A polycrystalline silicon film is formed on the entire surface of 12 and is formed depending on whether or not an n-type impurity that reduces the resistance value is introduced into this polycrystalline silicon film.

After the step of forming each of the power supply voltage wiring 14A and the high resistance load element 14B shown in FIG. 11, an interlayer insulating film 15 and a connection hole 16 are sequentially formed. Then, as shown in FIGS. 2 and 3, one semiconductor region 10 of the MISFET Qs is connected through the connection hole 16.
Data line on the interlayer insulating film 15 so that it is electrically connected to
Form 17.

By performing these series of manufacturing steps, the SR of this embodiment is
AM is completed. A protective film such as a passivation film may be formed after this.

Although the invention made by the present inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

For example, the present invention can be applied to an SRAM including a memory cell that forms a flip-flop circuit with a load element formed of a p-channel MISFET and a driving MISFET.

〔The invention's effect〕

The effects that can be obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

A high-concentration second-conductivity-type first semiconductor region that is in contact with the high-concentration first-conductivity-type drain region of the drive MISFET forming the SRAM memory cell is provided below the drive-MISF.
By providing a second semiconductor region of the second conductivity type having a high impurity concentration at a position deeper than the first semiconductor region in the channel formation region of the ET, the amount of charge accumulated as information in the first semiconductor region is improved. Therefore, soft error can be prevented, and the potential barrier region for minority carriers in the second semiconductor region can be driven by the MISF for driving.
Since it can be configured with an impurity concentration that does not affect the threshold voltage of ET, it is possible to prevent soft errors and improve electrical reliability.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a memory cell of an SRAM which is an embodiment of the present invention, and FIG. 2 is a main part plan view showing a memory cell of an SRAM which is an embodiment of the present invention. 2 is a cross-sectional view taken along the line III-III in FIG. 2, FIG. 4 is an impurity concentration distribution diagram, and FIGS. 5 and 6 are the main points in a predetermined manufacturing process of the memory cell shown in FIG. Partial plan views and FIGS. 7 to 11 are cross-sectional views of essential parts in respective manufacturing steps of a memory cell of an SRAM according to an embodiment of the present invention. In the figure, 2 ... Well region, 6 ... Gate insulating film, 7 ... Gate electrode, 7A ... Word line (WL), 7B, Vss ... Reference voltage wiring,
5,8,10,11 ... Semiconductor region, 12,15 ... Interlayer insulating film, 6A, 13,16
... Connection holes, 14B, R ... High resistance load elements, 14A, Vcc ... Power supply voltage wirings, 17, DL ... Data lines, Q ... MISFET.

Claims (7)

[Claims] 1. A transfer MISFET and a drive MI are provided on a main surface of a first conductive type first semiconductor region electrically isolated from other regions.
A semiconductor integrated circuit device comprising a memory cell composed of a flip-flop circuit having an SFET, wherein a main surface portion of a first semiconductor region below a drain region of the driving MISFET is in contact with the drain region, A second semiconductor region having the same conductivity type as that of the first semiconductor region and a higher impurity concentration than that of the first semiconductor region is provided, and a second semiconductor region having a channel formation region of the driving MISFET is provided on a main surface portion of the first semiconductor region deeper than the second semiconductor region. A semiconductor integrated circuit device comprising a third semiconductor region having the same conductivity type as that of the first semiconductor region and an impurity concentration higher than that of the third semiconductor region. 2. The second semiconductor region is configured so as to improve the amount of charge accumulated as information, and the third semiconductor region constitutes a potential barrier region for minority carriers in the first semiconductor region. The semiconductor integrated circuit device according to claim 1, which is characterized in that. 3. The second semiconductor region is also provided on the main surface portion of the first semiconductor region below the source region or the drain region of the transfer MISFET, which contributes to the improvement of the amount of charge accumulated as information. The semiconductor integrated circuit device according to claim 1 or 2, which is characterized in that. 4. The third semiconductor region according to claim 1, wherein the third semiconductor region is provided on a main surface portion of the first semiconductor region in substantially the entire area of the memory cell. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to any one of claims 1 to 4, wherein the memory cell constitutes a static random access memory. 6. The second semiconductor region according to claim 1, wherein the second semiconductor region is configured in a self-aligned manner with respect to the gate electrode of the driving MISFET. Semiconductor integrated circuit device. 7. The third semiconductor region is an MI for transfer and drive.
The semiconductor integrated circuit device according to any one of claims 1 to 6, wherein the semiconductor integrated circuit device is configured in a self-aligning manner with respect to a field insulating film that electrically separates each of the SFETs.