JPH0740658B2 - Address generation circuit - Google Patents

Description

The present invention relates to an address generation circuit of a digital signal processing processor.

(Prior Art) In filtering, which is often used in digital signal processing, it is necessary to shift input data every sampling time. However, it takes time to actually shift in memory, so it is realized by moving the pointer (DP) without moving the actual data. This is called a virtual shift. FIG. 2 is a diagram for explaining the concept of virtual shift.

As an example of the virtual shift shown in FIG. 2, 4 shown in the equation (1) is used.
This will be explained in the next FIR filter.

As shown in FIG. 2, data x (t) to x at time t
(T-3) is on the memory, and the pointer (DP) is x
It is assumed that (t) is shown. From this state, in order to calculate the output y (t) of the equation (1), x (t) to x (t-
1), x (t-2), and (x-3) can be sequentially accessed by decrementing the pointer (DP) by one. Then, at time (t + 1), the pointer (DP) is incremented by “+4”, and new input data x (t + 1)
To store. Therefore, x (t) and x (t used at time t
-1), x (t-2), and x (t-3) do not move in the memory, and the pointer pointing to x (t + 1) may be decremented by 1 and sequentially accessed. The realization of the shift operation by using the pointer without moving the data on the memory in this way is called virtual shift.

Conventionally, as the address generation circuit of the digital signal processing processor, Fujitsu MB8764 general-purpose digital signal processing LS
I User Manual (issued in April 1984), with index modification (hereinafter referred to as Conventional Example 1), and internal
Conference on Acoustics Speech
And Signal Processing '85 Proceedings "Architecture and Applications of Second Generation Digital Signal Processor" (International Conference on Acoustics, Speech
and Signal Procesesing '85 Architecture and Applic
ations of a Second-Generation Digital Signal Proc
ESSOR) (issued in April 1985), such as Texas Instruments TMS32020, which uses indirect addressing by a register file (hereinafter referred to as Conventional Example 2) is known.

(Problems to be Solved by the Invention) A digital signal processing processor is configured to efficiently realize a so-called multiply-accumulate operation, in which multiplications are accumulated, so that a recent processor has two RAMs.
Many have one or have a two-port RAM configuration. In addition, as LSI technology advances, processors with more RAM are being developed. In such a situation, the conventional address generating circuit has the following drawbacks.

The Fujitsu MB8764 described in Conventional Example 1 employs so-called index modification in which the effective address is generated by the sum of the counter value and the value specified by the literal field of the instruction. Therefore, when calculating the equation (1), the pointer is not moved while the time t is calculated, and x (t-
1) is (pointer-1), i.e. x in the counter
The address of (t) is given, and x (t-1) is realized by designating "-1" in the literal field of the instruction. The same applies to x (t-2) and x (t-3).

In this case, as many literal fields as the number of address bits for index modification are needed during the instruction. If there is only one RAM and the capacity is small, the literal field will be a few bits, but if there is a large amount of memory, or if there are many memory spaces, it is possible to specify a very long address during instruction. Need a field of. In fact, MB8764 uses a length of 14 pits for the literal field of two RAMs.

In order to solve this drawback, the Texas Instruments TMS32020 of Conventional Example 2 has a 5-file register file as shown in FIG. 5, and employs indirect addressing in which one of them is used as an effective address. In FIG. 5, reference numeral 100 is a 5-word register file, and 101 is an arithmetic logic operation circuit (ALU) capable of performing "+1" or "-1" or (A input + B input) operation on the A input. When the equation (1) is calculated by the address generating circuit shown in FIG. 5, the value of the pointer (DP) is stored in one word of the register file 100 as an initial value, and the value is set as the first effective address. Then, the value "+4" is stored in one word different from the one word having the pointer value of the register file 100. Next, the one word having the value of the pointer is used for the function of the arithmetic logic operation circuit 101. Therefore, the data storage address necessary for the equation (2) is generated by decrementing by 1. However, in order to calculate the output at the time (t + 1), one word having a pointer value and "+" are added.
It is necessary to specify 1 word having a value of 4 "and generate correct addresses to be input to the A input and the B input of the arithmetic logic operation circuit 101 respectively.
Unless one of the register files is incremented (ie, "+1") or decremented ("-1"), it must be updated with another register in the register file. Therefore, a field for designating two registers is required during the instruction.

However, in order to avoid this, TMS32020 uses one of the register files by using the register file command register.
It has a structure that specifies a word. However, in this case, this register file specification register must be updated every time the used register is updated, and the data bus is occupied by the update, which causes another drawback that the processing efficiency of the processor is deteriorated. It was

The object of the present invention is to reduce the number of control bits, and
An object of the present invention is to provide an address circuit that realizes indirect addressing suitable for digital signal processing.

(Means for Solving Problems) An address generating circuit of the present invention is a register file for storing data input from a data input terminal, data read from the register file, and an input from the data input terminal. Of the selected data, an arithmetic logic operation circuit that performs an arithmetic logic operation on the first data and the second data, and a register that stores the output data of the arithmetic product logic operation circuit. Becomes the first
Data is output to the selection circuit, and the second data is data read from the register.

(Operation) When the instalation length is limited, the direct addressing or the index modification addressing is disadvantageous because the addressing field in the indirection is used. Indirect addressing is an advantage. However, indirect addressing requires updating the pointer every time, and the updating method affects the addressing capability and the processor efficiency.
As mentioned earlier, in TMS32020, register file 2
Updating was realized by adding words. This is because the method of designating these two words cannot control the number of control bits and the limited instructions. Therefore, in order to solve this problem, there is only one register that stores the effective address, and a register file is prepared for updating. This is realized by designating one word of this register file. As a result, only one word of the register file needs to be specified, and the control input that specifies the operation of the arithmetic logic operation circuit and the selection circuit is all that is required. Indirect addressing suitable for digital signal processing can be realized.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
Is a data input terminal, 2 is a register file, 3 is a selection circuit, 4 is an arithmetic logic operation circuit, 5 is a register, 6 is an effective address output terminal, and 7 is a control input terminal.

Realization of this virtual shift will be described with reference to the timing charts shown in FIGS. 1 and 6.

First, this virtual shift requires two pointer value updates, "-1" to decrement the pointer and "+4" to store the new input sample.

Therefore, in the cycle of clock 0 shown in FIG. 6, “−1” is input from the data input terminal 1 and in the cycle of clock 1, “+4” is input from the data input terminal 1 to the address 0 of the register file 2,
Store at address 1 respectively. Next, you need to load the pointer with an initial value. However, since this initial value is used only once, in the cycle of clock 2 the control input terminal 7
The selection circuit 3 is switched via the, and the address of x (t) is directly input from the data input terminal 1 to the arithmetic logic operation circuit 4. At this time, in the arithmetic logic operation circuit 4, the input data through is selected via the control input terminal 7, and the input from the selection circuit 3 becomes the output of the arithmetic logic operation circuit 4 as it is. Then, in the register 5, it is set to the output of the arithmetic logic operation circuit 4 by the instruction applied through the control input terminal 7. In this way, the initial value of the pointer DP is loaded, and x
(T) can be referred to.

The pointer then needs to be decremented to reference x (t-1). This is because "-1" is read from the address 0 of the register file in the cycle of clock 3 via the control input terminal 7, and the arithmetic logic operation circuit 4 holds the current pointer value through the selection circuit 3 and adds it to the register output. Do. In this way, the output of the arithmetic logic operation circuit 4 becomes the value obtained by subtracting 1 from the pointer value and is stored in the register by the signal through the control input terminal 7. In this way, pointer decrementing can be realized. Similarly, since x (t-2) is referenced in the cycle of clock 4 and x (t-3) is referenced in the cycle of clock 5, the pointer is decremented. Thus x (t) to x
With reference to (t-3), y (t) is calculated according to the equation (1).

After the calculation of y (t) is completed, it is necessary to store the input data of x (t + 1) in the memory. Therefore, add "+4" to the pointer. First, "+4" stored in the first address is read from the register file 2 in the cycle of the clock 6 through the control input terminal 7 and is used as one input of the arithmetic logic operation circuit 4 through the selection circuit 3. The arithmetic logic operation circuit 4 adds "+4" read from the register file and the output of the register 5 holding the current pointer value and outputs the result. The register 5 holds the output of the arithmetic and logic operation circuit 4 according to an instruction via the control input terminal 7. In this way, (pointer value + 4) is realized.

FIG. 3 is a specific example of the arithmetic logic operation circuit 4 of FIG. 1, and is composed of an adder 10 and a selection circuit 11. In the explanation of the operation of the above-mentioned embodiment, when the initial value of the pointer is loaded into the register 5, the arithmetic logic operation circuit 4 needs the input data through. This can be realized by switching the selection circuit 11, selecting the "0" input, and calculating (input data +0) with the adder.

The number of bits of the control signal added from the control input terminal 7 necessary for designating this series of operations is 2 bits for register loading / updating / invariant as the operation mode, and 3 bits to indicate the address of the register file. 2 words for words, 3 bits for 7 words.

At this time, the data input terminal 1 is selected by the selection circuit 3 shown in FIG.
When the input from is selected, it is assigned as the highest address of the register file. As described above, the address generating circuit of the present invention is realized by the control input of 4 bits when the register file is 3 words and 5 bits when the register file is 7 words.

FIG. 4 is a second specific example of the arithmetic logic operation circuit 4 of FIG. 1, and is composed of an adder / subtractor 20 and a selection circuit 11. This allows the previous operation mode to be the same 2 bits as load, addition, subtraction, and invariant, but the contents of the register file do not need to store "+ n" and "-n" separately, and the register file can be small. Can be realized.

The present invention can be implemented as described above.

Also, in the arithmetic logic operation circuit 4 of FIG. 1, a circuit for stopping the carry propagation of addition or subtraction on the way is provided so as to cyclically refer to a limited memory, which is also a part of the present invention. is there.

(Effect) The effect of the present invention is that by updating one register holding an effective address using a register file and an arithmetic logic unit, it is suitable for digital signal processing, and the number of bits of a control signal is small. It is possible to realize indirect addressing. In the conventional example 1, an address field of 14 bits was required during the instruction. Further, in the conventional example 2, the address field is 7 bits, but since the register file designation register for indicating which of the 5 word register file is referred to is used, the data is not available when the other register file is referred to. I occupy the bus. However, by using the address generation circuit shown in the embodiment of the present invention, even in the case of a 7-word register file, it is only necessary to have an address field of 5 bits in the instruction, and moreover, data for updating the address is required. It does not occupy the bus.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining virtual shift, and FIGS. 3 and 4 are detailed blocks of a concrete example of an arithmetic logic operation circuit in the embodiment of FIG. 5 and 5 are block diagrams of a conventional example, and FIG. 6 is a timing chart of the embodiment of FIG. In FIG. 1, 1 is a data input terminal, 2 is a register file, 3 is a selection circuit, 4 is an arithmetic logic operation circuit, 5 is a register, 6 is an effective address output terminal, and 7 is a control input terminal.

Claims (1)

[Claims] 1. A register file for storing data input from a data input terminal, and a selection circuit for selecting one of data read from the register file and data input from the data input terminal. An arithmetic logic operation circuit for performing an arithmetic logic operation on first data and second data, and a register for storing output data of the arithmetic product logic operation circuit, wherein the first data is the output of the selection circuit. The address generating circuit is characterized in that the second data is data read from the register.