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JPH0740674B2 - Two-wire insulated transmission circuit - Google Patents
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JPH0740674B2 - Two-wire insulated transmission circuit - Google Patents

Two-wire insulated transmission circuit

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Publication number
JPH0740674B2
JPH0740674B2 JP13225086A JP13225086A JPH0740674B2 JP H0740674 B2 JPH0740674 B2 JP H0740674B2 JP 13225086 A JP13225086 A JP 13225086A JP 13225086 A JP13225086 A JP 13225086A JP H0740674 B2 JPH0740674 B2 JP H0740674B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
output
current
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13225086A
Other languages
Japanese (ja)
Other versions
JPS62289018A (en
Inventor
博光 桜井
Original Assignee
電気化学計器株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 電気化学計器株式会社 filed Critical 電気化学計器株式会社
Priority to JP13225086A priority Critical patent/JPH0740674B2/en
Publication of JPS62289018A publication Critical patent/JPS62289018A/en
Publication of JPH0740674B2 publication Critical patent/JPH0740674B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 産業上の利用分野 本発明は、例えば溶液のpH又は溶存酸素濃度の測定用セ
ンサの出力信号等を遠隔地点に設けた受信器に伝送する
に好適な二線式絶縁伝送回路に関するものである。
TECHNICAL FIELD The present invention relates to a two-wire insulation system suitable for transmitting, for example, an output signal of a sensor for measuring the pH of a solution or a dissolved oxygen concentration to a receiver provided at a remote location. The present invention relates to a transmission circuit.

従来の技術 第3図は、従来の二線式絶縁伝送回路を示す図で、T1
びT2は信号入力端子で、インピーダンス変換回路又は電
流・電圧変換回路等を介してpH又は溶存酸素濃度の測定
用センサの出力信号電圧等が加えられる。V/Fは電圧・
周波数変換回路、PSは直流源で、整流回路、平滑回路及
び出力安定化回路等により成る。TF1及びTF2は絶縁トラ
ンス、F/Vは周波数・電圧変換回路、V/Iは電圧・電流変
換回路、OSCは発振回路、T3及びT4は信号出力端子、L1
及びL2は伝送線路、T5及びT6は受信側の入出力端子、RX
は指示計又は記録計等を設けた受信器、Eは受信側に設
けた直流電源である。
Prior art Fig. 3 is a diagram showing a conventional two-wire insulation transmission circuit, in which T 1 and T 2 are signal input terminals, and pH or dissolved oxygen concentration is passed through an impedance conversion circuit or a current / voltage conversion circuit. The output signal voltage and the like of the measurement sensor of 1 are added. V / F is voltage
The frequency conversion circuit and PS are DC sources, and are composed of a rectifying circuit, a smoothing circuit, an output stabilizing circuit, and the like. TF 1 and TF 2 are isolation transformers, F / V is frequency / voltage conversion circuit, V / I is voltage / current conversion circuit, OSC is oscillator circuit, T 3 and T 4 are signal output terminals, L 1
And L 2 are transmission lines, T 5 and T 6 are input / output terminals on the receiving side, and R X
Is a receiver provided with an indicator or a recorder, and E is a DC power supply provided on the receiving side.

受信側に設けた直流電源Eの出力電圧は、受信器RX、入
出力端子T5及びT6、伝送線路L1及びL2、信号出力端子T3
及びT4、電圧・電流交換回路V/Iを介して発振回路COCに
加えられ、これを発振せしめる。発信回路OSCの発振出
力は絶縁トランスTF2を介して直流源PSに加えられ、整
流平滑された後、安定化され、直流電源Eの出力電圧と
絶縁された直流電圧が電圧・周波数変換回路V/Fに加え
られて、これを作動せしめる。
The output voltage of the DC power source E provided on the receiving side is the receiver R X , the input / output terminals T 5 and T 6 , the transmission lines L 1 and L 2 , and the signal output terminal T 3
And T 4, applied to the oscillation circuit COC via a voltage-current exchange circuit V / I, allowed to oscillate it. The oscillation output of the oscillator circuit OSC is applied to the DC source PS via the isolation transformer TF 2 , rectified and smoothed, and then stabilized, and the DC voltage insulated from the output voltage of the DC power source E is converted into the voltage / frequency conversion circuit V. Added to / F to activate this.

一方、例えばpH又は溶存酸素濃度測定用センサ等の出力
信号が、インピーダンス変換回路又は電流・電圧回路等
を介して信号入力端子T1及びT2に加えられ、電圧・周波
数回路V/Fにおいて入力信号電圧の大きさに比例した周
波数の交流電圧に変換され、絶縁トランスTF1を介して
周波数・電圧変換回路F/Vに加えられる。周波数・電圧
変換回路F/Vに加えられた交流電圧は入力信号電圧の大
きさに比例した直流電圧に変換された後、電圧・電流変
換回路V/Iにおいて直流電流に変換され、出力端子T3
びT4、伝送線路L1及びL2、入出力端子T5及びT6、直流電
流Eを介して受信器RXに供給される。
On the other hand, for example, an output signal of a sensor for measuring pH or dissolved oxygen concentration, etc. is added to the signal input terminals T 1 and T 2 via an impedance conversion circuit, a current / voltage circuit, etc., and input at a voltage / frequency circuit V / F. It is converted into an AC voltage with a frequency proportional to the magnitude of the signal voltage, and is applied to the frequency / voltage conversion circuit F / V via the insulating transformer TF 1 . The AC voltage applied to the frequency / voltage conversion circuit F / V is converted to a DC voltage proportional to the magnitude of the input signal voltage, then converted to a DC current in the voltage / current conversion circuit V / I, and output terminal T 3 and T 4 , transmission lines L 1 and L 2 , input / output terminals T 5 and T 6 , and a direct current E are supplied to the receiver R X.

発明が解決しようとする問題点 上記のような二線式絶縁伝送回路を用いてpH又は溶存酸
素濃度等の遠隔指示又は記録を行う場合或は指示又は記
録を行うと共にpH又は溶存酸素濃度等のプロセス制御を
行う場合には、一般に出力信号電流の下限を4mAに、上
限を20mAに定めているので、出力信号電流が4mAの場合
には電圧・周波数変換回路V/F及び周波数・電圧変換回
路F/V等の伝送回路として、消費電流が4mAで動作し得る
回路を用いる必要があるが、集積回路を以て形成された
従来における消費電流の小なる電圧・周波数変換回路及
び周波数・電圧変換回路等は温度特性が悪く、変換誤差
を免れることが出来ない。
Problems to be Solved by the Invention When remote indication or recording of pH or dissolved oxygen concentration, etc. is performed using the above-mentioned two-wire insulated transmission circuit, or when the indication or recording is performed and pH or dissolved oxygen concentration, etc. When performing process control, the lower limit of the output signal current is generally set to 4 mA and the upper limit is set to 20 mA, so if the output signal current is 4 mA, the voltage / frequency conversion circuit V / F and frequency / voltage conversion circuit It is necessary to use a circuit that can operate at a consumption current of 4 mA as a transmission circuit for F / V, etc., but a voltage / frequency conversion circuit and a frequency / voltage conversion circuit, etc. with a small consumption current in the past formed by an integrated circuit, etc. Has poor temperature characteristics and cannot avoid conversion errors.

このような欠点を除くために、従来は温度特性の一致し
た電圧・周波数変換回路及び周波数・電圧変換回路を用
いることにより温度変化に基づく変換誤差を互いに打ち
消さしめて回路全体の温度特性の改善を図っているが、
温度特性の一致した変換回路を選び出すことは極めて困
難である。
In order to eliminate such a drawback, conventionally, by using a voltage / frequency conversion circuit and a frequency / voltage conversion circuit having the same temperature characteristics, the conversion errors due to temperature changes are canceled out to improve the temperature characteristics of the entire circuit. However,
It is extremely difficult to select a conversion circuit having the same temperature characteristics.

問題点を解決するための手段 本発明においては、入力信号電圧に対応する電流を積分
回路に流入せしめ、この積分回路の出力電圧を第1の比
較器に加え、この第1の比較器の出力電圧をリセット信
号としてCMOS形リセット・セット・フリップフロップ回
路に加え、その反転に応じて充放電用コンデンサの充放
電を制御し、この充放電用コンデンサの充電電圧に応じ
て第2の比較器から送出される出力電圧をセット信号と
して前記CMOS形リセット・セット・フリップフロップ回
路に加え、その反転に応じて前記積分回路に流入する電
流の向きを逆転せしめることにより入力信号電圧を矩形
波電圧に変換せしめ、この矩形波電圧を絶縁トランスを
介して第3の比較器に加え、この第3の比較器の出力電
圧を電流に変換せしめるように構成することにより上記
従来の欠点を除き得る二線式絶縁伝送回路を実現したも
のである。
Means for Solving the Problems In the present invention, a current corresponding to an input signal voltage is caused to flow into an integrating circuit, the output voltage of the integrating circuit is applied to a first comparator, and the output of the first comparator is added. The voltage is applied as a reset signal to the CMOS type reset set flip-flop circuit, the charging / discharging of the charging / discharging capacitor is controlled according to its inversion, and the second comparator is operated according to the charging voltage of this charging / discharging capacitor. The output voltage that is sent is applied as a set signal to the CMOS reset set flip-flop circuit, and the input signal voltage is converted into a rectangular wave voltage by reversing the direction of the current that flows into the integrating circuit according to its inversion. This rectangular wave voltage is applied to the third comparator via an insulating transformer, and the output voltage of the third comparator is converted into a current. Ri is obtained by realizing the two-wire insulated transmission circuit for obtaining Except above conventional drawbacks.

作用 前記のように構成することにより、入力信号電圧を変換
して得られた矩形波電圧のデューテイ比が入力信号電圧
の大きさに比例し、この矩形波電圧を変換して得られた
出力電流の大きさは前記デュウーイ比に比例することと
なる。
Action With the above configuration, the duty ratio of the rectangular wave voltage obtained by converting the input signal voltage is proportional to the magnitude of the input signal voltage, and the output current obtained by converting the rectangular wave voltage. Will be proportional to the Duoi's ratio.

実施例 第1図は、本発明の一実施例を示す図で、T1及びT2は信
号入力端子で、例えばインピーダンス変換回路又は電流
・電圧変換回路(何れも図示していない)等を介してpH
又は溶存酸素濃度の測定用センサ等(何れも図示してい
ない)の出力信号電圧が加えられる。R1及びR2は入力抵
抗、Q1は低消費電力形の演算増幅器で、積分コンデンサ
C1と共に積分回路を形成する。R3は充電抵抗、C2は充放
電用コンデンサ、Q2及びQ3は比較器で、それぞれ例えば
低消費電力形の演算増幅器より成る。R4、R5及びR6は分
圧抵抗で、各抵抗値を例えば互いにほぼ等しくなし、各
分電圧を基準電圧として比較器Q2及びQ3に加えるように
形成してある。FFはCMOS形リセット・セット・フリップ
フロップ回路(以下、RS−フリップフロップ回路FFと略
記する)、TR1は開閉素子で、例えば適当なトランジス
タ等より成る。R7はベース抵抗、C3は直流阻止用コンデ
ンサ、TF1は絶縁トランス、Q4は例えば低消費電力形の
演算増幅器より成る比較器、R8及びR9は分圧抵抗で、例
えば両抵抗値を互いにほぼと等しくなし、その分電圧を
基準電圧として比較器Q4に加えるように形成してある。
Q5はCMOS形緩衝増幅器、R10は入力抵抗、Q6は低消費電
力形の演算増幅器、TR2はトランジスタで、例えばNチ
ャンネル電界効果トランジスタより成る。TR3も亦トラ
ンジスタで、例えばPNP形トランジスタより成る。Z1
びZ2はツェナダイオード又はリファレンスダイオード、
C4は平滑用コンデンサ、R11は平滑用抵抗、R12は電流制
限抵抗、CCは定電流回路、OSC発振回路、C5は結合コン
デンサ、TF2は絶縁トランス、PSは正負の直流源で、整
流回路、平滑回路及び出力安定化回路等より成る。T3
びT4は信号出力端子、L1及びL2は伝送線路、T5及びT6
受信側の入出力端子、RXは指示又は記録計等を備えた受
信器、Eは直流電源である。
Embodiment FIG. 1 is a view showing an embodiment of the present invention, in which T 1 and T 2 are signal input terminals, for example, through an impedance conversion circuit or a current / voltage conversion circuit (neither is shown). PH
Alternatively, an output signal voltage of a sensor for measuring dissolved oxygen concentration or the like (none of which is shown) is applied. R 1 and R 2 are input resistors, Q 1 is a low power consumption operational amplifier, integrating capacitor
Form an integrating circuit with C 1 . R 3 is a charging resistor, C 2 is a charging / discharging capacitor, Q 2 and Q 3 are comparators, each consisting of, for example, a low power consumption operational amplifier. R 4 , R 5 and R 6 are voltage-dividing resistors, and their respective resistance values are, for example, substantially equal to each other, and are formed so that the respective divided voltages are applied as reference voltages to the comparators Q 2 and Q 3 . FF is a CMOS type reset set flip-flop circuit (hereinafter abbreviated as RS-flip-flop circuit FF), and TR 1 is an opening / closing element, which is composed of, for example, an appropriate transistor. R 7 is a base resistor, C 3 is a DC blocking capacitor, TF 1 is an insulating transformer, Q 4 is a comparator consisting of a low power consumption operational amplifier, R 8 and R 9 are voltage dividing resistors, for example, both resistors. The values are made substantially equal to each other, and the voltage is applied to the comparator Q 4 as a reference voltage.
Q 5 is a CMOS type buffer amplifier, R 10 is an input resistor, Q 6 is a low power consumption type operational amplifier, and TR 2 is a transistor, for example, an N-channel field effect transistor. TR 3 is also a transistor, for example a PNP transistor. Z 1 and Z 2 are Zener diodes or reference diodes,
C 4 is a smoothing capacitor, R 11 is a smoothing resistor, R 12 is a current limiting resistor, CC is a constant current circuit, OSC oscillator circuit, C 5 is a coupling capacitor, TF 2 is an insulating transformer, PS is a positive and negative DC source. , A rectifying circuit, a smoothing circuit, an output stabilizing circuit, and the like. T 3 and T 4 are signal output terminals, L 1 and L 2 are transmission lines, T 5 and T 6 are input / output terminals on the receiving side, R X is a receiver equipped with an indicator or recorder, and E is a DC power supply. Is.

受信側の直流電源Eの出力電圧を受信器RX、入出力端子
T5及びT6、伝送線路L1及びL2、信号出力端子T3及びT4
介して定電流回路CCに加えてツェナダイオードZ1及びZ2
に作動電流を供給すると、ツェナダイオードZ1及びZ2
生ずるツェナ電圧(高レベル電圧を+VDD、中間レベル
電圧を+V3及び低レベル電圧をV0とする)が発振回路OS
Cに加えられ、その発振出力が結合コンデンサC5及び絶
縁トランスTF2を介して直流源PSに加えられ、整流平滑
された後、安定化され、受信側の直流電源Eの電圧と絶
縁された正負の直流電圧+VCC及び−VEEが、演算増幅器
Q1以下の各回路素子に作動電圧として供給される。尚、
後述するように演算増幅器Q6の出力によりトランジスタ
TR3が導通せしめられた後は、トランジスタTR3を介して
ツェナダイオードZ1及びZ2に作動電流が供給される。
The output voltage of the DC power supply E on the receiving side is applied to the receiver R X
Zener diodes Z 1 and Z 2 in addition to the constant current circuit CC via T 5 and T 6 , transmission lines L 1 and L 2 , and signal output terminals T 3 and T 4.
When an operating current is supplied to the oscillator circuit, the Zener voltage (high level voltage is + V DD , intermediate level voltage is + V 3 and low level voltage is V 0 ) generated in the zener diodes Z 1 and Z 2 is generated by the oscillation circuit OS.
It is added to C, and its oscillation output is applied to the DC source PS via the coupling capacitor C 5 and the isolation transformer TF 2 , rectified and smoothed, then stabilized, and insulated from the voltage of the DC power source E on the receiving side. Positive and negative DC voltage + V CC and −V EE
It is supplied as an operating voltage to each circuit element under Q 1 . still,
As will be described later, the output of operational amplifier Q 6
After TR 3 is turned on, an operating current is supplied to the Zener diodes Z 1 and Z 2 via the transistor TR 3 .

一方、例えばpH又は溶存酸素濃度等の測定用センサの出
力信号がインピーダンス変換回路又は電流・電圧変換回
路を介して信号入力端子T、及びT2に加えられると、Ei
/R1(Eiは正の入力信号電圧の大きさ、R1は入力抵抗R1
の抵抗値で、以下、各抵抗の抵抗値及び各コンデンサの
容量等を各抵抗及び各コンデンサ等の表示符号と同一の
記号を以て表わす)なる電流が積分コンデンサC1回路に
流れ、演算増幅器Q1の出力電圧は第2図(イ)に波形図
を示すように、低レベル電圧−VEEに向って直線的に低
下しながら比較器Q3に加えられる。比較器Q3に加えられ
る演算増幅器Q1の出力電圧が、比較器Q3に加えられる基
準電圧−V1によって定まるスレッシュホールドレベル以
下に下ると、比較器Q3の出力が高レベル電圧となっRS−
フリップフロップ回路FFのリセット信号入力端子Rに加
えられ、RS−フリップフロップ回路FFのQ端子の出力電
圧が低レベル電圧−VEEとなる。
On the other hand, when the output signal of the sensor for measuring pH or dissolved oxygen concentration is applied to the signal input terminals T and T 2 via the impedance conversion circuit or the current / voltage conversion circuit, E i
/ R 1 (E i is the magnitude of the positive input signal voltage, R 1 is the input resistance R 1
In the following, the resistance value of each resistor and the capacitance of each capacitor are represented by the same symbols as the reference symbols of each resistor and each capacitor, etc.), and a current flows through the integrating capacitor C 1 circuit, and the operational amplifier Q 1 As shown in the waveform diagram of FIG. 2 (a), the output voltage of is applied to the comparator Q 3 while decreasing linearly toward the low level voltage −V EE . The output voltage of the operational amplifier Q 1 applied to the comparator Q 3 is, when down below the comparator Q is determined by the reference voltage -V 1 applied to the 3 threshold level, the output of the comparator Q 3 is a high level voltage RS-
It is applied to the reset signal input terminal R of the flip-flop circuit FF, and the output voltage of the Q terminal of the RS-flip-flop circuit FF becomes the low level voltage -V EE .

入力信号電圧Eiの大きさ、入力抵抗R1及びR2の各抵抗
値、低レベル電圧−VEEの大きさの関係が、 (Ei/R1−VEE/R2)<0 満足する間は、積分コンデンサC1回路に、 Ei/R1−VEE/R2 になる電流が流れ、演算増幅器Q1の出力電圧は高レベル
電圧+VCCに向って直線的に上昇する。
The relationship between the magnitude of the input signal voltage E i, the resistance values of the input resistors R 1 and R 2 , and the magnitude of the low-level voltage −V EE satisfies (E i / R 1 −V EE / R 2 ) <0 During this period, a current of E i / R 1 −V EE / R 2 flows through the integrating capacitor C 1 circuit, and the output voltage of the operational amplifier Q 1 linearly increases toward the high level voltage + V CC .

{第2図(イ)} 前記のようにRS−フリップフロップ回路FFにおけるQ端
子出力電圧が低レベル電圧になると、開閉素子TR1が開
放し、共通端子及び充電抵抗R3を介して充放電用コンデ
ンサC2が充電され、その充電電圧、即ち、比較器Q2にお
ける非反転入力端子の電位VC2は次式のように上昇する
{第2図(ロ)} 上式において、tは開閉素子TR1の開放からの経過時間
(秒)である。
{FIG. 2 (a)} As described above, when the output voltage of the Q terminal in the RS-flip-flop circuit FF becomes a low level voltage, the switching element TR 1 opens, and charging / discharging is performed via the common terminal and the charging resistor R 3. The charging capacitor C 2 is charged, and its charging voltage, that is, the potential V C2 of the non-inverting input terminal of the comparator Q 2 rises as in the following equation {Fig. 2 (b)}. In the above equation, t is the elapsed time (seconds) from the opening of the switching element TR 1 .

比較器Q2の非反転入力端子の電位VC2が、比較器Q2の基
準電圧−V2により定まるスレッシュホールドレベル以上
になると、比較器Q2の出力電圧が高レベル電圧に転じて
RS−フリップフロップ回路FFのセット信号入力端子Sに
加えられ、RS−フリップフロップ回路FFのQ端子出力が
高レベル電圧となって開閉素子TR1が閉成し、充放電用
コンデンサC2が放電すると共に{第2図(ロ)}、積分
コンデンサC1回路に再びEi/R1なる電流が流れ、演算増
幅器Q1の出力電圧は第2図(イ)に示すように再び下降
に転じ、以下、上記の動作が繰り返され、RS−フリップ
フロップ回路FFにおけるQ端子出力は第2図(ハ)に示
すように変化することとなる。
Comparator Q potentials V C2 of the non-inverting input terminal of the 2, at the threshold level or higher which is determined by the reference voltage -V 2 of the comparator Q 2, the output voltage of the comparator Q 2 is turned to a high level voltage
It is applied to the set signal input terminal S of the RS-flip-flop circuit FF, the Q-terminal output of the RS-flip-flop circuit FF becomes a high level voltage, the switching element TR 1 is closed, and the charging / discharging capacitor C 2 is discharged. At the same time, {Fig. 2 (b)}, the current E i / R 1 flows again in the integrating capacitor C 1 circuit, and the output voltage of the operational amplifier Q 1 starts to fall again as shown in Fig. 2 (a). After that, the above operation is repeated, and the output of the Q terminal in the RS-flip-flop circuit FF changes as shown in FIG.

RS−フリップフロップ回路FFのQ出力端子電圧が低レベ
ル状態を保持する時間をt1、高レベル状態を保持する時
間をt2とすると、 となり、又、 が成立ち、 となる。
When the time period during which the Q output terminal voltage of the RS-flip-flop circuit FF maintains the low level state is t 1 and the time period during which the Q output terminal voltage maintains the high level state is t 2 , And again Was established, Becomes

よって、RS−フリップフロップ回路FFのQ端子出力電圧
のレベル変化、したがってまた端子出力電圧のレベル
変化の周期Tは、 Q端子及び端子の各出力電圧のレベル変化の周波数F
は、 となる。
Therefore, the cycle of the level change of the Q terminal output voltage of the RS-flip-flop circuit FF, and therefore the level change of the terminal output voltage, is Frequency F of Q terminal and level change of each output voltage of terminal
Is Becomes

(6)式から明らかなように、Q端子及び端子の各出
力電圧のレベル変化の周波数Fは入力信号電圧Eiの大き
さに比例しているから、演算増幅器Q1乃至RS−フリップ
フロップ回路FFより成る回路は電圧・周波数変換回路を
構成することとなる。
As is clear from the equation (6), the frequency F of the level change of the Q terminal and the output voltage of each terminal is proportional to the magnitude of the input signal voltage E i. Therefore, the operational amplifier Q 1 to RS-flip-flop circuit The circuit made up of FFs constitutes a voltage / frequency conversion circuit.

然しながら、周囲温度の変動等によって充放電用コンデ
ンサC2の容量及び比較器Q3の基準電圧−V2の大きさ等が
変化すると周波数Fも亦変化すること(6)式から明ら
かであるが、RS−フリップフロップ回路FFにおけるQ端
子出力が低レベル電圧のときのデューテイ比Dを求める
と、 となる。
However, it is clear from the equation (6) that the frequency F also changes when the capacity of the charging / discharging capacitor C 2 and the magnitude of the reference voltage −V 2 of the comparator Q 3 change due to fluctuations in the ambient temperature. , When calculating the duty ratio D when the Q terminal output in the RS-flip-flop circuit FF is a low level voltage, Becomes

(7)式から明らかなように、デューテイ比Dは入力信
号電圧Eiの大きさに比例し、又、積分コンデンサC1及び
充放電用コンデンサC2の各容量変化或いは比較器Q3及び
Q2の基準電圧−V1及び−V2の大きさの変化等に因って時
間t1及びt2が変動した場合においてもデューテイ比Dは
一定に保たれるから、デューテイ比Dは常に入力信号電
圧Eiの大きさに比例することとなる。
As is clear from the equation (7), the duty ratio D is proportional to the magnitude of the input signal voltage E i , and the capacitance change of the integrating capacitor C 1 and the charging / discharging capacitor C 2 or the comparator Q 3 and
The duty ratio D is kept constant even when the times t 1 and t 2 change due to changes in the magnitudes of the reference voltages −V 1 and −V 2 of Q 2 , so the duty ratio D is always It is proportional to the magnitude of the input signal voltage E i .

RS−フリップフロップ回路FFの端子出力電圧は、直流
阻止用コンデンサC3及び絶縁トランスTF1を介して比較
器Q4の反転入力端子に加えられ、比較器Q4の反転入力端
子の電圧{第2図(ニ)}が基準電圧V3によって定まる
比較器Q4のスレッシュホールドレベル以下に下ると、比
較器Q4の出力電圧が高レベル電圧となり、緩衝増幅器Q5
の出力電圧は第2図(ホ)に示すように高レベル電圧+
VDDとなる。逆に比較器Q4の反転入力端子の入力電圧が
スレッシュホールドレベルより高い場合には、緩衝増幅
器Q5の出力電圧は低レベル電圧+V0となる。
The terminal output voltage of the RS-flip-flop circuit FF is applied to the inverting input terminal of the comparator Q 4 via the DC blocking capacitor C 3 and the isolation transformer TF 1, and the voltage of the inverting input terminal of the comparator Q 4 { 2 (d)} falls below the threshold level of the comparator Q 4 determined by the reference voltage V 3 , the output voltage of the comparator Q 4 becomes a high level voltage and the buffer amplifier Q 5
Output voltage is high level voltage +
It becomes V DD . Conversely, when the input voltage at the inverting input terminal of the comparator Q 4 is higher than the threshold level, the output voltage of the buffer amplifier Q 5 becomes the low level voltage + V 0 .

尚、第1図には、互いにほぼ等しい抵抗値を有する分圧
抵抗R8及びR9を設け、その分電圧V3を基準電圧として比
較器Q4に加えるように形成した場合を例示したが、分圧
抵抗R8及びR9を省き、ツェナダイオードZ1及びZ2の接続
点における中間レベル電圧V3を比較器Q4の非反転入力端
子に加えるように形成してもよい。
Incidentally, FIG. 1 exemplifies a case where the voltage dividing resistors R 8 and R 9 having resistance values substantially equal to each other are provided, and the voltage V 3 is applied as a reference voltage to the comparator Q 4 by way of example. Alternatively, the voltage dividing resistors R 8 and R 9 may be omitted, and the intermediate level voltage V 3 at the connection point of the Zener diodes Z 1 and Z 2 may be applied to the non-inverting input terminal of the comparator Q 4 .

又、比較器Q4として、出力電圧が低レベル電圧の場合+
V0、高レベル電圧の場合+VDDとなり得るような比較器
を用いる場合には、緩衝増幅器Q5を省いても差支えな
い。
Also, if the output voltage is a low level voltage as the comparator Q 4 , +
When using a comparator that can be + V DD in the case of V 0 and a high level voltage, the buffer amplifier Q 5 can be omitted.

緩衝増幅器Q5の出力電圧は、入力抵抗R10を介して片電
源で作動せしめられる演算増幅器Q6の反転入力端子に加
えられ、その出力電圧がレベルシフト用トランジスタTR
2を介してトランジスタTR3のベース電極に加えられてコ
レクタ電流を変化せしめ、平滑用抵抗R11における電圧
降下と、電流制限抵抗R12における電圧降下とが等しく
なるように制御作動が行われる。
The output voltage of the buffer amplifier Q 5 is applied to the inverting input terminal of the operational amplifier Q 6 which is operated by a single power source via the input resistor R 10 , and the output voltage is applied to the level shift transistor TR.
The collector current is applied to the transistor TR 3 via 2 to change the collector current, and the control operation is performed so that the voltage drop in the smoothing resistor R 11 and the voltage drop in the current limiting resistor R 12 become equal.

即ち、緩衝増幅器Q5の出力電圧は、演算増幅器Q6、レベ
ルシフト用トランジスタTR2及びトランジスタTR3より成
る電圧・電流変換回路において電流に変換されることと
なるが、この変換出力電流i0の大きさは、 となり、RS−フリップフロップ回路FFにおけるQ端子出
力電圧のデューテイ比Dに比例する。
That is, the output voltage of the buffer amplifier Q 5 includes an operational amplifier Q 6, although the be converted to a current in the voltage-current converting circuit comprising the level shift transistor TR 2 and the transistor TR 3, the converted output current i 0 The size of And is proportional to the duty ratio D of the Q terminal output voltage in the RS-flip-flop circuit FF.

(8)式に(7)式を代入すると、 となり、変換出力電流i0の大きさは入力信号電圧Eiの大
きさに比例し、その比例係数は、ツェナダイオードZ1
びZ2の電圧+VDD及び直流源PSの出力電圧−VEEの大きさ
と、抵抗R1、R2、R10、R11及びR12の各抵抗値よりなる
から周囲温度の変動に因る比例係数の変化は極めて小で
ある。
Substituting equation (7) into equation (8), Therefore, the magnitude of the conversion output current i 0 is proportional to the magnitude of the input signal voltage E i , and the proportional coefficient is the voltage of the Zener diodes Z 1 and Z 2 + V DD and the output voltage of the DC source PS −V EE . Since the size and the resistance values of the resistors R 1 , R 2 , R 10 , R 11 and R 12 are included, the change of the proportional coefficient due to the fluctuation of the ambient temperature is extremely small.

変換出力電流i0は信号出力端子T3及びT4、伝送線路L1
びL2、入出力端子T5及びT6、直流電源Eを介して受信器
RXに伝送され、指示又は記録が行われる。
The converted output current i 0 is received by the receiver through the signal output terminals T 3 and T 4 , the transmission lines L 1 and L 2 , the input / output terminals T 5 and T 6 , and the DC power source E.
It is transmitted to R X for instruction or recording.

以上はRS−フリップフロップ回路のFFの端子出力電圧
を直流阻止用コンデンサC3及び絶縁トランスTF1を介し
て比較器Q4に加えた場合を例示したが、Q端子、入力抵
抗R2及びベース抵抗R7の接続点と直流阻止用コンデンサ
C3との間に、例えば緩衝増幅器を介在せしめ、Q端子出
力電圧を緩衝増幅器、直流阻止用コンデンサC3及び絶縁
トランスTF1を介して比較器Q4に加えるようにしても本
発明を実施することが出来る。
The above has illustrated the case where the terminal output voltage of the FF of the RS-flip-flop circuit is applied to the comparator Q 4 via the DC blocking capacitor C 3 and the insulating transformer TF 1. However, the Q terminal, the input resistance R 2 and the base Connection point of resistor R 7 and DC blocking capacitor
Between the C 3, for example, a buffer amplifier allowed intervention, Q terminal output voltage buffer amplifier, also be applied to the comparator Q 4 via a capacitor C 3 and the insulating transformer TF 1 DC blocking the invention embodiment You can do it.

発明の効果 本発明においては、入力信号電圧を電圧・周波数変換回
路において矩形波に変換し、この矩形波を直流阻止用コ
ンデンサ及び絶縁トランスを介して周波数・電圧変換回
路に導入し、更に、この周波数・電圧変換回路の変換出
力を電圧・電流変換回路に導入し、その変換出力電流の
大きさを前記電圧・周波数変換回路における変換出力矩
形波電圧のデューデイ比に比例せしめるように構成して
あるので、良好な温度特性及び直線性を以て入力信号電
圧を電流に変換し得ると共に、回路構成も比較的簡潔
で、例えばpH又は溶存酸素濃度等の測定信号の遠隔地点
への伝送等に用いて効果極めて大である
According to the present invention, the input signal voltage is converted into a rectangular wave in the voltage / frequency conversion circuit, and this rectangular wave is introduced into the frequency / voltage conversion circuit via the DC blocking capacitor and the insulating transformer. The conversion output of the frequency / voltage conversion circuit is introduced into the voltage / current conversion circuit, and the magnitude of the conversion output current is made proportional to the duty ratio of the converted output rectangular wave voltage in the voltage / frequency conversion circuit. Therefore, it is possible to convert the input signal voltage into a current with good temperature characteristics and linearity, and the circuit configuration is relatively simple, and it is effective when used for transmitting a measurement signal such as pH or dissolved oxygen concentration to a remote point. Extremely large

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示す図、第2図はその作動
説明のための波形図、第3図は従来の二線式絶縁伝送回
路を示す図で、T1及びT2:信号入力端子、R1、R2及び
R10:入力抵抗、Q1及びQ6:演算増幅器、C1:積分コンデン
サ、R3:充電抵抗、C2:充放電用コンデンサ、Q2、Q3及び
Q4:比較器、R4乃至R6、R8及びR9:分圧抵抗、FF:フリッ
プフロップ回路、TR1:開閉素子、R7:ベース抵抗、C3:直
流阻止用コンデンサ、TF1及びTF2:絶縁トランス、Q5
衝増幅器、TR2及びTR3:タランジスタ、Z1及びZ2:ツェナ
ダイオード、C4:平滑用コンデンサ、R11:平滑用抵抗、R
12:電流制限抵抗、CC:定電流回路、OSC:発振回路、C5:
結合コンデンサ、PS:直流源、T3及びT4:信号出力端子、
L1及びL2:伝送線路、T5及びT6:入出力端子、RX:受信
器、E:直流電源、V/F:電圧・周波数変換回路、F/V:周波
数・電圧変換回路、V/I:電圧・電流変換回路である。
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation thereof, and FIG. 3 is a diagram showing a conventional two-wire insulated transmission circuit. T 1 and T 2 : Signal input terminals, R 1 , R 2 and
R 10 : Input resistance, Q 1 and Q 6 : Operational amplifier, C 1 : Integrating capacitor, R 3 : Charging resistor, C 2 : Charging / discharging capacitor, Q 2 , Q 3 and
Q 4: comparator, R 4 to R 6, R 8 and R 9: dividing resistors, FF: flip-flop circuit, TR 1: switching element, R 7: base resistance, C 3: DC blocking capacitor, TF 1 and TF 2: insulation transformer, Q 5 buffer amplifier, TR 2 and TR 3: Taranjisuta, Z 1 and Z 2: the Zener diode, C 4: smoothing capacitor, R 11: smoothing resistance, R
12 : Current limiting resistor, CC: Constant current circuit, OSC: Oscillation circuit, C 5 :
Coupling capacitor, PS: DC source, T 3 and T 4: signal output terminal,
L 1 and L 2 : Transmission line, T 5 and T 6 : Input / output terminals, R X : Receiver, E: DC power supply, V / F: Voltage / frequency conversion circuit, F / V: Frequency / voltage conversion circuit, V / I: A voltage / current conversion circuit.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】入力信号電圧に対応する電流を積分回路に
流入せしめる回路と、この積分回路の出力電圧が加えら
れる第1の比較器と、この第1の比較器の出力電圧がリ
セット信号入力端子に加えられるCMOS形リセット・セッ
ト・フリップフロップ回路と、このCMOS形リセット・セ
ット・セット・フリップフロップ回路にリセット信号が
加えられた際に低レベル出力電圧を送出する端子の出力
電圧が低レベルの際に前記入力信号電圧に対応する電流
及びこれと逆向きの電流の合成電流を前記積分回路に流
入せしめる回路と、前記CMOS形リセット・セット・フリ
ップフロップ回路にリセット信号が加えられた際に低レ
ベル出力電圧を送出する端子の出力電圧により開閉を制
御され、充放電用コンデンサの放電回路を開閉する開閉
素子と、前記充放電用コンデンサの充電回路と、前記充
放電用コンデンサの充電電圧が設定値に達した際に前記
CMOS形リセット・セット・フリップフロップ回路にセッ
ト信号を加える第2の比較器と、前記CMOS形リセット・
セット・フリップフロップ回路の出力電圧が第1の絶縁
トランスを介して加えられる第3の比較器と、この第3
の比較器の出力に対応する電圧が加えられる電圧・電流
変換回路と、この電圧・電流変換回路の出力電流が供給
される伝送線路と、この伝送線路を介して加えられる直
流電圧により作動電流を供給され、前記第1の絶縁トラ
ンスの二次側回路素子に作動電圧を供給するツェナダイ
オードと、このツェナダイオードのツェナ電圧により作
動せしめられる発振回路と、第2の絶縁トランスを介し
て加えられる前記発振回路の発振出力から正負の直流電
圧を発生する直流源とより成る二線式絶縁伝送回路。
1. A circuit for causing a current corresponding to an input signal voltage to flow into an integrating circuit, a first comparator to which an output voltage of the integrating circuit is applied, and an output voltage of the first comparator is a reset signal input. The CMOS type reset set flip-flop circuit that is applied to the pin and the output voltage of the pin that outputs the low level output voltage when the reset signal is applied to this CMOS type reset set set flip-flop circuit is low level. At the time of applying a reset signal to the CMOS type reset set flip-flop circuit, and a circuit for causing a combined current of a current corresponding to the input signal voltage and a current opposite thereto to flow into the integrating circuit. An opening / closing element for opening / closing the discharge circuit of a charging / discharging capacitor, the switching of which is controlled by the output voltage of a terminal that outputs a low-level output voltage; A charging circuit of capacitor, said when the charging voltage of the charging and discharging capacitor reaches the set value
A second comparator for applying a set signal to the CMOS reset set flip-flop circuit;
A third comparator to which the output voltage of the set flip-flop circuit is applied via a first isolation transformer;
The voltage / current conversion circuit to which the voltage corresponding to the output of the comparator is applied, the transmission line to which the output current of this voltage / current conversion circuit is supplied, and the operating current by the DC voltage applied via this transmission line. A Zener diode that is supplied and supplies an operating voltage to the secondary side circuit element of the first isolation transformer, an oscillation circuit that is operated by the Zener voltage of the Zener diode, and a Zener diode that is applied via a second isolation transformer. A two-wire insulated transmission circuit consisting of a DC source that generates a positive and negative DC voltage from the oscillation output of the oscillator circuit.
JP13225086A 1986-06-07 1986-06-07 Two-wire insulated transmission circuit Expired - Lifetime JPH0740674B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13225086A JPH0740674B2 (en) 1986-06-07 1986-06-07 Two-wire insulated transmission circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13225086A JPH0740674B2 (en) 1986-06-07 1986-06-07 Two-wire insulated transmission circuit

Publications (2)

Publication Number Publication Date
JPS62289018A JPS62289018A (en) 1987-12-15
JPH0740674B2 true JPH0740674B2 (en) 1995-05-01

Family

ID=15076878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13225086A Expired - Lifetime JPH0740674B2 (en) 1986-06-07 1986-06-07 Two-wire insulated transmission circuit

Country Status (1)

Country Link
JP (1) JPH0740674B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103560778B (en) * 2013-10-16 2016-04-20 广州金升阳科技有限公司 A kind of two-wire system signal-isolated transmission circuit
CN104764469A (en) * 2015-04-16 2015-07-08 于广沅 Double-line-mode analog signal isolation converter
CN110474609B (en) * 2019-08-08 2023-06-09 浙江中控技术股份有限公司 Foundation field bus signal modulation circuit
CN110868167B (en) * 2019-12-02 2023-08-25 云南电网有限责任公司电力科学研究院 DC Voltage Isolation Amplifier

Also Published As

Publication number Publication date
JPS62289018A (en) 1987-12-15

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