JPH0740676B2 - Digital transmission signal reproduction device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission signal reproducing apparatus.

BACKGROUND ART AND PROBLEMS When transmitting digital signals such as PCM signals (including recording / reproducing), the receiving signal (reproducing signal) is transmitted on the receiving side (reproducing side) in order to correct intersymbol interference. It is input to the digital signal detector via the waveform equalizer. A transversal type filter is usually used as the waveform equalizer. This transversal filter samples a received digital signal whose waveform is distorted by passing through a transmission line, delays the sampled values sequentially with a plurality of delay elements, and multiplies each delayed output by a predetermined coefficient. It is configured to add and obtain an equalized output. The equalized output is supplied to the digital data detector and converted into a rectangular wave digital signal, but the S / N of the encoded output input to the detector must be at least 20 dB for accurate detection. Is.

On the other hand, since the transmission path (especially the magnetic recording / reproducing system) has bandpass characteristics and nonlinearity, the amplitude value of the received (reproduced) digital signal input to the equalizer according to the frequency of the transmitted signal is fluctuate. Therefore, the dynamic range of the received signal, which is defined as the ratio of the peak of the amplitude and the amplitude at the maximum repetition frequency of the transmitted signal, is usually about 20 to 30 dB.

Therefore, the dynamic range required for the equalizer is 40 to 50 dB as a whole, and the number of sampling levels (or the number of quantization bits) of the signal processed inside the equalizer is 7 to 8 bits. . An equalizer is an A / D converter for sampling and encoding a transmission signal, a plurality of parallel M-bit shift registers for delaying the output parallel M-bit signal, and multiplying the output of this shift register by a predetermined coefficient. When configured with a multiplier and an adder that adds the outputs of this multiplier,
If the number of quantization bits M is large, the circuit becomes large-scale and complicated. Also, if the equalizer is composed of a delay element array such as CCD or BBD and an analog coefficient adder that multiplies each delay output by a coefficient and adds, there is a limit to the transmission dynamic range of CCD or BBD. In addition, there is a problem that the S / N equalized output above a certain level cannot be obtained and the code error increases.

SUMMARY OF THE INVENTION In view of the above problems, the present invention compresses the dynamic range of a signal handled by an equalizer, simplifies the circuit configuration, and even an equalizer having a limited transmission dynamic range has a high The purpose is to enable quality signal processing.

SUMMARY OF THE INVENTION A digital transmission signal reproducing apparatus according to the present invention has a swing compression characteristic that has a swing compression characteristic according to a frequency-swing characteristic of a transmitted digital signal, and a swing compression means that suppresses a high swing band portion. An equalizer for equalizing the waveform of the amplitude-compressed digital signal to reduce intersymbol interference, and an amplitude correction means for correcting the amplitude of the equalizer output by the inverse characteristic of the amplitude compression means. However, the digital signal is reproduced based on the output of the amplitude correction means. With this configuration, the equalizer circuit can be simplified or high-quality waveform equalization processing can be performed.

Embodiments The present invention will be described below with reference to the drawings of the embodiments.

FIG. 1 shows a fixed head type multi-channel to which the present invention is applied.
In the block diagram of the main part of the PCM recorder / player, terminals (6) and (7)
The left-channel audio signal L and the right-channel audio signal R given to the are converted into digital signals by the A / D converters (8) and (9), respectively, and error correction codes are added by the PCM circuit (10) and data interleaving is performed. And the like, and then given to the multiplexer (12) via the modulator (11). In the multiplexer (12), the serial digital signal output from the modulator (11) is sequentially distributed to the N channels, and the recording heads (14-1) of the N channels are passed through the recording amplifiers (13-1) to (13-N). ~ (14-N) and tape (1)
Recorded in the upper N tracks. The signals are not simultaneously recorded in each track, but are recorded in time division (track sequence) by the multiplexer (12) scanning its output as shown by arrow S. Therefore, in the A-side recording area (4A) of the magnetic tape (1),
N tracks from the center of the tape to the side edge, one after the other
It is formed in a state numbered by ~ N.

When the cassette tape is turned upside down and recorded, tracks are formed in the B-side recording area (4B) in the same manner as the A-side recording area (4A) from the center of the tape to the side edges and sequentially numbered 1 to N. To be done.

During playback, as shown in Fig. 1, the playback head (14'-
The signals reproduced by 1) to (14'-N) pass through the reproduction amplifiers (15-1) to (15-N) and then the multiplexer (16).
Is supplied to. Recording heads (14-1) to (14-N)
And the reproduction heads (14'-1) to (14'-N) may be the same.

The multiplexer (16) converts the reproduction signal obtained from the N tracks into a serial signal and reproduces the equalizer circuit (1
Send to 7). The scanning of the multiplexer (16) is carried out in the direction shown by the arrow S ', whereby the data 1, 2, ... The output of the equalizer circuit (17) is given to a PCM processing circuit (19) through a digital signal detection and demodulation circuit (18), where error correction, data deinterleaving, and other processing are performed, and then the left side. It is separated into a channel signal and a right channel signal, and is derived as a reproduced audio signal via D / A converters (20) and (21).

FIG. 2A is a block diagram of the equalizer circuit (17) of FIG. 1 showing the basic configuration of the present invention, and FIGS. 2B to 2D are graphs showing the frequency characteristics of each part. FIG. 3 is a graph showing the frequency spectrum of the reproduced digital signal processed by the equalizer of FIG.

In the recording / reproducing system shown in FIG. 1, 2 Mbit / s is used with 20 tracks.
If transmission is performed at a rate of ec, the transmission rate per track is 100 Kbit / sec, and if the modulator (11) in FIG. 1 is performing 8-bit → 10-bit NRZ modulation, Maximum repetition frequency of transmitted signal (...
…… 10101 ………………) is 50 KHz. When the reproduction heads (14'-1) to (14'-N) are integrated and detected using magnetic flux response type heads using Hall elements or magnetoresistive effect elements, the frequency spectrum of the reproduction signal is the third. As shown by the solid line S1 in the figure, there is a peak in the low range (15 KHz), and there is a characteristic that gradually attenuates in the high range.

The level difference between the peak level of this spectrum and the reproduction level at the highest repetition frequency is about 29 dB as shown in FIG. The equalized output of the equalizer (17) in Fig. 2 must have S / N of about 20 dB at the maximum repetition frequency of 50 KHz in order to minimize the error in the detector / demodulator (18) in the next stage. I have to. Therefore the equalizer (17) must be capable of processing signals with a resolution or dynamic range of about 50 dB. When the equalizer is composed of a digital circuit, the quantization bit number M thereof is determined by the dynamic range D of the processed signal, and since D = 6M + 1.76 dB, M = 7-8 bits are required. Therefore, the equalizer has a large scale of hardware and is severely limited in terms of cost.

For this reason, in this embodiment, as shown in FIG. 2, the low-frequency suppressing circuit (23) suppresses the low-frequency peak of the reproduced signal, and then the equalizer (24) performs waveform equalization. The low-frequency suppression circuit (23) can be composed of, for example, a primary high-pass filter having the characteristics shown in FIG. 2 (B). When the low-pass cutoff frequency f ₀ of this high-pass filter is set to 48 KHz, the frequency spectrum of the output signal of the low-pass suppressing circuit (23) has its low-pass peak compressed to 19 dB as shown by the dotted line S2 in FIG. It As a result, the dynamic range (ratio between the noise level and the maximum peak level) of the signal handled by the equalizer (24) in the next stage is 39 dB, and the equalization process can be performed using a digital filter with a quantization bit number of 6 bits. It will be possible. The frequency characteristic of the equalizer (24) may be a bandpass characteristic similar to the conventional one as shown in FIG. 2C.

The output of the equalizer (24) is supplied to a digital data detection / demodulation circuit (18) through a low-frequency correction circuit (25). The low-frequency correction circuit (25) is a circuit that restores the low-frequency component suppressed by the low-frequency suppression circuit (23) to obtain a correct equalized waveform without intersymbol interference. For example, as shown in FIG. 2D. It can be configured by a low-pass filter having characteristics opposite to those of the low-frequency suppression circuit (23).

FIG. 4 is a block diagram showing a more specific embodiment of the basic constitution of the equalizer of the present invention shown in FIG. The low-frequency suppression circuit (23) shown in FIG. 2 is composed of an amplifier (27) having a high-pass filter characteristic as shown in FIG. The reproduction signal suppressed by the amplifier (27) in the low frequency range is 6 bits.
It is sampled and encoded by the A / D converter (28). As shown in Fig. 3, the band of the reproduced signal is 0 to about 100 KHz (transmission rate
Since the sampling frequency is 100K bits / sec), the sampling frequency is 20
It is 0 KHz.

The 6-bit parallel signal of the A / D converter (28) is given to the series circuit of the 6-bit parallel shift registers (29-1) to (29-n) and sequentially delayed by the bit cycle of the transmission signal. The delayed outputs and input signals of the shift register series circuit are multiplied by the coefficients a _{0 to} a _n by the multipliers (30-0) to (30-n) and then added by the adder (31). It These shift register, multiplier and adder constitute a transversal type digital filter (32), and the coefficients a _{0 to} a _{n of the} multiplier.
Is defined so that the digital filter (32) exhibits the waveform equalizing filter characteristic of FIG. 2C.

The output of the adder (31) is given to a digital integrator (33) that operates as the low-frequency correction circuit (25) in FIG. 2, and the detection / demodulation circuit ( 18)
Be derived to.

As described above, since the bit number of the code signal handled by the digital filter (32) is reduced from 8 bits to 6 bits, the shift registers (29-1) to (29-n) and the multiplier (30-
0) to (30-n) and the hardware amount of adder (38)
It will be reduced to 3/4, and it will be possible to make an LSI in one chip.

FIG. 5 is a block diagram showing another embodiment of the reproduction equalizer circuit, and the same parts as those in FIG. 4 are designated by the same reference numerals. In FIG. 5, the reproduced signal is given to the A / D converter (28) through the amplifier (27) having no filter characteristic and is quantized as in FIG. The output of the A / D converter (28) is given to the differentiator (34), and the difference between adjacent sample values is derived to the digital equalizer (32) similar to that shown in FIG. The differentiator (34) has a function of reducing the number of quantization bits of the output of the A / D converter (28) and giving it to the digital equalizer (32), whereby the digital equalizer (32) is provided. It is possible to reduce the number of bits per sampled value of the digital signal handled by. Since the differentiator (34) has a differentiating function, it can be considered that the differencer (34) acts as a high-pass filter that suppresses low-frequency components. It corresponds to the region suppression circuit (23).

The output of the difference unit (34) is equalized by the digital equalizer (32), and the equalized output is low-frequency corrected by the digital integrator (33) and then led to the detection / demodulation circuit (18).

FIG. 6 is a block diagram of an equalizer circuit showing still another embodiment. In this embodiment, a transversal type equalization filter is configured by using a delay element array such as CCD or BBD for analog sampling and transmission of an input signal. Sixth
In the figure, the reproduction signal is low-pass suppressed by a high-pass filter amplifier (27) similar to that in Fig. 4, and then the CCD or BBD
And the like, and sampling and transfer (delay) are performed in the bit cycle of the reproduction signal. The input and each delayed output of the charge transfer device array (36) are connected to the coefficient multiplier (37
The coefficients a _{0 to} a _n are multiplied by −0) to (37-n), then added by the adder (38), and taken out as an equalized output. The equalized output is low-frequency corrected by the analog integrator (39) and then led to the detection / demodulation circuit (18).

In the embodiment shown in FIG. 6, since the low-frequency peak of the reproduced signal whose waveform is equalized is suppressed by the high-pass filter amplifier (27) and then supplied to the charge transfer element array (36), the charge transfer element array is Even if there is a limit to the dynamic range of the signal that can be handled, it is possible to perform waveform equalization processing on a reproduced signal that apparently exceeds this limit, thus obtaining a reproduced digital signal with higher accuracy and fewer errors. be able to.

The present invention has been described above based on the preferred embodiments, but the present invention is not limited to the embodiments and can be implemented in various modes.

For example, since the frequency spectrum of the transmission signal shown in FIG. 3 changes depending on the modulation method and transmission rate in the modulator (11) of FIG. 1, transmission is performed in accordance with the frequency spectrum pattern according to the modulation method and transmission rate. It is preferable to compress the dynamic range of the signal. Further, when the reproduction heads (14'-1) to (14'-N) of FIG. 1 are speed-responsive and differential detection is performed, a high-frequency upstream frequency spectrum is shown. The same effect as that of the embodiment can be obtained by performing the waveform equalization processing after compressing.

Further, in the equalizer of the embodiment shown in FIG. 4, the A / D converter (28) is given a non-linear characteristic so that the quantization step is roughened on the high level side of the input reproduction signal. With 23), it is possible to obtain the same effect as that of compressing the amplitude.

As described above, according to the present invention, the waveform equalizer is performed after suppressing the high amplitude band portion according to the frequency-amplitude characteristic of the transmitted digital signal. The dynamic range of the signal to be handled becomes small, and therefore the hardware of the equalizer can be simplified. Moreover, even if there is a limit to the dynamic range of the signal that can be handled by the waveform equalizer, it is possible to perform signal processing that apparently expands this limit, and to perform more accurate waveform equalization and code. It is possible to reproduce a digital signal with few errors.

[Brief description of drawings]

FIG. 1 shows a fixed head type multi-channel to which the present invention is applied.
FIG. 2A is a block diagram showing the basic structure of a receiving end equalizer circuit for PCM transmission according to the present invention, and FIGS. 2B to 2D show the frequency characteristics of each part of FIG. 2A. FIG. 3 is a graph showing the frequency spectrum of the reproduced digital signal processed by the equalizer circuit of FIG. 2, and FIG. 4 is an equalizer circuit showing a more specific embodiment based on the basic configuration of FIG. Block diagrams, FIG. 5 and FIG. 6 are block diagrams of an equalizer circuit showing different embodiments, respectively. The symbols used in the drawings are (23) ... low-frequency suppression circuit (24) ... equalizer (25) ... low-frequency correction circuit.

Claims (1)

[Claims] 1. A amplitude compression means for suppressing a high amplitude band portion, which has an amplitude compression characteristic corresponding to a frequency-amplitude characteristic of a transmitted digital signal, and a waveform of the amplitude compressed digital signal. And an amplitude compensator for compensating the amplitude of the output of the equalizer with the inverse characteristic of the amplitude compression means, and the output of the amplitude correction means. A digital transmission signal reproducing device configured to reproduce a digital signal based on the above.