JPH0743798B2 - Automatic operation confirmation tester - Google Patents

Description

The present invention relates to an operation test of a fault detection circuit and an alarm generation circuit provided in a system having a function of detecting a fault condition and generating an alarm.

[Conventional technology]

Conventionally, when performing an operation confirmation test of a fault detection circuit and an alarm generation circuit provided in a system having a function of detecting a fault state and generating an alarm, only an actual fault that can be manually performed is generated. We are conducting an operation confirmation test. In addition, even when checking the alarm output of the alarm generation circuit, a simple jig is used to display the alarm output status of the alarm generation circuit, and the present situation is mainly based on visual inspection by humans.

[Problems to be Solved by the Invention] By the way, as described above, in the operation check test of the conventional fault detection circuit and alarm generation circuit, the fault detection circuit and the alarm generation circuit are caused by a fault that cannot be performed manually. The operation confirmation test of cannot be performed. In recent years,
The number of fault detection circuits and alarm generation circuits that require an operation confirmation test is increasing due to the complexity of the functions inside the equipment due to technological progress (that is, the fault detection circuits etc. are provided depending on the type of fault). In other words, the system has 1st to Nth (N is an integer of 2 or more).
The first to Nth fault detection circuits for detecting the first to Nth fault states according to the fault states of No. 1) to N) are provided), and all of these fault detection circuits and alarm generation circuits are manually operated. However, there is a problem that the number of man-hours required for the operation confirmation test is enormous.

[Means for Solving the Problems] According to the present invention, a first to N-th (N is an integer of 2 or more) failure state is detected, and first to N-th failure detection signals are transmitted, respectively. First to Nth failure detection circuits, and the first
To a pseudo fault generating circuit for transmitting a pseudo fault generating signal used in a system having an alarm generating circuit for transmitting an alarm signal in response to each of the Nth fault right issuing signals, and the pseudo fault in the pseudo fault mode. Supplying means for sequentially supplying the failure occurrence signals to the first to Nth failure detection circuits, and setting the pseudo failure mode in the operation confirmation test to generate the pseudo failure occurrence signals from the pseudo failure generation circuit. An automatic operation confirmation circuit for receiving the alarm signal and confirming the alarm signal, wherein the pseudo fault generation circuit and the supply means are provided in the system. Is obtained.

[Examples] Hereinafter, the present invention will be described with reference to Examples.

Referring to the drawings, the system 1 includes a fault detection circuit 11, an alarm generation circuit 12, an OR gate 2 and a pseudo fault generation control circuit 4. The output of OR gate 2 is the fault detection circuit 11
One of the inputs of the OR gate 2 is connected to the + 5V terminal. The other of the inputs of the OR gate 2 is a pseudo-fault occurrence control circuit 4 including a D-type flip-flop 41.
(In the drawing, only one fault detection circuit 11 and one OR gate 2 are shown and the other fault detection circuits and OR gates are omitted. However, these fault detection circuits and OR gates are usually of a fault type. In other words, the fault detection circuit and the OR gate, which are omitted in the figure, are indicated by a dotted line (broken line).
In general, different faults occur in the system, but a plurality of fault detection circuits (for example, the first fault to the Nth fault (N is an integer of 2 or more)) (for example, 1 to Nth failure detection circuits), and OR gates are provided corresponding to these failure detection circuits. Then, one input of each OR gate is similarly connected to the + 5V terminal. Further, in the figure, only two D type flip-flops 41 are shown in the pseudo fault occurrence control circuit 4, but the pseudo fault occurrence control circuit 4 is provided with a plurality of D type flip flops 41. That is, if there are N OR gates, N D-type flip-flops are required, and these N D-type flip-flops are connected in cascade.

Then, the Q terminal of the first D type flip-flop is connected to the first OR gate, and the Q terminal of the Nth D type flip-flop is connected to the Nth OR gate.

When confirming the operations of the fault detection circuit 11 and the alarm generation circuit 12, one of the inputs of the OR gate 2 and the pseudo fault generation control circuit 4 are connected to the automatic operation confirmation circuit 3 including a microprocessor as shown in the figure. The output of the alarm generation circuit 12 is input to the automatic operation confirmation circuit 3.

Next, operation confirmation of the fault detection circuit 11 and the alarm generation circuit 12 will be described.

Under the control of the microprocessor 31, the pseudo failure serial data A and the pseudo failure write clock B are sent from the automatic operation confirmation circuit 3 to the pseudo failure occurrence control circuit 4.

As a result, the pseudo fault serial data A is sequentially output from the Q terminals of the first to Nth D type flip-flops with a predetermined time difference (a predetermined timing difference). Then, these pseudo fault serial data A
Are given to the first to N-th OR gates as pseudo fault occurrence signals C, respectively. By the way, as shown in the figure, a high level (+ 5V) is applied to the input of the OR gate 2, and the OR gate 2 always outputs the high level regardless of the input of the pseudo fault occurrence signal C to the OR gate 2. That is, the pseudo fault occurrence signal C is not output to the fault detection circuit 11. In the automatic operation confirmation circuit 3, when the pseudo fault serial data A is transmitted, the microprocessor 31
The + 5V terminal is grounded under the control of (for example, the + 5V terminal is grounded via a switching transistor (not shown) provided in the automatic operation confirmation circuit 3, and the microprocessor 31 must turn on this switching transistor. Ground the + 5V terminal). As described above, when the + 5V terminal is grounded, one of the inputs of the first to Nth OR gates changes from the high level to the low level. ). As a result, the first to Nth
From the OR gate, the pseudo failure occurrence signals (first to Nth pseudo failure occurrence signals) are sequentially transmitted (that is, with a predetermined timing shift). Then, these first to Nth pseudo fault occurrence signals are given to the first to Nth fault detection circuits with a predetermined timing shift.

In the first fault detection circuit, the first pseudo fault generation signal causes a fault state, and the fault signal E (first fault signal) is sent to the alarm generation circuit 12. When receiving the first fault signal, the alarm generation circuit 12 sends out an alarm output F (first alarm signal) corresponding to the first fault signal.

Similarly, the second to Nth fault detection circuits enter the fault state by the second to Nth pseudo fault generation signals, respectively, and send the second to Nth fault signals to the alarm generation circuit 12. When receiving the second to Nth fault signals,
The alarm generation circuit 12 sends out second to Nth alarm signals in response to the second to Nth fault signals, respectively. The first to Nth fault signals are given to the alarm generation circuit 12 with a predetermined timing shift, and as a result, the first to Nth alarms are shifted from the alarm generation circuit 12 with a predetermined timing. A signal will be sent.

These first to Nth alarm signals are sent to the automatic operation confirmation circuit 3, and it is confirmed by the microprocessor 31 that an alarm corresponding to a preset pseudo fault has occurred.

In this way, by sending the pseudo fault occurrence signals to all the fault detection circuits, the operation of all the fault detection circuits can be confirmed in a short time.

〔The invention's effect〕

As described above, according to the present invention, it is possible to automatically perform the operation confirmation test of all the fault generating circuits and the alarm generating circuits. As a result, the reliability of the fault generating circuits and the alarm generating circuits are improved and the test work time is increased. The effect is to be able to significantly reduce.

[Brief description of drawings]

The drawings are block diagrams showing an embodiment of the present invention with some parts omitted. 1 …… System, 2 …… OR gate, 3 …… Automatic operation check circuit, 4 …… Pseudo fault occurrence control circuit, 11 …… Fault detection circuit, 12
…… Alarm generation circuit, 31 …… Microprocessor, 41…
... D type flip-flop.

Front page continuation (72) Inventor Kinya Endo 2 Raijin, Yoshioka, Yamato-cho, Kurokawa-gun, Miyagi Miyagi NEC Corporation (56) References JP-A-60-54096 (JP, A)

Claims (1)

[Claims] 1. A first to Nth fault detection circuit for detecting a first to Nth (N is an integer of 2 or more) fault condition and transmitting a first to Nth fault detection signal, respectively, A pseudo fault generating circuit for transmitting a pseudo fault generating signal used in a system having an alarm generating circuit for transmitting an alarm signal in response to each of the first to Nth fault detecting signals, Supplying means for sequentially supplying the pseudo fault occurrence signals to the first to Nth fault detection circuits, and the pseudo fault generation circuit is set in the pseudo fault mode during an operation confirmation test to generate the pseudo fault generation signals. And an automatic operation confirming circuit for receiving the alarm signal and confirming the alarm signal, wherein the pseudo fault generating circuit and the supplying means are provided in the system. Automatic operation check test equipment that.