JPH0743898B2 - Data recording / playback method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data recording method, and more particularly to the performance of a recording medium (position of error on the recording medium, error distribution, etc.) and the performance of a recording / reproducing apparatus (data recording method). It is suitable for use in a recording medium inspection device for evaluating and examining the quality of recording data such as an optical system, a servo system, an electric circuit section, and a modulation method.

[Prior Art] The applicant previously proposed a data recording method in Japanese Patent Application No. 61-151027 and a recording medium inspection apparatus in Japanese Patent Application No. 61-151028. This recording medium inspection device records and reproduces predetermined data on a recording medium and inspects the recording medium by detecting an error generated in the process, in a recording and reproducing device, the unit data of the data is used to determine the presence or absence of a recording and reproduction error. Error pattern generating means for detecting and generating an error pattern signal that takes the first and second states depending on whether the recording / reproducing error is detected, and count pulse generating means for generating a count pulse of the same cycle as the unit data. Position detecting means for outputting a reference position detecting signal representing a reference position of the recording medium, clear pulse generating means for outputting a clear pulse when the error pattern signal is inverted and when the reference position detecting signal is input, and the count First counter means for counting with a pulse and clearing the count value with the clear pulse; Second count means for counting with a clear pulse, and writing based on a write control signal, to the address designated by the count value of the second counter means, the error pattern signal and the counter value of the first counter means being written. It comprises a memory means for storing data and a write control signal generating means for outputting a write control signal to the memory means. The first counter means counts the count pulse so that the count value is EF run or error run. The second counter means counts the clear pulse, and the count value indicates the address of the memory means. The memory means records the write data composed of the error pattern signal and the count value of the first counter means at the address designated by the second counter means. The error pattern signal of this write data indicates the write data type of EF run or error run, and the count value of the first counter means indicates its length.

[Problems to be Solved by the Invention] When a recording medium is actually measured using this apparatus, a large number of minimum error run length data are written in the memory circuit of the recording medium inspection apparatus, and the storage thereof is performed. There is a drawback that the capacity is not used efficiently.

The present invention has been made in view of the above points, and provides a data recording method that efficiently uses the storage capacity of the memory means.

[Means for Solving Problems] EF run length data indicating a length in which no error has occurred on the recording medium and error run length data indicating a length in which an error has occurred are recorded in a memory circuit and reproduced. This is a data recording / reproducing method for recording data, and when the error run length data following the EF run length data is the minimum value during data recording, the recording of the minimum error run length data to the memory circuit is prohibited and the data is reproduced. In the data recording / reproducing method, it is determined that the data read from the memory circuit has continuously become EF run length data, and the minimum value of error run length data for which recording is prohibited is restored. .

[Operation] When the data is recorded, when the error run length data following the EF run length data has the minimum value, the recording of the minimum error run length data to the memory circuit is prohibited, and the data is read from the memory circuit at the time of data reproduction. It is judged that the recorded data has become the EF run length data continuously, and the minimum error run length data that prohibits recording is restored.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a recording medium inspection apparatus using a data recording method according to the present invention, FIGS. 2 and 3 are flow charts for explaining the recording medium inspection apparatus shown in FIG. 1, and FIG. (A)-(l) shows the timing chart which shows one operation example, respectively. Also, FIG. 5 (a),
FIGS. 6B and 6A and 6B are views showing display examples of the recording medium inspection device shown in FIG. In addition, []
The value given inside is a data value.

A recording system controller ₁ outputs a data clock RDCK to the data generator 2 and controls the start and stop of the data series Mseq by the control line C ₁ . A data generator 2 outputs a data sequence Mseq to be recorded on the disc in synchronization with the data clock RDCK. The pattern of the data series Mseq consisting of 8-bit symbol units is shown below, but the data value of each symbol uses a value in hexadecimal notation.

The data sequence Mseq is a start pattern indicated by data [FF] 5 times consecutively after data [00] 3 times or more consecutively, and a 20th order M sequence (the cycle is 2 ²⁰ (-1 bit), and an end pattern indicated by 5 consecutive data [00]. The length of the test pattern is determined according to the recording time, and when the recording time is long, the same sequence is repeated.

Reference numeral 3 denotes an EFM modulator, which is output from the data clock RDCK from the recording system controller 1 and the data generator 8
Enter each bit symbol data series Mseq and EF
After M-modulation, 14 in synchronization with the data clock RDCK
Outputs the bit symbol data series M.Mseq.

Reference numeral 4 denotes an optical recording / reproducing apparatus, in which the data sequence M.Mseq output from the EFM modulator 3 is applied to a disc to be inspected (not shown) at a constant linear velocity (CLV control) according to the following format consisting of 588 channel bits per frame. ) To record.

Each data D _{1 to} D _{32 in the} above format is a data series M.Mse
It is an addition of extra bits (3 bits) to each piece of data (14 bits) of q. This recording format conforms to the compact disc (CD) format, and is mainly required for accurate CLV control during reproduction of the optical recording / reproducing apparatus 4.

Further, the optical recording / reproducing apparatus 4 outputs a reference position detection signal RSYNC of one pulse for each rotation of the disk to the reproducing system controller 8 described later by the position detecting means (not shown) during reproduction. This reference position detecting means can be realized by, for example, optically detecting a label attached to the label portion of the disc to be inspected. When the disk drive system is the direct drive system, a signal can be obtained from the motor, but the former is preferable for detecting the error position of the disk.

An EFM demodulator 5 outputs the data clock PDCK and EFM demodulates the reproduction data M.PBD (14 bits) output from the optical recording / reproducing device 4 into the reproduction data PBD (8 bits).

Reference numeral 6 denotes a data generator that outputs a data series Mseq in synchronization with the data clock PDCK output from the EFM demodulator 5. The data series Mseq starts from the data series Mseq output from the data generator 2. Only the pattern is removed, and the test pattern and end pattern are the same.

Reference numeral 7 denotes the reproduction data PBD output in parallel from the EFM demodulator 5 in synchronization with the data clock PDCK, and the data sequence Mseq output in parallel from the data generator 6,
It is a data comparator for comparing every symbol unit (8 bits), and outputs an error pattern COMP which becomes an "H" signal when the reproduction data PBD and the data series Mseq are the same and an "L" signal when they are different.

Reference numeral 8 represents a reproducing system controller, and 9 represents a 16-bit run length counter.

The reproduction system controller 8 inputs the data clock PDCK and the reproduction data PBD output from the EFM demodulator 5, respectively, and detects the above-mentioned start pattern and end pattern by reading the reproduction data PBD. Then, the start / stop control of the data series Mseq output from the data generator 6 is performed by the control line C ₂ .

The reproduction system controller 8 and the run length counter 9 are connected by a control line C ₃ , and the reproduction system controller 8 outputs an initial reset signal and the run length counter 9 outputs an overflow detection signal.

The reproduction system controller 8 outputs the count clock ECK and the clear signal CLR to the input terminal and the clear terminal of the run length counter 9, respectively, and also the inspection data clock KDCK.
Is output to the input port P ₁ of the microcomputer 10 described later.

The count clock ECK is a signal delayed by a predetermined time in the same cycle as the data clock PDCK, and is output during measurement of the error pattern. The inspection data clock KDCK is a pulse signal of 1 pulse when the polarity of the error pattern COMP is inverted or when the run length counter 9 detects an overflow.
When the reference position detection signal RSYNC is input, it is output as a pulse signal of two pulses at the timings described below. The clear signal CLR is similarly output as a signal obtained by delaying the inspection data clock KDCK for a predetermined time.

The run length counter 9 successively counts the count clock ECK, constantly outputs the count data to the input port P ₂ of the microcomputer 10, and repeats 0 start each time the clear signal CLR is input.

Next, in one cycle of the data clock PDCK, the count clock EC output from the reproduction system controller 8 is output.
The output sequence of K, the inspection data clock KDCK, and the clear signal CLR will be described.

1) When the polarities of the error pattern COMP are the same, only the count clock ECK is output.

2) When the polarity of COMP of the error pattern is inverted or the overflow of the run length counter 9 is detected, the inspection data clock KDCK, the clear signal CLR, and the count clock ECK are output in this order.

3) The reference position detection signal RSYNC is the previous data clock P.
When input in one cycle of DCK, check data clock K
DCK, clear signal CLR, inspection data clock KDCK, clear signal CLR, count clock ECK are output in this order.

Reference numeral 10 denotes a microcomputer (hereinafter abbreviated as the microcomputer 10) programmed according to the flowchart shown in FIG.

The microcomputer 10 and the reproduction system controller 8 are connected by a control line C _4, and when the reproduction system controller 8 detects the start pattern and end pattern of the reproduction data PBD,
The start signal SS and the end signal ES are output to the microcomputer 10, respectively.

At the input port P ₂ of the microcomputer 10, the error pattern COMP is added to the delay circuit 12 together with the count data of the run length counter 9.
And the bit polarity signal KS formed via the inverter INV13 is input as inspection data. This inspection data K ₁
As shown in Table 1, 16-bit data is converted into a bit string,
The first block has the most significant bit as the data of the bit polarity signal KS, and the second block has the lower 15 bits as the count data of the run length counter 9. The most significant bits “0” and “1” of this bit string correspond to “L” and “H” of the bit polarity signal KS, respectively. It represents the run length, and the case of 1 represents the burst error length in which erroneous symbols continue for the number indicated by the lower 15 bits. When all the lower 15 bits are 0, the reference position detection signal is shown regardless of the most significant bit.

Further, the microcomputer 10 outputs write data K ₂ , write control signal ▲ ▼ and address data ADD to the RAM 11 from the output ports Pa, Pb and Pc, respectively.

The RAM 11 writes the write data K ₂ to the address designated by the address data ADD when the write control signal ▲ ▼ becomes the “L” signal.

Reference numeral 14 is an external computer for data processing. The external computer 14 and the reproduction system controller 8 are mutually controlled by a control line C ₅ such as start and stop. Further, the address data ADD is input to the input port P ₃ of the external computer 14 from the output port Pc of the microcomputer 10, and the final address data Amax output at the end of measurement of the test data is read. Further, the RAM 11 inputs the read control signal ▲ ▼ and the address data ADD output from the output ports Pd and Pe of the external computer 14, and is designated by the address data ADD when the read control signal ▲ ▼ becomes the "L" signal. The data K ₂ written in the address is output to the input port P ₄ of the external computer 14.

Further, the external computer 14 fetches the write data K _{2 of the} RAM 11 according to the flowchart of FIG.

Reference numeral 15 is a printer, and 16 is a display, which displays the calculation processing result of the external computer 14.

With the above configuration, the present invention avoids recording the solid burst error length [1] (indicating that the number of erroneous symbols is one is 1) in the RAM 11 that is most likely to occur at the time of inspection of the recording medium, and stores it as much as possible. The capacity is used efficiently. For example, the microcomputer 10 sends the inspection data K ₁
EF run length [5] (indicating that the correct symbol was detected five times in a row), solid burst error length [1],
When inputting in the order of EF run length [10], solid burst error length [1] is omitted and EF run length [5] and EF run length [1]
[0] as write data K ₂ at consecutive addresses in RAM 11. On the other hand, the external computer 14 inserts the solid burst error length [1] between these EF run lengths when retrieving the write data K ₂ from the RAM 11 and restores the original inspection data K ₁ . However, if the procedure described above is simply performed, various problems occur when the reference position detection signal is detected, when the run length counter 9 overflows, and the like.

Next, the program of the microcomputer 10 will be described with reference to the flowchart of FIG.

In the flowchart of FIG. 2, FLAG1 indicates whether or not the solid burst error length [1] can be omitted, FLAG1 = 1 indicates that it can be omitted, and FLAG1 = 0 indicates that it cannot be omitted. FLAG2 indicates whether or not the solid burst error length [1] has been omitted. FLAG2 = 1 indicates that it is omitted, and FLAG2 = 0 indicates that it is not omitted.

First, the microcomputer 10 sends a start signal SS from the playback controller 8 (a signal that detects the start pattern of the playback data PBD).
Enter to execute the program.

Step S ₁ to S ₃ in the address data ADD, FLAG1, respectively initialized to 0 FLAG2. Next, in step S ₄ , the write control signal ▲ ▼ output from the output port Pb is set to the “H” signal to make the write disabled state, and in step S ₅ , the output port Pc
To the address data ADD [0] set in step S ₁
Is output.

Next, in step S ₆ , the inspection data clock KD is input to the input port P _1.
CK is judged whether or not the input via the controller lines C ₄ further step S ₈ in the case of NO determines whether the end signal ES is inputted, again if NO Step S ₆
Return to. Here the test data clock KDCK is applied to input port P _1.
If is input, the process proceeds to step S ₇ and the inspection data K ₁ is input from the input port P ₂ .

Next, in step S ₉ , the inspection data K ₁ is converted. As shown in Table 1, this conversion process is performed for 2 lower 15 bits of the inspection data K ₁ indicating the solid burst error length.
The polarity inversion of the binary data (2's complement generation) is performed to facilitate the subsequent arithmetic processing. The inspection data after the conversion process is K ₁ ′.

Next, in step S ₁₀ , the inspection data K ₁ ′ = [0] or [−3
2768], that is, it is determined whether or not the inspection data K ₁ ′ is the reference position detection signal. If YES, it is determined in step S ₁₁ whether FLAG 2 is 1. If YES in step S ₁₁ , check data K ₁ ′ = [− 32768] in step S ₁₂ , and if NO, step S 11.
Inspection data K ₁ by ₁₃ '= proceeds to S ₁₄ after setting the [0].
If K ₁ ′ = [− 32768] is set here, it indicates that the inspection data before the reference position detection signal is processed is the solid burst error length [1] and the writing to the RAM 11 is omitted. , K ₁ ′ = [0], it is not omitted. After the FLAG1 = 0 in step S _14, the process proceeds to step S _15. On the other hand, if NO in step S ₁₀ , the inspection data K ₁ ′ <0 in step S ₁₆ , that is, the inspection data K
₁ 'is equal to or solid burst error length or.

If YES in step S _16, test data K in step S _17
1 ′ = [− 1], that is, it is determined whether the inspection data K ₁ ′ is the solid burst error length [1], and if YES, FLAG1 = 1, that is, the inspection data K ₁ ′ is omitted in step S _19. It is determined whether or not it is possible. In the case of NO in step S ₁₇ proceeds to step S ₁₅ after the FLAG1 = 0 in step S _18.

Step If YES in step S ₁₉ S _20, S ₂₁ in FLAG1 =
0, FLAG2 = returns to step S ₆ after the 1, and if NO, it proceeds to step S ₁₅ after the FLAG1 = 0 in step S _18.

If NO in step S ₁₆ , it is further determined in step S ₂₂ whether the inspection data K ₁ ′ = [32767], that is, the inspection data K ₁ ′ is the maximum value. If YES in step S _22, step S
_23, the processing advances to step S ₁₅ after the FLAG1 = 0, in the case of NO, the process proceeds to step S ₁₅ after the FLAG1 = 1 in step S _24.

After the forward and FLAG2 = 0 in step S _15, step S ₂₅
To set write data K ₂ = inspection data K ₁ ′.

Next, in steps S ₂₆ and S ₂₇ , the address data ADD and the write data K ₂ are output from the output ports Pc and Pa, respectively, and in step S ₂₈ , the write control signal ▲ ▼ output from the output port Pb is the “L” signal. To The RAM 11 writes the write data K ₂ at the address designated by the address data ADD when the write control signal ▲ ▼ becomes the “L” signal. When the process proceeds to step S ₂₉ , the write control signal ▲ ▼ output from the output port Pb is set to the “H” signal again, and address data ADD = address data ADD + 1 (increment of address data ADD) is performed in step S ₃₀ .

Next, in step S ₃₁ , ADD> 4095, that is, address data ADD
Determines whether is within the storage capacity of RAM11 (4K words), YES
In the case of, the program ends, and in the case of NO, the process returns to step S ₆ .

Note that determines when the input wait inspection data clock KDCK and end signal ES in step S _6, S _8, when the end signal ES is inputted, the process proceeds to step S _32, whether FLAG2 = 1 or. If YES in step S _32, the write data K ₂ = at step S ₃₃ - Set to 1, step S _34, S ₃₅ at the output port Pc, respectively the address data from the Pa ADD, outputs write data K ₂ Output port P in step _S36.
Set the write control signal ▲ ▼ = "L" signal output from b. The RAM 11 writes the write data K ₂ [−1] at the address specified by the address data ADD when the write control signal ▲ ▼ becomes the “L” signal. Then step S ₃₇
Write control signal output from output port Pb at
= Return to "H" signal, and the program ends. Also as program if NO at step S ₃₂ is the end.

Next, the program of the external computer 14 will be described with reference to the flowchart of FIG.

FIG. 3 is a flowchart showing FLAG3 indicating whether or not the solid burst error length [1] is omitted, and FLAG3 = 1.
In the case of, there is omission, and in the case of FLAG3 = 0, there is no omission.

Finished the measurement of the aforementioned test data, the program is executed, the external computer 14 to enter the final address data Amax that is first output from the output port Pc of the microcomputer 10 in step S ₁₀₀ to the input port P ₃ . Next, in steps S _{101 to} S ₁₀₃ , the address data ADD, FLAG3 and the variable X are set to 0, respectively, and in step S ₁₀₄ , the read control signal ▲ ▼ output from the output port Pd is set to the “H” signal.
Then address data AD from the output port Pe in step S ₁₀₅
Outputs D, and the read control signal ▲ ▼ the "L" signal is output from the output port Pd at step S _106. The RAM 11 outputs the write data K ₂ written in the address designated by the address data ADD when the read control signal ▲ ▼ becomes the “L” signal. Then, in step _S107 , the input port P ₄
From this, the write data K ₂ is input, and the read control signal ▲ ▼ output from the output port Pd in step S ₁₀₈ is set to the “H” signal again.

Next, in step _S109 , it is determined whether or not the write data K ₂ = [0], that is, the reference position detection signal in which the solid burst error [1] has not been omitted before, and if YES, step S the process proceeds to step S ₁₁₁ after the FLAG3 = 0 at _110, and if NO, it proceeds to S _112.

In step S ₁₁₂ , it is determined whether or not the write data K ₂ = [− 32768], that is, the reference position detection signal in which the solid burst error [1] is omitted before that. If YES, step S ₁₁₃ Proceed to.

In step S ₁₁₃ , set K ₁ (X) = [− 1], and
In _S114 , X = X + 1 (increment of variable X) is performed,
Proceed to step S ₁₁₅ . Here, K ₁ (X) = [− 1] means an operation instruction to write the inspection data K ₁ = [− 1] restored at the address X of the RAM in the external computer 14. Step S (maximum value of the variable X) ₁₁₅ In the X> Xmax determines whether i.e. if the set maximum capacity of RAM in the external computer 14, if YES program becomes end, if NO step S ₁₁₆ Write data K ₂ = [0], step
After the FLAG3 = 0 in S _117, the process proceeds to step S _111.

If NO in step S ₁₁₂ , write data in step S ₁₁₈
It is determined whether or not K ₂ <0, that is, the solid burst error length. If YES in step S ₁₁₈ in step S ₁₁₀ FLAG3 =
0 and then, the process proceeds to step S _111.

If NO in step S ₁₁₈ in step S ₁₁₉ FLAG3 =
It is determined whether or not [1]. Step S If YES in ₁₁₉ the step S ₁₂₀ in _{K 1 (X) = [-} 1] and then, the step S ₁₂₁
In after incrementing the variable X, the process proceeds to step S _122, and if NO, it proceeds to a step S _123. Determining whether step in S ₁₂₂ X> Xmax, if YES program becomes end, and if NO, it proceeds to step S _123.

Step S ₁₂₃ In determining whether write data K ₂ = [32767] or, after the case of YES where the FLAG3 = 0 in step S _124, the process proceeds to step S _111, if NO in step S ₁₂₅ FL
After the AG3 = 1, the process proceeds to step S _111.

K ₁ (X) = set to write data K ₂ in step S _111, the variable X, the address data ADD is incremented at steps S _126, S _127, the process proceeds to step S _128.

Determining whether step in S ₁₂₈ X> Xmax, if YES program becomes end, if NO step S ₁₂₉
Proceed to.

In step _S129 , address data ADD> address data A
It is determined whether or not it is max. If YES, the program ends, and if NO, the process returns to step S ₁₀₅ .

Hereinafter, these operation examples will be described with reference to the timing charts of FIGS.

The numbers in <> indicate the order of operation, and the values in [] indicate data values.

The reproduction data PBD is a symbol value in which an error occurs when the symbol value [D ₁ ] to [Dn] is added to the reproduction data PBD, and the count value of the run length counter 9 and the address data value of the RAM 11 are in decimal notation. Represent.

(1) Recording of data series The data generator 2 is controlled by the recording controller 1.
The data sequence Mseq is output in the order of the start pattern, test pattern, and end pattern. This data series Mseq is EFM
It is EFM-modulated by the modulator 3 and recorded by an optical recording / reproducing apparatus 4 on a disc to be inspected (not shown) in the prescribed format.

(2) Test Data Detection Process and Writing Data to RAM 11 Next, the disc to be inspected on which the data series Mseq is recorded is reproduced by the optical recording / reproducing device 4. The reproduction data M.PBD output from the optical recording / reproducing device 4 is EFM demodulated by the EFM demodulator 5 to become reproduction data PBD.

The reproduction system controller 8 reads the value of the reproduction data PBD at the timing of the data clock PDCK output from the EFM demodulator 5 and detects the start pattern thereof. When the reproduction system controller 8 detects the start pattern, it controls the data generator 6 by the control line C ₂ to reproduce the reproduction data PB.
D and the test pattern of the data sequence Mseq output from the generator 6 are synchronized. After that, the reproduction data PBD and the series Mseq are output in synchronization with the data clock PDCK. The data comparator 7 compares the synchronized reproduction data PBD with the data value of the data series Mseq to determine an error in the reproduction data PBD.

When the reproduction system controller 8 detects the start pattern of the reproduction data PBD, it initializes the run length counter 9 by the control line C ₃ to clear the counter value, and outputs the start signal SS to the microcomputer 10. The microcomputer 10 executes a program by entering a start signal SS, the address data ADD in step S ₁ ~S _3, FLAG1, FLAG
Set 2 to 0 respectively. Next, in step S ₄ , write control signal ▲ ▼ is changed to “H” signal, and in step S ₅ , output port
The Pc address data output is set to [0]. After that step
By S _6, S ₈ waits for an input of the test data clock KDCK or end signal ES.

The case of the normal EF run length and the solid burst error length (excluding [1]) is assumed and described in FIG. 4 (a).

The data comparator 7 receives the symbol value [D ₁ ] of the reproduction data PBD <1> synchronized with the data clock PDCK <0> and the data sequence M.
The symbol value [d ₁ ] of seq <1> is determined to be the same, and the error pattern COMP <2> is set to the “H” signal. The run length counter 9 sets the count length <4> to [1] by the count clock ECK <3>.

In the same manner, the data comparator 7 outputs the data clocks <5>, <
10> and <15> are determined to be the same for both symbol values, and the run length counter 9 uses the count clock <8>,
Count value <9>, <14 by <13>, <18>
> And <19> are defined as [2], [3], and [4].

Next, the data comparator 7 determines that the symbol value [D ₅ ′] of the reproduction data PBD <21> synchronized with the data clock PDCK <20> and the symbol value [d ₅ ] of the data sequence Mseq <21> are different, The error pattern COMP <22> is set to the “L” signal. When the reproduction system controller 8 outputs the inspection data clock KDCK <23> due to the inversion of the error pattern COMP, the microcomputer 10 advances from step S ₆ to S ₇ , and the value [0] of the first block, The inspection data K _{1 including} the value [4] of the second block is input, and the inspection data K ₁ ′ is set to [4] by the conversion process of step S ₉ . After that, steps S ₁₀ , S ₁₆ , S ₂₂
The inspection data K ₁ '[4] is determined that EF run length (excluding the 32767]), the FLAG1 to 1 in step S _24, S ₁₅ by, FLA
Set G2 to 0. Next, in step S ₂₅ , write data K ₂
[4] and then, by the address data ADD to <24> output from the output port Pc in step S ₂₆ [0], the step S ₂₇
The write data K ₂ <25> output from the output port Pa at is set to [4]. The data output from these output ports Pa and Pc is output and held until the next data is output. Next, in step S ₂₈ , the write control signal ▲ ▼ <26> output from the output port Pb is set to the “L” signal, and the data [4] is written to the address [0] of the RAM 11.
Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [1]. This address data ADD [1]
Is within the storage capacity of the RAM 11, the process returns from step S ₃₁ to step S ₆ , and the microcomputer 10 again waits for input of the inspection data clock KDCK or the end signal ES. Next, the reproduction system controller 8 outputs a clear signal CLR <27> accompanying the inspection data clock KDCK <23>, and the count value <28> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 sets the count value <30> to [1] by the count clock ECK <29>. Where the error pattern CO
Delay time since MP <22> became "L" signal
The delay time set in 15 is reached and the polarity signal KS <31> is "H".
Become a signal.

Next, the data comparator 7 determines that the symbol value [D ₆ ′] of the reproduction data PBD <33> synchronized with the data clock PDCK <32> and the symbol value [d ₆ ] of the data sequence Mseq <33> are different, The error pattern COMP <34> is set to the “L” signal. The run length counter 9 sets the count value <36> to [2] by the count clock ECK <35>.

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <38> to synchronize the data clock PDCK <37> and [D _7] data series Mseq symbol value <38> a [d _7] the same, an error The pattern COMP <39> is the “H” signal. Inspection data clock KDCK <40 due to inversion of error pattern COMP
> Is output, the microcomputer 10 proceeds from step S ₆ to step S ₇ and inputs the inspection data K ₁ having the value [1] of the first block and the value [2] of the second block. _The inspection data K ₁ ′ is set to [−2] by the conversion processing of ₉ . After that step
The inspection data K ₁ ′ [−2] is determined to be the solid burst error length (excluding [1]) by S ₁₀ , S ₁₆ and S ₁₇ , and FLAG1 and FLAG2 are set to 0 in steps S ₁₈ and S ₁₅ . Then the write data K ₂ and [-2] At step S _25, step S
Outputs <41> address data ADD [1] at _26, and outputs <42> write data K ₂ [-2] in step S _27. Then write control signal in step S ₂₈ ▲ ▼ <43> the "L"
Data [-2] at address [1] of RAM11 as a signal
Write in. Then write control signal in step S ₂₉ ▲ ▼
Returns to "H" signal increments the address data ADD in step S ₃₀ and [2]. This address data
Since ADD [2] is within the storage capacity of RAM 11, step S ₃₁
Returns to the S ₆ from, the microcomputer 10 again inspection data clock KD
Waiting for input of CK or end signal ES. Next, the reproduction system controller 8 outputs a clear signal CLR <44> accompanying the inspection data clock KDCK <40>, and the count value <45> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 sets the count value <47> to [1] by the count clock ECK <46>. Here, the elapsed time after the error pattern COMP <39> becomes “H” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS
<48> becomes the “L” signal.

Next, a case where the solid burst error length [1] is next to the EF run length (excluding [32767]) will be described with reference to FIG.

After the data clock PDCK <37>, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 outputs the count value <86> at the time when the count clock <85> is output.
Let> be [8].

Next, the data comparator 7 determines that the symbol value [D ₁₅ ′] of the reproduction data PBD <88> synchronized with the data clock PDCK <87> and the symbol value [d ₁₅ ] of the data sequence Mseq <88> are different, The error pattern COMP <89> is set to the “L” signal. When the inspection data clock KDCK <90> is output due to the inversion of the error pattern COMP, the microcomputer 10 performs step S ₆
Proceeds to S ₇ from the value of the first block [0], enter the inspection data K ₁ consisting the value of the second block [8], the test data K ₁ 'in the conversion process of step S ₉ [ 8]. After that, the inspection data K ₁ ′ [8] is obtained by steps S ₁₀ , S ₁₆ and S ₂₂ .
Is determined as the EF run length (excluding [32767]), and the step
The S _24, S ₁₅ in FLAG1 to 1, set the FLAG2 to 0. Then set the write data K ₂ [8] in step S _25, output to <91> address data ADD [2] in step S _26, outputs the write data K ₂ [8] in step S ₂₇ <92 > Do. Then write control signal in step S ₂₈ ▲ ▼ <93> the "L"
The data [8] is written to the address [2] of the RAM 11 as a signal. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [3]. This address data AD
D [3] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the microcomputer 10 will again test data clock KDCK
Alternatively, it waits for the end signal ES to be input. Next, the reproduction system controller 8 outputs the clear signal CLR <94> accompanying the inspection data clock KDCK <90>, and the count value <95> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 uses the count clock ECK <96> to
The count value <97> is set to [1]. Here, the elapsed time after the error pattern COMP <89> becomes the “L” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <98
> Becomes the “H” signal.

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <100> to be synchronized to the data clock PDCK <99> and [D _16] data series Mseq symbol value <100> to [d _16] the same, an error The pattern COMP <101> is the “H” signal. Inspection data clock due to inversion of error pattern COMP
When KDCK <102> is output, the microcomputer 10 Step S ₆
Proceeds to S ₇ from the value of the first block [1], enter the inspection theta K ₁ consisting the value of the second block [1], the test data K ₁ 'in the conversion process of step S ₉ [ -1].
After that, in steps S ₁₀ , S ₁₆ and S ₁₇ , the inspection data K ₁ ′ [−
1] is determined to be the solid burst error length [1], and it is determined in step S ₁₉ whether FLAG1 is 1 or not. Here, since the FLAG1 is set to 1 before the inspection data (EF runlength [8]), to 0 FLAG1 at step S _20, S _21, sets the FLAG2 to 1, the inspection data K ₁ to RAM11 ′ [-1] is not written and the process returns to step S ₆ and the inspection data clock KDCK is returned.
Alternatively, it waits for the end signal ES to be input. Next, the reproduction system controller 8 outputs a clear signal CLR <103> accompanying the inspection data clock KDCK <102>, and the run length counter 9
The count value <105> of is cleared to [0]. Next, the run length counter 9 sets the count value <106> to [1] by the count clock ECK <105>. Here, the time elapsed after the error pattern COMP <101> becomes the “H” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <107> becomes the “L” signal.

Next, a case where the EF run length is [32767] or more is assumed and described in FIG. 4 (c).

After the data clock PDCK <99>, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 outputs the count value <1> when the count clock <136> is output.
Let 37> be [32767]. At this point, the run length counter 9 outputs an overflow detection signal to the reproduction system controller 8. When the reproduction system controller 8 receives this overflow detection signal, the inspection data clock KDCK <at the same timing as when the polarity of the error pattern COMP is reversed.
141> is output.

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <139> to be synchronized to the data clock PDCK <138> and [D _32783] Data series Mseq symbol value <139> to [d _32783] the same, an error The pattern COMP <140> is set to the “H” signal. When the inspection data clock KDCK <141> is output along with the overflow detection signal, the microcomputer 1
For 0, the process proceeds from step S ₆ to S ₇ , and the inspection data K _{1 including} the value [0] of the first block and the value [32767] of the second block is input, and the inspection data is converted by the conversion process of step S _9.
Let K ₁ ′ be [32767]. After that, the inspection data K ₁ ′ [32767] is determined to be the EF run length [32767] in steps S ₁₀ , S ₁₆ and S ₂₂ , and both FLAG1 and FLAG2 are set to 0 in steps S ₂₃ and S ₁₅ . Next, in step S ₂₅ , the write data K _{2 is set} to [3276
Set 7], the address data ADD [3 in step S _26]
Outputs <142>, and write data K ₂ [32 in step S ₂₇
767] is output. Next, in step S ₂₈ , write control signal ▲
▼ Set <144> to "L" signal and write data [32767] to address [3] of RAM11. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and the step S
_{At 30} , the address data ADD is incremented to [4]. The address data ADD [4] is returned to S ₆ from step S ₃₁ since it is the storage capacity of RMA11, becomes again waits for input test data clock KDCK or end signal ES.
Next, from the playback system controller 8, check data clock KD
Clear signal CLR <145> is output according to CK <141>,
The count value <146> of the run length counter 9 is cleared to become [0]. Next, the run length counter 9 sets the count value <148> to [1] by the count clock ECK <147>.
And

Next, the case where the EF run length [32767] is followed by the solid burst error length (excluding [1]) will be described with reference to FIG.

After the data clock PDCK <138>, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 sets the count value <178> to [32767] at the time when it is output from the count clock <177>. . At this point, the run length counter 9 outputs an overflow detection signal to the reproduction system controller 8.

Next, the data comparator 7 determines the symbol value [D ₆₅₅₅₀ ′] of the reproduction data PBD <180> synchronized with the data clock PDCK <179>.
And the symbol value [d ₆₅₅₅₀ ] of the data series Mseq <180> are different, and the error pattern COMP <181> is set to the “L” signal. With the inversion of the overflow detection signal and the error pattern COMP, the inspection data clock KDCK <182
> Is output, the microcomputer 10 proceeds from step S ₆ to step S ₇ and inputs the inspection data K _{1 including} the value [0] of the first block and the value [32767] of the second block, and the step S
_The inspection data K ₁ ′ is set to [32767] in the conversion process of ₉ . After that, the inspection data K ₁ [32767] is obtained in steps S ₁₀ , S ₁₆ and S ₂₂ .
Determines that the EF run length [32767], FLAG1 at step S _23, S ₁₅
And FLAG2 are both set to 0. Next, write data K ₂ in step S ₂₅ is set to [32767], outputs <183> address data ADD [4] in step S _26, outputs the write data K ₂ [32767] In step S ₂₇ <184 > Do. Next, in step S ₂₈ , the write control signal ▲ ▼ <185> is set to the “L” signal, and the data [32767] is written to the address [4] of the RAM 11. Next, in step S ₂₉ , the write control signal ▲ ▼ is set to "H".
Back to signal increments the address data ADD in step S ₃₀ and [5]. This address data ADD
Since [5] is within the storage capacity of the RAM 11, from step S ₃₁
Returning to S ₆ , the microcomputer 10 again waits for input of the inspection data clock KDCK or the end signal ES. Next, the reproduction system controller 8 outputs a clear signal CLR <186> accompanying the inspection data clock KDCK <182>, and the count value <187> of the run length counter 9 is cleared to [0].
Next, the run length counter 9 sets the count value <189> to [1] by the count clock ECK <188>. Here, the time elapsed after the error pattern COMP <181> becomes the “L” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <190> becomes the “H” signal.

Next, the data comparator 7 determines the symbol value [D ₆₅₅₅₁ ′] of the reproduction data PBD <192> synchronized with the data clock PDCK <191>.
And the symbol value [d ₆₅₅₅₁ ] of the data series Mseq <192> are different, and the error pattern COMP <193> is set to the “L” signal. Run length counter 9 count clock ECK <194
>, The count value <195> is set to [2].

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <197> to be synchronized to the data clock PDCK <196> and [D _65552] Data series Mseq symbol value <197> to [d _65552] the same, an error The pattern COMP <198> is set to the “H” signal. When the inspection data clock KDCK <199> is output due to the inversion of the error pattern COMP, the microcomputer 10 proceeds from step S ₆ to step S ₇ , and the first block value [1], second block
The inspection data K ₁ consisting of the block value [2] and the inspection data K ₁ ′ is [-2] by the conversion process in step S ₉ .
And After that, the inspection data K is obtained in steps S ₁₀ , S ₁₆ and S _17.
1 '[-2] it is determined that a solid burst error length (excluding [1]), setting the step S _18, S ₁₅ in FLAG1 and FLAG2 both zero. Next, in step S ₂₅ , write data D ₂
It was set to [-2], the address data ADD in step S ₂₆
Output [5] <200> and write data K _{2 in} step S _27.
<201> is issued from [-2]. Next, in step S ₂₈ , the write control signal ▲ ▼ <202> is set to the “L” signal, and the data [−2] is written to the address [5] of the RAM 11. Next step
The write control signal ▲ ▼ is returned to the “H” signal in S ₂₉ , and the address data ADD is incremented to [6] in step S ₃₀ . The address data ADD [6] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the input again waits for the test data clock KDCK or end signal ES. Next, the reproduction system controller 8 outputs the clear signal CLR <203> accompanying the inspection data clock KDCK <199>, and the count value <204> of the run length counter 9 is cleared to become [0]. Next, the run length counter 9 receives the count value <206> by the count clock ECK <205>.
Is [1]. Here, the time elapsed after the error pattern COMP <198> becomes the “H” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <207> becomes the “L” signal.

Next, the case where the EF run length [32767] is followed by the solid burst error length [1] will be described with reference to FIG.

After the data clock PDCK <208>, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 sets the count value <236> to [32767] when the count clock <235> is output. . At this point, the run length counter 9 sends an overflow detection signal to the reproduction system controller 8
Output to.

Next, the data comparator 7 determines the symbol value [D ₉₈₃₁₉ ′] of the reproduction data PBD <238> synchronized with the data clock PDCK <237>.
And the symbol value [d ₉₈₃₁₉ ] of the data series Mseq <238> are different, and the error pattern COMP <239> is set to the “L” signal. The overflow detection signal and the error pattern
Inspection data clock KDCK <240> due to inversion of COMP
Is output, the microcomputer 10 proceeds from step S ₆ to step S ₇ and inputs the inspection data K _{1 including} the value [0] of the first block and the value [32767] of the second block, and the step S
_The inspection data K ₁ ′ is set to [32767] in the conversion process of ₉ . After that, the inspection data K ₁ ′ [32767] by steps S ₁₀ , S ₁₆ and S ₂₂
Was determined that the EF run length [32767], FLA in step S _23, S ₁₅
G1 and FLAG2 are both set to zero. Next, in step S ₂₅ , write data K ₂ is set to [32767], in step S ₂₆ address data ADD [6] is output <241>, and in step S ₂₇
Write data K ₂ [32767] is output with <242>. Next, with the write control signal ▲ ▼ the <243>"L" signal in step S _28, writing data [32767] to RAM11 address [6]. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [7]. This address data AD
D [7] is returned to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the microcomputer 10 will again test data clock KDCK
Alternatively, it waits for the end signal ES to be input. Next, the reproduction system controller 8 outputs the clear signal CLR <244> accompanying the inspection data clock KDCK <240>, and the run length counter 9
The count value <245> of is cleared to [0]. Next, the run length counter 9 sets the count value <247> to [1] by the count clock ECK <246>. Here, the time elapsed after the error pattern COMP <239> becomes the “L” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <248> becomes the “H” signal.

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <250> to be synchronized to the data clock PDCK <249> and [D _97320] Data series Mseq symbol value <250> to [d _98320] the same, an error The pattern COMP <251> is set to the “H” signal. When the inspection data clock KDCK <252> is output due to the inversion of the error pattern COMP, the microcomputer 10 proceeds from step S ₆ to S ₇ and proceeds to the first block value [1] and the second block value [1]. 1] Enter the inspection data K ₁ consisting of
The inspection data K ₁ ′ is set to [−1] in the conversion process of step S ₉ . After that, in steps S ₁₀ , S ₁₆ , and S ₁₇ , the inspection data K ₁ ′
[-1] is determined as the solid burst error length [1],
In step S ₁₉ , it is determined whether FLAG1 is 1. FLAG here
Since previous 1 is set to 0 by the inspection data (EF run length [32767]), FLAG1 and F in step S _18, S ₁₅
Set both LAG2 to 0. Then set the write data K ₂ to [-1] in step S _25, the address data ADD [7] Output <253> and in step S _26, outputs the write data K ₂ [-1] in Step S ₂₇ <244> Then step S ₂₈
To change the write control signal ▲ ▼ <255> to “L” signal and
Write data [-1] to address [7] of AM11. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [8]. This address data ADD [8] is RAM
Since 11 is in the storage capacity of the returns from step S ₃₁ to S _6,
The input of the inspection data clock KDCK or the end signal ES is awaited again. Next, the reproduction system controller 8 outputs a clear signal CLR <256> accompanying the inspection data clock KDCK <252>, and the count value <257> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 receives the count value <259 by the count clock ECK <258>.
> As [1]. Here, the error pattern COMP <251>
Becomes the delay time set by the delay circuit 15, and the polarity signal KS <260> becomes the “L” signal.

Next, a case where the reference position detection signal RSYNC is input during counting of the EF run length will be described with reference to FIG. 4 (f).

After the data clock PDCK <249>, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 sets the count value <290> to [7] when the count clock <289> is output. .

When the reference position detection signal RSYNC is input between the data clocks PDCK <286> and <291>, the data comparator 7 first reproduces the reproduction data P synchronized with the data clock PDCK <291>.
Symbol value [D ₉₈₃₂₇ ] of BD <292> and data sequence Mseq <2
The symbol value [ _d98327 ] of 92> is determined to be the same, and the error pattern COMP <293> is set to the “H” signal. When the first inspection data clock KDCK <294> is output in accordance with the next input reference position detection signal RSYNC, the microcomputer 10 proceeds from step S ₆ to S ₇ , and the value of the first block [0] , Second
The inspection data K ₁ consisting of the block value [7] and the inspection data K ₁ ′ is set to [7] by the conversion process in step S ₉ . After that, the inspection data is obtained in steps S ₁₀ , S ₁₆ and S _22.
Judge K ₁ ′ [7] as the EF run length (excluding [32767]),
Step S _24, S ₁₅ in FLAG1 to 1, set the FLAG2 to 0. Next, the write data K ₂ is set to [7] in step S ₂₅ , and the address data ADD [8] is output in step S ₂₆ <29.
5>, and the write data K ₂ [7] is output in step S ₂₇ <29
6> Do. Next, in step S ₂₈ , the write control signal ▲ ▼ <
The data [7] is written in the address [8] of the RAM 11 by setting 297> to the “L” signal. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [9]. The address data ADD [9] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, again checking the data clock KDCK
Alternatively, it waits for the end signal ES to be input. Next, the clear signal CLR <298> is output in accordance with the inspection data clock KDCK <294>, and the count value <299> of the run length counter 9 is cleared to [0]. Next, when the second inspection data clock KDCK <300> is output in accordance with the reference position detection signal RSYNC, the microcomputer 10 advances from step S ₆ to S ₇ , and the value of the first block [0], The inspection data K ₁ consisting of the value [0] of the second block is input, and the inspection data K ₁ ′ is set to [0] by the conversion process of step S ₉ . After that, in step S ₁₀ , the inspection data K ₁ [0] is discriminated as the reference position detection signal,
Step S ₁₁ in FLAG2 it is determined whether 1. FLAG here
Since 2 is set to 0 by the previous inspection data K ₁ ′ (EF run length [7]), the inspection data K ₁ ′ is set to [0] (before the solid burst error length [1] in step S ₁₃ ). Is a reference position detection signal that is not omitted), and step
FLAG1 and FLAG2 in S _14, S ₁₅ is set to 0. Then set the write data K ₂ [0] at step S _25. Outputs the address data ADD [9] in step S ₂₆ to <301>,
Outputs the write data K ₂ [0] at step S ₂₇ <302> to. Next, in step S ₂₈ , the write control signal ▲ ▼ <303>
Is set to the "L" signal, and the data [0] is written to the address [9] of the RAM 11. Then write control signal in step S ₂₉ ▲
▼ is returned to the “H” signal, and the address data ADD is incremented to [10] in step S ₃₀ . The address data ADD [10] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the input again waits for the test data clock KDCK or end signal ES. Next, the clear signal CLR <304> is output in accordance with the inspection data clock KDCK <300>, and the count value <305> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 sets the count value <307> to [1] by the count clock ECK <306>.

Next, the data comparator 7 determines that both data values synchronized with the data clock PDCK <308> are the same, and the run length counter 9 uses the count clock ECK <311> to determine the count value <
Let 312> be [2].

Next, a case where the reference position detection signal RSYNC is input while counting the solid burst error length will be described with reference to FIG. 4 (g).

Data comparator 7 determines the symbol value of the reproduced data PBD <314> to be synchronized to the data clock PDCK <313> and [D ₉₈₃₂₉ '] data series Mseq symbol value <314> [d _98329] and different error patterns COMP <315> is set to “L” signal. The inspection data clock KDCK <316> is output along with the inversion of the error pattern COMP, and the microcomputer 10 performs step S
_{From 6} to S ₇ , the inspection data K ₁ consisting of the first block value [0] and the second block value [2] is input, and the inspection data K ₁ ′ is converted by the conversion process of step S _3. [2].
After that, the inspection data K ₁ ′ is obtained by steps S ₁₀ , S ₁₆ and S _22.
[2] was determined that EF run length (excluding the 32767]), the FLAG1 at step S _24, S ₁₅ to 1, set the FALG2 to 0. Next, write data K ₂ is set to [2] in step S ₂₅ , and address data ADD [10] is output in step S ₂₆ <317>
Then, write data K ₂ [2] is output in step S ₂₇ <318>
To do. Then write control signal in step S ₂₈ ▲ ▼ <319
> Is set to the “L” signal, and the data [2] is written to the address [10] of the RAM 11. Then write control signal in step S ₂₉ ▲
▼ is returned to the “H” signal, and the address data ADD is incremented to [11] in step S ₃₀ . The address data ADD [11] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the input again waits for the test data clock KDCK or end signal ES. Next, the reproduction system controller 8 outputs a clear signal CLR <320> accompanying the inspection data clock KDCK <316>, and the count value <321> of the run length counter 9 is cleared to become [0].
Next, the run length counter 9 sets the count value <323> to [1] by the count clock ECK <322>. Here, the time elapsed after the error pattern COMP <315> becomes the “L” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <324> becomes the “H” signal.

After that, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 sets the count value <349> to [6] when the count lock <348> is output.

Here, when the reference position detection signal RSYNC is input between the data clocks PDCK <345> and <350>, the data comparator 7 first determines the symbol of the reproduction data PBD <351> synchronized with the data clock PDCK <350>. Value [D ₉₈₃₃₅ ′] and data string Ms
_{Judge that} the symbol value [d ₉₈₃₃₅ ] of eq <351> is different,
The error pattern COMP <352> is set to the “L” signal. When the first inspection data clock KDCK <353> is output in accordance with the next input reference position detection signal RSYNC, the microcomputer 10 advances from step S ₆ to S ₇ and the value of the first block [1 ], And the inspection data K ₁ consisting of the value [6] of the second block are input, and the inspection data K ₁ ′ is converted by the conversion processing in step S _9.
Is set to [-6]. Thereafter, the inspection data K ₁ ′ [−6] is determined as the solid burst error length (excluding [1]) in steps S ₁₀ , S ₁₆ and S ₁₇ , and FLAG 1 is determined in steps S ₁₈ and S ₁₅ .
And FLAG2 are both set to 0. Then set the write data K ₂ in the -6 At step S _25, the address data ADD [11] Output <354> and in step S _26, outputs the write data K ₂ [-6] In step S ₂₇ <355> Next, in step S ₂₈ , the write control signal ▲ ▼ <356> is set to the “L” signal, and the data [−6] is written in the address [11] of the RAM 11. Next, in step S ₂₉ , the write control signal ▲ ▼ is set to "H".
Back to signal increments the address data ADD in step S ₃₀ and [12]. This address data ADD [1
2] is within the storage capacity of the RAM 11, so steps S ₃₁ to S ₆
Return to inspection data clock KDCK or end signal again
Waiting for ES input. Next, inspection data clock KDCK <35
A clear signal CLR <357> is output according to 3>, and the count value <358> of the run length counter 9 is cleared to [0]. Then with the reference position detection signal RSYNC, the second examination data clock KDCK <359> is output, the microcomputer 10 proceeds from step S ₆ to S _7, the value of the first block [1], the The inspection data K _{1 including} the value [0] of the block of 2 is input, and the inspection data K ₁ ′ is converted by the conversion process in step S _9.
Is [-32768]. Thereafter Step S ₁₀ by the inspection data K ₁ 'determines that the reference position detection signal [-32768], FLAG2 in step S ₁₁ it is determined whether or not 1. Here FLAG2 previous inspection data K ₂ (Solid burst error length [6])
Since it is set to 0, the [0] inspection data K ₁ 'in step S ₁₃ and (the reference position detection signal Solid burst error length [1] is not omitted before), also step S _14, both FLAG1 and FLAG2 in S ₁₅ is set to 0. Next, the write data K ₂ is set to [0] in step S ₂₅ , and the address data ADD [12] is output in step S _26.
360>, and K ₂ [0] is output as the write data <361> in step S ₂₇ . Next, in step S ₂₈ , write control signal ▲
▼ Set <362> to "L" signal and write data [0] to address [12] in RAM11. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [13]. The address data ADD [13] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, again checking the data clock K
Waiting for DC or end signal ES input. Next, the clear signal CLR <363> is output in accordance with the inspection data clock KDCK <359>, and the count value <364> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 receives the count value <366 by the count clock ECK <365>.
> As [1].

Next, the data comparator 7 determines that both data values synchronized with the data clock PDCK <367> are the same, and the run length counter 9 uses the count clock ECK <370> to determine the count value <
371> as [2].

Next, the case where the reference position detection signal RSYNC is input during counting the EF run length and the solid burst error length [1] continues further will be described with reference to FIG. 4 (h).

Data comparator 7 determines the symbol value of the reproduced data PBD <373> to be synchronized to the data clock PDCK <372> and [D _98337] Data series Mseq symbol value <373> to [d _98337] the same, the error pattern COMP <374> is the “H” signal.
Inspection data clock accompanying error pattern COMP inversion
KDCK <375> is output, the microcomputer 10 S from step S ₆
Proceed to ₇ and input the inspection data K ₁ consisting of the value [1] of the first block and the value [2] of the second block, and step
The inspection data K ₁ ′ is set to [−2] in the conversion process of S ₉ . After that, in steps S ₁₀ , S ₁₆ and S ₁₇ , the inspection data K ₁ ′ [-2]
Was determined that the solid burst error length (excluding [1]) to set the FLAG1 and FLAG2 in step S _18, S ₁₅ are both zero. Next, write data K ₂ in step S ₂₅ [-2]
Set, outputs <376> address data ADD [13] In step S _26, the write data K ₂ output [-2] <377> in step S ₂₇ to. Next, in step S ₂₈ , write control signal ▲
▼ Set <378> to the “L” signal and set the address [1] of RAM11.
Write data [-2] in [3]. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [14]. The address data ADD [14] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the input again waits for the test data clock KDCK or end signal ES. Next, from the playback system controller 8, check data clock KDCK
The clear signal CLR <379> associated with <375> is output, and the count value <380> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 sets the count value <382> to [1] by the count clock ECK <381>.
And Here, the time elapsed after the error pattern COMP <374> becomes the “H” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <383> becomes the “L” signal.

After that, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 sets the count value <408> to [6] when the count clock <407> is output.

Here, when the reference position detection signal RSYNC is input between the data clocks PDCK <404> and <409>, the data comparator 7 first determines the symbol of the reproduction data PBD <410> synchronized with the data clock PDCK <409>. Value [D ₉₈₃₄₃ ′] and data series
It is determined that the symbol value [ _d98343 ] of Mseq <410> is different, and the error pattern COMP <411> is set to the “L” signal. If then first test data clock KDCK <412> with the inversion of the reference position detection signal RSYNC and error pattern is outputted, the microcomputer 10 proceeds from step S ₆ to S _7, the value of the first block [ 0], enter the inspection data K ₁ consisting the value of the second block [6], and [6] the inspection data K ₁ 'in the conversion process of step S _9. After that, steps S ₁₀ and S
_16, the inspection data K ₁ '[6] The EF run length by S ₂₂ ([327
67] determines that the exception), the FLAG1 at step S _24, S ₁₅ 1
And set FLAG2 to 0. Then set the write data K ₂ [6] in step S _25, output to <413> address data ADD [14] In step S _26, outputs the write data K ₂ [6] in step S ₂₇ <414 > Do. Next, in step S ₂₈ , the write control signal ▲ ▼ <415> is set to the “L” signal, and the RAM 11
Write the data [6] to the address [14] of. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [15]. The address data ADD [15] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the input again waits for the test data clock KDCK or end signal ES. Next, the clear signal CLR <416> is output in accordance with the inspection data clock KDCK <412>, and the count value <417> of the run length counter 9 is cleared to [0]. Then with the reference position detection signal RSYNC, the second examination data clock KDCK <418> is output, the microcomputer 10 proceeds from step S ₆ to S _7, the value of the first block [0], the Two
The inspection data K ₁ consisting of the block value [0] and the inspection data K ₁ ′ is set to [0] by the conversion process in step S ₉ . Thereafter Step S ₁₀ by the inspection data K ₁ 'determines that the reference position detection signal [0], FLAG2 in step S ₁₁ it is determined whether or not 1. Here FLAG2 is the previous inspection data K ₁ ′ (E
Since it is set to 0 by the F run length [6]), the inspection data K ₁ ′ is set to [0] (the reference position detection signal in which the solid burst error length [1] is not omitted before that) in S _13. and a step S _14, S ₁₅ in FLAG1 and FLAG2 are 0
Set to. Then set the write data K ₂ [0] at step S _25, the address data ADD [1 at step S ₂₆
Outputs 5 and <419>, the write data K in step S _27
2 Outputs [0] <420>. Next, in step S ₂₈ , the write control signal ▲ ▼ <421> is set to the “L” signal, and the data [0] is written in the address [15] of the RAM 11. Then step S
_{At 29} , the write control signal ▲ ▼ is returned to the “H” signal, and at step S ₃₀ , the address data ADD is incremented [16].
And The address data ADD [16] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the input again waits for the test data clock KDCK or end signal ES. Next, the clear signal CLR <422> is output in accordance with the inspection data clock KDCK <418>, and the count value <423> of the run length counter 9 is cleared to become [0]. Next, the run length counter 9 sets the count value <425> to [1] by the count clock ECK <424>. Here, the elapsed time after the error pattern COMP <411> becomes the “L” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <42
6> becomes “H” signal.

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <428> to be synchronized to the data clock PDCK <427> and [D _98344] Data series Mseq symbol value <428> to [d _98344] the same, an error The pattern COMP <429> is set to the “H” signal. The inspection data clock KDCK <430> is output as the error pattern COMP is inverted, and the microcomputer 10 performs step S
_{From 6} to S ₇ , the inspection data K ₁ consisting of the value [1] of the first block and the value [1] of the second block is input, and the inspection data K ₁ ′ is converted by the conversion process of step S _9. [-1]. After that, in steps S ₁₀ , S ₁₆ , and S ₁₇ , the inspection data K ₁ ′
[-1] is determined as the solid burst error length [1],
In step S ₁₉ , it is determined whether FLAG1 is 1. FLAG here
Since 1 is set to 0 by the previous inspection data (reference position detection signal), FLAG1 and F in step S _18, S ₁₅
Set both LAG2 to 0. Then set the write data K ₂ [-1] in step S _25, output to <431> address data ADD [16] In step S _26, outputs the write data K ₂ [-1] in Step S ₂₇ <432> Then write control signal in step S ₂₈ ▲ ▼ the <433> in the "L" signal, RAM
Write data [-1] to address [16] of 11. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [17]. This address data ADD [17] is RAM
Since 11 is in the storage capacity of the returns from step S ₃₁ to S _6,
The input of the inspection data clock KDCK or the end signal ES is awaited again. Next, the reproduction system controller 8 outputs a clear signal CLR <434> associated with the inspection data clock KDCK <430>, and the count value <435> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 sets the count value <437 by the count clock ECK <436>.
> As [1]. Here, the error pattern COMP <429>
Becomes the "H" signal, the elapsed time becomes the delay time set by the delay circuit 15, and the polarity signal KS <438> becomes the "L" signal.

Next, the case where the reference position detection signal RSYNC is input next to the solid burst error length [1] will be described with reference to FIG. 4 (i).

After the data clock <439>, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 outputs the count value <463> at the time when the count clock <462> is output.
> As [6].

Data comparator 7 determines the symbol value of the reproduced data PBD <465> to be synchronized to the data clock PDCK <464> and [D ₉₈₃₅₀ '] data series Mseq symbol value <465> [d _98350] and different error patterns Set COMP to “L” signal. Inspection data clock KDCK <46 due to error pattern inversion
7> is output, the microcomputer 10 proceeds from step S ₆ to step S ₇ and inputs the inspection data K _{1 including} the value [0] of the first block and the value [6] of the second block, and the step S _The inspection data K ₁ ′ is set to [6] in the conversion processing of ₉ . Thereafter, the inspection data K ₁ ′ [6] is determined to be the EF run length (excluding [32767]) in steps S ₁₀ , S ₁₆ and S ₂₂ , and F is determined in steps S ₂₄ and S ₁₅ .
Set LAG1 to 1 and FLAG2 to 0. Then set the write data K ₂ [6] in step S _25, output to <468> address data ADD [17] In step S _26, outputs the write data K ₂ [6] in step S ₂₇ <469 > Do. Then step S
_{At 28} , the write control signal ▲ ▼ <470> is set to the “L” signal, and the data [6] is written to the address [17] of the RAM 11.
Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [18]. This address data ADD [18]
Is within the storage capacity of the RAM 11, the process returns from step S ₃₁ to step S ₆ , and the input of the inspection data clock KDCK or the end signal ES is awaited again. Next, inspection data clock KDCK <467>
A clear signal CLR <471> is output, and the count value <472> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 count clock ECK <473
>, The count value <474> is set to [1]. Here, the elapsed time after the error pattern COMP <466> becomes “L” signal becomes the delay time set by the delay circuit 15,
The polarity signal KS <475> becomes the “H” signal.

Here, when the reference position detection signal RSYNC is input between the data clocks PDCK <464> and <476>, the data comparator 7 first determines the symbol of the reproduction data PBD <477> synchronized with the data clock PDCK <476>. Value [D ₉₈₃₅₁ ] and data series Ms
The symbol value [ _d98351 ] of eq <477> is determined to be the same, and the error pattern COMP <478> is set to the “H” signal. Next, when the first inspection data clock KDCK <479> is output due to the inversion of the reference position detection signal RSYNC and the error pattern, the microcomputer 10 advances from step S ₆ to S ₇ and the value of the first block [ 1], enter the inspection data K ₁ consisting the value of the second block [1], the test data K ₁ 'in the conversion process of step S ₉ and [-1]. After that, steps S ₁₀ , S ₁₆ ,
The inspection data K ₁ '[-1] by S ₁₇ determines that the solid burst error length [1], FLAG1 at step S ₁₉ it is determined whether or not 1. FLAG1 is the previous inspection data K ₁ ′ (EF
Since it is set to 1 by the run length [6],
S _20, S ₂₁ in FLAG1 to 0, it sets the FLAG2 to 1, write data K ₁ 'Step S ₆ without writing [-1] to RAM11
Return to inspection data clock KDCK or end signal again
Waiting for ES input. Next, inspection data clock KDCK <47
The clear signal CLR <480> is output according to 9>, and the count value <481> of the run length counter 9 is cleared to [0]. Then with the reference position detection signal RSYNC, the second examination data clock KDCK <482> is output, the microcomputer 10 proceeds from step S ₆ to S _7, the value of the first block [1], the The inspection data K _{1 including} the value [0] of the block of 2 is input, and the inspection data K ₁ ′ is converted by the conversion process in step S _9.
Is [-32768]. Thereafter Step S ₁₀ by the inspection data K ₁ 'determines that the reference position detection signal [-32768], FLAG2 in step S ₁₁ it is determined whether or not 1. FLAG2 is the previous inspection data K ₁ ′ (solid burst error length [-
1]), the inspection data K ₁ ′ is set to [−32768] (reference position detection signal in which the solid burst error length [1] is omitted before that) in S ₁₃ .
Also set the FLAG1 and FLAG2 in step S _14, S ₁₅ are both zero. Next, in step S ₂₅ , the write data K ₂ is changed to [−3276
Set 8], the address data ADD in step S ₂₆ [18]
The output <438>, and write data K ₂ [-32 in Step S ₂₇
768] is output <484>. Next, in step S ₂₈ , the write control signal ▲ ▼ <485> is set to the “L” signal, and the data [−32768] is written to the address [18] of the RAM 11. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [19]. The address data ADD [19] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the input again waits for the test data clock KDCK or end signal ES. Next, the clear signal CLR <486> is output in accordance with the inspection data clock KDCK <482>, and the count value <487> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 uses the count clock ECK <488> to
The count value <489> is set to [1]. Here, the elapsed time after the error pattern COMP <478> becomes "H" signal becomes the delay time set by the delay circuit 15, and the polarity signal KS
<490> becomes the “L” signal.

Next, a case where the end signal ES is input during counting the FE run length will be described with reference to FIG. 4 (j).

After the data clock PDCK <476>, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 sets the count value <530> to [12] when the count clock <529> is output. To do.

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <532> to be synchronized to the data clock PDCK <531> and [D _98362] Data series Mseq symbol value <532> to [d _98362] the same, an error The pattern COMP <533> is set to the “H” signal. Here, the reproduction system controller 8 detects the end pattern (the reproduction data PBDs <522>, <527>, and <532> symbol values [D ₉₈₃₅₈ ] to [D ₉₈₃₆₂ ] are all [0]) and outputs an end signal. When outputting the ES, the microcomputer 10 from the step S ₈
Proceeds to S _32, FLAG2 is determined whether 1. FLAG2 here
Indicates the previous inspection data K ₁ ′ (reference position detection signal [−3276
8)), the program ends and the test data measurement ends.

Next, the case where the first test data is a solid burst error [1] will be described with reference to FIG.

The data comparator 7 determines that the symbol value [D ₁ '] of the reproduction data PBD <1> synchronized with the data clock PDCK <0> and the symbol value [d ₁ ] of the data sequence Mseq <1> are different, and the error pattern COMP <2> is set to "L" signal. Next, the run length counter 9 sets the count value <4> to [1] by the count clock ECK <3>. Here, the elapsed time after the error pattern COMP <2> becomes the “L” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <5> becomes the “H” signal.

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <7> to be synchronized to the data clock PDCK <6> and [D _2] data series Mseq symbol value <7> [d _2] the same, an error The pattern COMP <8> is set to the “H” signal. Inspection data clock KDCK <9> due to inversion of error pattern COMP
Is output, the microcomputer 10 proceeds from step S ₆ to step S ₇ and inputs the inspection data K _{1 including} the value [1] of the first block and the value [1] of the second block, and the step S _The inspection data K ₁ ′ is set to [−1] by the conversion processing of ₉ . Thereafter, the inspection data K ₁ ′ [−1] is determined as the solid burst error length [1] in steps S ₁₀ , S ₁₆ and S ₁₇ , and step S ₁₉
Determine whether FLAG1 is 1 or not. Here, since the FLAG1 is set by the initial setting step S ₂ to 0, step
The S _18, S ₁₅ in FLAG1 and FLAG2 both set to zero. Next, the write data K ₂ is set to [−1] in step S ₂₅ , and the address data ADD [0] is output <10> in step S ₂₆ ,
Outputs the write data K ₂ [-1] in Step S ₂₇ <11> to. Then write control signal in step S ₂₈ ▲ ▼ <12>
Is set to the "L" signal, and the data [-1] is written to the address [0] of the RAM 11. Next, in step S ₂₉ , the write control signal ▲ ▼ is returned to the “H” signal, and in step S ₃₀ , the address data ADD is incremented to [1]. The address data ADD [1] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, again checking the data clock KDCK
Alternatively, it waits for the end signal ES to be input. Next, the reproduction system controller 8 outputs the clear signal CLR <13> accompanying the inspection data clock KDCK <9>, and the count value <14> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 uses the count clock ECK <15> to
The count value <16> is set to [1]. Here, the time elapsed after the error pattern COMP <8> becomes the “H” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <17
> Becomes the “L” signal. Since the subsequent operation is the same as that of FIG. 4 (a), the description thereof will be omitted.

A case where the next last test data is the solid burst error length [1] will be described with reference to FIG.

After the data clock PDCK <491>, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 outputs the count value <5 at the time when the count clock <514> is output.
Let 15> be [6].

Data comparator 7 determines the symbol value of the reproduced data PBD <517> to be synchronized to the data clock PDCK <516> and [D ₉₈₃₅₇ '] data series Mseq symbol value <517> [d _98357] and different error patterns COMP <518> is set to “L” signal. When the inspection data clock KDCK <519> is output due to the inversion of the error pattern COMP, the microcomputer 10 proceeds from step S ₆ to S ₇ , and the value of the first block [0], the value of the second block [ 6] Enter the inspection data K ₁ consisting of
The inspection data K _{1 is set} to [6] in the conversion process of step S ₉ .
After that, the inspection data K ₁ ′ is obtained by steps S ₁₀ , S ₁₆ and S _22.
[6] was determined that EF run length (excluding the 32767]), the FLAG1 at step S _24, S ₁₅ to 1, set the FLAG2 to 0. Next, write data K ₂ is set to [5] in step S ₂₅ , and address data ADD [19] is output in step S ₂₆ <520>
Then, write data K ₂ [6] is output in step S ₂₇ <521>
To do. Then write control signal in step S ₂₈ ▲ ▼ <522
> Is set to the “L” signal, and the data [6] is written to the address [19] of the RAM 11. Then write control signal in step S ₂₉ ▲
▼ returns to "H" signal increments the address data ADD in step S ₃₀ and [20]. The address data ADD [20] returns to S ₆ from step S ₃₁ since it is the storage capacity of the RAM 11, the input again waits for the test data clock KDCK or end signal ES. Next, the reproduction system controller 8 outputs a clear signal CLR <523> associated with the inspection data clock KDCK <519>, and the count value <524> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 sets the count value <526> to [1] by the count clock ECK <525>. Here, the time elapsed after the error pattern COMP <518> becomes the “L” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <527> becomes the “H” signal.

Next, the data comparator 7 determines the symbol value of the reproduced data PBD <529> to be synchronized to the data clock PDCK <528> and [D _98358] Data series Mseq symbol value <529> to [d _98358] the same, an error The pattern COMP <530> is set to the “H” signal. The inspection data clock KDCK <531> is output along with the inversion of the error pattern COMP, and the microcomputer 10 performs step S ₆
Proceeds to S ₇ from the value of the first block [1], enter the inspection data K ₁ consisting the value of the second block [1], the test data K ₁ 'in the conversion process of step S ₉ [ -1].
After that, in steps S ₁₀ , S ₁₆ and S ₁₇ , the inspection data K ₁ ′ [−
1] is determined to be the solid burst error length [1], and it is determined in step S ₁₉ whether FLAG1 is 1 or not. Here, since FLAG1 is set to 1 by the previous inspection data K ₁ ′ (EF run length [6]), FLAG1 is set to 0 in steps S ₂₀ and S ₂₁ , and F
Set LAG2 to 1 without writing to the RAM 11, returns to the step S _6, the re-input waiting inspection data clock KDCK or end signal ES. Next, the reproduction system controller 8 outputs a clear signal CLR <532> associated with the inspection data clock KDCK <531>, and the count value <533> of the run length counter 9 is cleared to [0]. Next, the run length counter 9 sets the count value <535> to [1] by the count clock ECK <534>. Here, the elapsed time after the error pattern COMP <530> becomes “H” signal becomes the delay time set by the delay circuit 15, and the polarity signal KS <53
6> becomes the “L” signal. After that, the data comparator 7 determines that both symbol values are the same, and the run length counter 9 sets the count value <541> to [5] by the count clock <540>. Next, the data comparator 7 uses the data clock PD
The symbol value [D ₉₈₃₆₂ ] of the playback data PBD <543> and the symbol value [d of the data sequence Mseq <543> synchronized with CK <542>.
₉₈₃₆₂ ] is determined to be the same, and the error pattern COMP <544> is set to the “H” signal. Here, when the reproduction system controller 8 detects an end pattern (the reproduction data PBD <529>, <538>, and <543> symbol values [ _D98358 ] to [ _D98362 ] are all [0]), the end signal is detected. When outputting the ES, the microcomputer 10 proceeds to S ₃₂ from the step S _8, FLAG2 is determined whether 1.
Here, since FLAG2 is set to 1 by the previous inspection data (solid burst error length [1]), the write data K ₂ is set to [-1] in step S _33, step S
Address data output <545> to ₃₄ at ₃₄ , step S
_{At 35} , the write data output <546> is set to [-1]. Next, in step S ₃₆ , the write control signal ▲ ▼ <547> is set to the “L” signal, and the data [−1] is written in the address [20] of the RAM 11. Now back to the write control signal ▲ ▼ the "H" signal in step S _37, the program measures the test data becomes the end ends.

Table 2 shows the contents of the write data recorded at each address of the RAM 11 in the above operation example FIGS. 4 (a) to 4 (j).

As shown in Table 2, EF run length [4], solid burst error length [2], EF run length [8], EF run length [3276] is measured at each address of RAM11 after the measurement of test data is started.
7], EF run length [32767], solid burst error length [2], EF run length [32767], solid burst error length [1], EF run length [7], reference position detection signal, EF run length [2 ], Solid burst error length [6], reference position detection signal, solid burst error length [2], EF run length [6], reference position detection signal, solid burst error length [1], EF run length [6], The reference position detection signal and the inspection result of the recording medium are sequentially recorded.

(3) Reading of data from the RAM 11 and restoration of the inspection data When the measurement of the test data is completed, the external computer 14 takes in the data of the RAM 11 according to the flowchart of FIG.

The operation will be described below with reference to the flowchart of FIG.

The external computer 14 executes the program by the signal from the control line C ₅ , and in step S ₁₀₀ , the input port
Input the address data Amax [18] from P ₃ . Step
S ₁₀₁ to S ₁₀₃ in the address data ADD, FLAG3, initializes the variable X respectively [0], the read control signal ▲ ▼ the "H" signal is output from the output port Pd at step S _104. Then address data ADD from the output port Pe in step S ₁₀₅
Outputs [0], a read control signal at step S ₁₀₆ ▲
The write data K ₂ [4] written in the address [0] is output from the RAM 11 by using the ▼ as an “L” signal, and the next step
This write data K ₂ [4] is input from the input port P _{4 in} S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . After that, the write data K ₂ [4] is determined to be the EF run length in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and step S
_{At 119} , it is determined whether FLAG3 is 1 or not. Here FLAG3 it because it is set to 0 by default goes to step S _123. The write data K ₂ [4] at step S ₁₂₃ determines that the EF run length (excluding the 32767]), setting the FLAG3 in step S ₁₂₅ to 1. Next, in step _S111 , the inspection data K ₁ (0)
_Is set to [4], and the variable X is set in steps S ₁₂₆ and S _127.
[0] and the address data ADD [0] are incremented to [1] and [1], respectively. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Then outputs the address data ADD [1] at step S _105, the write data K ₂ written from RAM11 read control signal ▲ ▼ as "L" signal to the address [1] at step S ₁₀₆ the [-2] Then, the write data K ₂ [−2] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . After that, the write data K ₂ [-2] is determined as the solid burst error length in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and the FLAG is determined in step S ₁₁₀ .
Set 3 to 0. Next, in step _S111 , the inspection data K
₁ Set (1) to [-2], and then step _S126 , _S127
Then, the variable X [1] and the address data ADD [1] are incremented to [2] and [2], respectively. Steps S ₁₂₈ , S
₁₂₃ a variable X, make sure that the address data ADD is within the range respectively returns to step S _105.

Next, in step _S105 , the address data ADD [2] is output, and in step _S106 , the read control signal ▲ ▼ is used as the “L” signal and the write data K ₂ [8] written in the address [2] from the RAM 11 is output. Then, in the next step S ₁₀₇ , this write data K ₂ [8] is input, and in step S ₁₀₈ the read control signal ▲ ▼ is set to the “H” signal again. After that step S
_The write data K ₂ [8] is determined to be the EF run length in ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and it is further determined in step S ₁₁₉ whether FLAG3 is 1. Here, since FLAG3 is set to 0 before the write data K ₂ [-2] proceeds to step S _123. Step
The write data K ₂ [8] In S ₁₂₃ determines that the EF run length (excluding the 32767]), setting the FLAG3 in step S ₁₂₅ to 1. Next inspection data K ₁ (2) in step S ₁₁₁ is set to [8], the variable X [2] in step S _126, S _127, address data ADD [2] respectively incremented [3],
[3]. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [3] is output, and in step _S106 , the read control signal ▲ ▼ is used as the “L” signal and the write data K ₂ [32767] written in the address [3] from the RAM 11 is output. Then, in the next step S ₁₀₇ , this write data K ₂ [32767] is input, and in step S ₁₀₈ , the read control signal ▲ ▼ is set to the “H” signal again. After that, in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , write data K ₂ [3276
7] it was determined that EF run length, yet in step S ₁₁₉ FLAG3 1
Determine whether or not. Here, since FLAG3 is set to 1 before the write data [8], the test data K ₁ and (3) in step S ₁₂₀ is set to [-1], the variable X [3] at step S ₁₂₁ Increment to [4]. Step
After confirming that the variable X is within the range in S ₁₂₂ , step S
_Continue to ₁₂₃ . Write data K ₂ [32767] in step S ₁₂₃
It determines that the EF run length [32767], a FLAG3 in step S ₁₂₄ 0
Set to. Next, in step S ₁₁₁ , the inspection data K ₁ (4) is set to [32767], and in steps S ₁₂₆ and S ₁₂₇ , the variable X is set.
[4] and the address data ADD [3] are respectively incremented to [5] and [4]. Step S _128, variable S ₁₂₉ X, make sure that the address data ADD is within the range respectively returns to step S _105.

Next, in step _S105 , the address data ADD [4] is output, and in step _S105 , the read control signal ▲ ▼ is used as the “L” signal and the write data K ₂ [32767] written in the address [4] from the RAM 11 is output. Then, in the next step S ₁₀₇ , this write data K ₂ [32767] is input, and in step S ₁₀₈ the read control signal ▲ ▼ is set to the “H” signal again. After that, in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , write data K ₂ [3276
7] it was determined that EF run length, yet in step S ₁₁₉ FLAG3 1
Determine whether or not. FLAG3 is the previous write data [3
2767] is set to 0, so step S
_Continue to ₁₂₃ . Write data K ₂ [32767] in step S ₁₂₃
It determines that the EF run length [32767], a FLAG3 in step S ₁₂₄ 0
Set to. Next, the inspection data K ₁ (5) is set to [32767] in step S ₁₁₁ , and the variable X is set in steps S ₁₂₆ and S _127.
[5] and the address data ADD [4] are incremented to [6] and [5], respectively. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [5] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [−2] written in the address [5] from the RAM 11 is written. Is output, the write data K ₂ [-2] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . Thereafter, the write data K ₂ [-2] is determined to be the solid burst error length in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and further step S ₁₁₀
To set FLAG3 to 0. Next inspection data K ₁ (6) in step S ₁₁₁ is set to [-2], the variable X [6] in step S _126, S _127, address data ADD [5] respectively incremented [7], [ 6]. Further step S ₁₂₈ ,
Variable X in S _129, make sure that the address data ADD is within the range respectively returns to step S _105.

Next, in step _S105 , the address data ADD [6] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [32767] written in the address [6] from the RAM 11 is written. It is output, and in the next step S ₁₀₇ , this write data K ₂ [32767] is input and step S ₁₀₈ is entered.
Read control signal ▲ ▼ becomes "H" signal. After that, write data K ₂ [32767] in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ .
It was determined that the EF run length, further FLAG3 in step S ₁₁₉ it is determined whether or not 1. FLAG3 is the previous write data [-
2] is set to 0, so step S ₁₂₃ is performed as it is.
Proceed to. In step S ₁₂₃ , write data K ₂ [32767] to EF
It determines that the run length [32767], a FLAG3 in step S ₁₂₄ is set to 0. Next, the inspection data K ₁ (7) is set to [32767] in step S ₁₁₁ , and the variable X is set in steps S ₁₂₆ and S _127.
[7] and the address data ADD [6] are incremented to [8] and [7], respectively. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [7] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [−1] written from the RAM 11 to the address [7]. Is output, the write data K ₂ [−1] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . After that, the write data K ₂ [−1] is obtained in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ .
Is determined as the solid burst error length, and in step S ₁₁₀
Set FLAG3 to 0. Next, in step _S111 , the inspection data K
₁ (8) is set to [-1], and the variables X [8] and address data ADD [7] are incremented to [9] and [8] in steps _S126 and _S127 , respectively. Further steps S ₁₂₈ , S
₁₂₉ a variable X, make sure that the address data ADD is within the range respectively returns to step S _105.

Next, in step _S105 , the address data ADD [8] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [7] written in the address [8] from the RAM 11 is written. This is output and the write data K ₂ [7] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . After that step S
_The write data K ₂ [7] is determined to be the EF run length from ₁₀₉ , S ₁₁₁ and S ₁₁₈ , and it is further determined in step S ₁₁₉ whether FLAG3 is 1 or not. Here FLAG3 it so is set to the inspection data K ₂ 0 in [-1] before the process proceeds to step S _123. In step S ₁₂₃ , the write data K ₂ [7] is set to the EF run length ([3276
7] it is determined that the exception), sets the FLAG3 in step S ₁₂₅ to 1. Next, in step S ₁₁₁ , the inspection data K ₁ (9) is [7]
And the variable X [9] and the address data ADD [8] are incremented [10] in steps S ₁₂₆ and S ₁₂₇ , respectively.
[9]. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [9] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [0] written in the address [9] from the RAM 11 is written. The write data K ₂ [0] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . Next step
Determining a reference position detection signal omission is not performed in the write data K ₂ [0] Solid burst error length [1] by S _109, the FLAG3 in step S ₁₁₀ is set to 0. Next, in step _S111 , the inspection data K ₁ (10) is set to [0],
Variables X [10] and address data AD in steps S ₁₂₆ and S ₁₂₇
D [9] is incremented to [11] and [10], respectively. Further, in steps S ₁₂₈ and S ₁₂₉ , variable X and address data
Make sure that each ADD is within range and then step S
Return to ₁₀₅ .

Next, in step _S105 , the address data ADD [10] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal and the write data K ₂ [2] in which the address [10] is written from the RAM 11 is output. Then, in the next step _S107 , this write data K ₂ [2] is input, and in step _S108 , the read control signal ▲ ▼ is set to the "H" signal again. After that step S
_The write data K ₂ [2] is determined to be the EF run length in ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and it is further determined in step S ₁₁₉ whether FLAG3 is 1. Here FLAG3 it so is set to the inspection data K ₂ 0 in [0] before the process proceeds to step S _123. In step S ₁₂₃ , the write data K ₂ [2] is changed to the EF run length ([3276
7] it is determined that the excluded) to set the FLAG3 in step S ₁₂₅ to 1. Next, in step _S111 , the inspection data K ₁ (11) is [2]
And the variable X [11] and the address data ADD [10] are incremented in steps S ₁₂₆ and S ₁₂₇ , respectively, [12], [1
1]. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [11] is output, and in step _S106 , the read control signal ▲ ▼ is used as the "L" signal and the write data K ₂ [-6] written in the address [11] from the RAM 11 is written. This is output, and the write data K ₂ [-6] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . After that, the write data K ₂ [−6] is determined as the solid burst error length in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and the FLAG is determined in step S ₁₁₀ .
Set 3 to 0. Next, in step _S111 , the inspection data K ₁ (1
2) is set to [-6] and variable X is set in steps S ₁₂₆ and S _127.
[12] and the address data ADD [11] are incremented to [13] and [12], respectively. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [12] is output, and in step _S106 , the read control signal ▲ ▼ is used as the “L” signal and the write data K ₂ [0] written in the address [12] from the RAM 11 is output. Then, in the next step _S107 , the write data K ₂ [0] is input, and in step _S108 , the read control signal ▲ ▼ is set to the “H” signal again. Then step S
_{It is determined by 109} that the write data K ₂ [0] is the reference position detection signal in which the solid burst error length [1] is not omitted, and FLAG3 is set to 0 in step _S110 . Next, in step _S111 , the inspection data K ₁ (13) is set to [0],
In steps S ₁₂₆ and S ₁₂₇ , variable X [13], address data AD
D [12] is incremented to [14] and [13], respectively. Further, in steps S ₁₂₈ and S ₁₂₉ , variable X and address data
Make sure that each ADD is within range and then step S
Return to ₁₀₅ .

Next, in step _S105 , the address data ADD [13] is output, and in step _S106 , the read control signal ▲ ▼ is used as the "L" signal and the write data K ₂ [-2] written from the RAM 11 to the address [13] is output. The write data K ₂ [-2] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . After that, the write data K ₂ [-2] is determined as the solid burst error length in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and the FLAG is determined in step S ₁₁₀ .
Set 3 to 0. Next, in step _S111 , the inspection data K ₁ (1
4) is set to [-2] and the variable X is set in steps S ₁₂₆ and S _127.
[14] and the address data ADD [13] are incremented to [15] and [14], respectively. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [14] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [6] written in the address [14] from the RAM 11 is written. This is output, and the write data K ₂ [6] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is turned to the “H” signal again in step S ₁₀₈ . After that step
The write data K ₂ [6] is determined to be the EF run length in S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and it is further determined in step S ₁₁₉ whether FLAG3 is 1. Here FLAG3 previous inspection data K ₂ in [-2] 0
Since it is set to, the process directly proceeds to step S ₁₂₃ . In step S ₁₂₃ , the write data K ₂ [6] is changed to the EF run length ([3276
7] it is determined that the exception), sets the FLAG3 in step S ₁₂₅ to 1. Next, in step S ₁₁₁ , the inspection data K ₁ (15) is [6]
And the variable X [15] and the address data ADD [14] are incremented in steps S ₁₂₆ and S ₁₂₇ , respectively, [16], [1
5]. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [15] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [0] written in the address [15] from the RAM 11 is written. The write data K ₂ [0] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . Next step
Determining a reference position detection signal omission is not performed in the write data K ₂ [0] Solid burst error length [1] by S _109, the FLAG3 in step S ₁₁₀ is set to 0. Next, in step _S111 , the inspection data K ₁ (16) is set to [0],
Variables X [16] and address data AD in steps S ₁₂₆ and S ₁₂₇
D [15] is incremented to [17] and [16], respectively. Further, in steps S ₁₂₈ and S ₁₂₉ , variable X and address data
Make sure that each ADD is within range and then step S
Return to ₁₀₅ .

Next, in step _S105 , the address data ADD [16] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [−1] written in the address [16] from the RAM 11 is written. Is output, and the write data K ₂ [−1] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is set to the “H” signal again in step S ₁₀₈ . Thereafter, the write data K ₂ [-1] is determined to be the solid burst error length in steps S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and FL is set in step S ₁₁₀ .
Set AG3 to 0. Next, in step S ₁₁₁ , the inspection data K ₁
(17) is set to [-1], and the variables X [17] and address data ADD [16] are incremented to [18] and [17] in steps _S126 and _S127 , respectively. Further steps S ₁₂₈ , S ₁₂₉
In variables X, make sure that the address data ADD is within the range respectively returns to step S _105.

Next, in step _S105 , the address data ADD [17] is output, and in step _S106 , the read control signal ▲ ▼ is used as the “L” signal, and the write data K ₂ [6] written in the address [17] from the RAM 11 is written. This is output, and the write data K ₂ [6] is input in the next step S ₁₀₇ , and the read control signal ▲ ▼ is turned to the “H” signal again in step S ₁₀₈ . After that step
The write data K ₂ [6] is determined to be the EF run length in S ₁₀₉ , S ₁₁₂ , and S ₁₁₈ , and it is further determined in step S ₁₁₉ whether FLAG3 is 1. Here FLAG3 previous inspection data K ₂ in [-1] 0
Since it is set to, the process directly proceeds to step S ₁₂₃ . The data K ₂ [6] written in step S ₁₂₃ is set to the EF run length ([3276
7] it is determined that the exception), sets the FLAG3 in step S ₁₂₅ to 1. Next, in step S ₁₁₁ , the inspection data K ₁ (18) is [6]
And the variable X [18] and the address data ADD [17] are incremented in steps S ₁₂₆ and S ₁₂₇ , respectively, [19], [1
8]. Returns to step S ₁₀₅ to confirm that the further step S _128, variable S ₁₂₉ X, the address data ADD is within the range, respectively.

Next, in step _S105 , the address data ADD [18] is output, and in step _S106 , the read control signal ▲ ▼ is set to the “L” signal, and the write data K ₂ [−32768] written in the address [18] from the RAM 11 is written. Is output, and the next step _S107
Input this write data K ₂ [−32768] with and press Step S
_{At 108} , the read control signal ▲ ▼ is set to the “H” signal again.
Next, in steps S ₁₀₉ and S ₁₁₂ , write data K ₂ [−3276
8] determines that a solid burst error length [1] reference position detection signal omission has been performed, test data K ₁ (19) in step S ₁₁₃ is set to [-1], the variable X at step S ₁₁₄
Increment [19] to [20]. Step S ₁₁₅
In sure that the variable X is in range, the write data K ₂ in step S ₁₁₆ [0], the FLAG3 in step S ₁₁₇ 0
Set to. Next, in step S ₁₁₁ , the inspection data K ₁ (20) is set to [0], and in steps S ₁₂₆ and S ₁₂₇ , the variable X [20],
The address data ADD [17] is incremented by [2
1] and [18]. The variable X is within the range in steps S ₁₂₈ and S ₁₂₉ , while the address data ADD is found in step S _129.
Is detected to be larger than Amax [18] (> 18), the program is ended, and the acquisition of the write data K ₂ is completed. As described above, the solid burst error length [1] omitted when writing to the RAM 11 is restored, and the original inspection data K ₁ is written to the RAM in the external computer.

Next, the computer 12 performs data processing according to a required recording medium evaluation program and displays the result on the printer 13 and the display 14.

FIGS. 5 and 6 show the actual measurement results, and the measurement data at that time are as follows.

Disc: Write-once type optical disc Recording laser power: 4.8 (mW) Reproducing laser power: 0.3 (mW) Linear velocity: 1.8 (m / s) Measuring time: 59 (sec) Total number of data: 4096 Total number of symbols: 14046359 Number of error symbols : 2896 Symbol error rate: 2.06D-04 Reference position detection signal: 591 FIG. 5 (a) shows the error distribution on the disk under the following conditions, where the horizontal axis is the number of symbols and the vertical axis is the number of tracks. .

1) Arrange the count value of the second block of the write data recorded at each address of the RAM 11 from left to right according to the address scale according to the scale of the horizontal axis.

2) When the value of the first block of the write data is [0], that is, when the second count value indicates the EF run length, black printing is performed for the corresponding length, and the value of the first block is [ 1]
In the case of, that is, when the count value of the second block indicates the burst error length, the corresponding length is left blank.

3) When the value of the second block of the write data is the reference position detection signal of [0], the process moves to the next track.

By displaying under the above conditions, scratches on the disc,
You can visually check the error part during recording and playback by dust or the like. Further, by comparing the number of symbols for each track (the position of the right end on the graph), the optical recording / reproducing apparatus 4
CLV control status is known.

FIG. 5 (b) shows the horizontal axis of FIG. 5 (a) as the rotation angle of the disk. According to this display method, the error position and its size can be accurately detected from the number of tracks and the angle. You can

6 (a) and 6 (b) show the EF run length distribution and the solid burst error length distribution, respectively, with the horizontal axis representing the number of symbols and the vertical axis representing the generating circuit. In addition, the solid line A in the figure,
B is a distribution obtained by calculation when errors occur randomly. In the example of FIG. 6, the solid line deviates greatly from this solid line, and it can be seen that many burst-like errors occur.

Next, based on an actual measurement example, Table 3 shows a comparison of the number of RAM write data recorded by the conventional recording method and this recording method.
Shown in.

The error rates ε of the media A, B, and C are 5.65, respectively.
^{× 10 -5, 2.06 × 10 -4} , a 2.43 × 10 ^-3.

As described above, according to this data recording method, the number of write data can be reduced by about 25% to 50%.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and various aspects are obtained.

For example, although the data recording method is realized by the software processing of the microcomputer 10 in the embodiment, it may be realized by a hardware configuration such as a logic circuit and a shift register.

Further, the external computer 14 restores the write data omitted when the write data is fetched. However, the write data should be fetched without performing this restore, and the recording medium evaluation program should include a program for performing this restore. You can also

As described above, according to the data recording / reproducing method of the present invention, at the time of data recording, when the error run length data following the EF run length data has the minimum value, the error run of the minimum value to the memory circuit is performed. Prohibiting the recording of long data, during data playback,
Since it is determined that the data read from the memory circuit has become EF run length data continuously and the error run length data of the minimum value that prohibits recording is restored, the efficiency of the memory circuit storage capacity is improved. It can be used well, resulting in cost reduction. Further, at the time of data reproduction, it is possible to easily restore the minimum value error run length data which is prohibited from being recorded in the memory circuit, so that the minimum value error run length data is not lost.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a recording medium inspection device using a data recording method according to the present invention, and FIGS. 2 and 3 are first diagrams.
4 is a flow chart for explaining the recording medium inspection apparatus shown in the figure, FIGS. 4 (a) to 4 (l) are timing charts showing one operation example, and FIGS. 5 and 6 are the recording medium shown in FIG. It is a figure which shows the example of a display of an inspection apparatus. 1 ... Recording controller, 2, 6 ... Data generator,
3 ... EFM modulator, 4 ... Optical recording / reproducing device, 5 ... E
FM demodulator, 7 ... Data comparator, 8 ... Reproduction system controller, 9 ... Run length counter, 10 ... Microcomputer, 11 ... RAM, 12 ... Delay circuit, 13 ... Inverter I
NV, 14 ... External computer, 15 ... Printer, 16 ...
Shows the display.

Claims (1)

[Claims] 1. A data recording / reproducing method for recording and reproducing, in a memory circuit, EF run length data indicating a length on which an error has not occurred on a recording medium and error run length data indicating a length on which the error has occurred. When the data is recorded, when the error run length data following the EF run length data has the minimum value, the recording of the minimum value of the error run length data in the memory circuit is prohibited to reproduce the data. In some cases, it is determined that the data read from the memory circuit has continuously become the EF run length data, and the error run length data of the minimum value that prohibits recording is restored. Data recording / playback method.