JPH0743927B2 - Dynamic RAM read method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM reading method.

2. Description of the Related Art A conventional dynamic RAM read method will be described with reference to a dynamic RAM read circuit shown in FIG. 3 and a flow chart of the dynamic RAM read method shown in FIG.

In Fig. 3, 1 is the first charging circuit line for selection, and 2 is the first
Line for discharge circuit to be selected, 3 is a sense amplifier circuit to be selected, 4 is an amplifier circuit, 5 and 6 are third switch elements to be selected, 7 is a second bit line pair, 8 is a first bit line pair to be selected, 9 is a non-selected second switch element, 10 is a selected second switch element, 11
Is a memory cell, 12 is a selection target word line, 13 is a non-selection word line, 14 is a selection target block, 15 is a non-selection target block, 16
Is a non-selected second switching element, 17, 18 is a first non-selected charging / discharging circuit line, 19, 20 is a non-selected third switching element, 21 is a selected first switching element, and 22 is a non-selected Selection target sense amplifier circuit, 23, 24 are selection target fourth switch element, 25,
Reference numeral 26 is a second charge / discharge circuit line to be selected, and 28 is a first bit line pair not to be selected.

In the conventional dynamic RAM read method, in the dynamic RAM read circuit configured as shown in FIG. 3, as shown in FIG. 4, first, one word line 12 to be selected is driven to be selected. The potential difference generated on the first bit line pair 8 is latched by the selection target sense amplifier circuit 3, the selection target first switch element 21 is turned off, and the selection target third switch elements 5 and 6 are turned on. When the target sense amplifier circuit 3 is activated and a sufficient potential difference between the selection target first bit line pair 8 is obtained, the selection target first switch element 21 is turned on and rewriting is performed, and at the same time, the selection target second switch element is performed. Turn ON 10 and select the first bit line pair 8
Is transmitted to the second bit line pair 7, and the potential difference generated in the second bit line pair 7 is transmitted to the selection target sense amplifier circuit 3.
When the fourth switch elements 23 and 24 to be selected are turned on, amplification is performed with the amplifier circuit 4 that is activated.

Problems to be Solved by the Invention However, in the above method, the dynamic RAM
Since the capacity and the integration are advanced, the charging and discharging currents of several thousand sense amplifier circuits 3 flow into the first and second charging and discharging circuit lines, respectively. , First
1st, 2nd charging / discharging circuit lines Disconnection problems due to electromigration, and large currents flowing only in the local areas of the chip, causing problems such as heat generation and circuit malfunctions, etc. Had a problem. Also, the third switch elements 5, 6, 19, 20 for driving such a large current are MOS
In a transistor, a gate width of about several mm is required,
There was a problem that it was difficult in terms of layout. Also, in the sense amplifier circuits 3 and 22, the bit line 8
The layout area is reduced due to the reduction of the pitch, etc., and it is extremely difficult to configure the sense amplifier circuits 3 and 22 using transistors having a large current driving capability gm.

As described above, the sense amplifier circuits 3 and 22 or the third switch elements 5 and 6, which form the drive circuit of the sense amplifier circuit 3,
While the current drive capacity gm of 19,20 and the drive capacity gm of the transistor element that constitutes the flip-flop are limited, the capacity of the first and second bit line pairs to be charged and discharged is highly integrated. Since it becomes larger as a result, the charging / discharging time becomes longer and longer, and there is a problem in reading speed.

The present invention has been completed as a result of various devisings in view of the above points.

Means for Solving the Problems The present invention provides a plurality of first bit line pairs, a second bit line pair provided corresponding to the plurality of first bit line pairs, and the plurality of first bit line pairs. In a dynamic RAM having a plurality of sense amplifier circuits provided corresponding to the first bit line pair, the potential difference generated in the first bit line pair by driving the selected word line is associated with the first bit line pair. The sense amplifier circuit provided detects the voltage and drives the charge / discharge circuit section of the sense amplifier circuit to activate the sense amplifier circuit, thereby initially amplifying the potential difference generated in the first bit line pair. After that, the output line pair of the sense amplifier circuit is connected to the second bit line pair, a potential difference is generated between the first bit line pair and the second bit line pair, and in that state, the second bit line pair is connected to the second bit line pair. Connected and The above-mentioned problems are solved by amplifying by the plurality of other sense amplifier circuits separated from the respective front air first bit line pairs.

Operation According to the present invention, a plurality of other sense amplifiers connected to the second bit line pair provided corresponding to the first bit line pair to be selected and separated from the respective first bit line pairs. Since the circuit is used to amplify the potential difference generated in the first bit line pair and the second bit line pair to be selected, one line for charge and discharge circuits for selection, which has been a problem in the conventional method, is provided. In addition, the charging and discharging currents are not concentrated, and the charging and discharging currents are distributed to the plurality of non-selected target charging and discharging circuit lines. Further, the current driving capability gm of one sense amplifier circuit to be selected cannot be sufficiently obtained due to the layout area problem.
In addition, the current drive capacity gm of one third switch element to be selected
However, due to the layout area, it is not possible to sufficiently obtain the problem that the amplification operation is performed by using a plurality of sense amplifier circuits via the second bit line pair, so that the entire charge / discharge current drive capability gm is increased. It will be.

Practical Example FIG. 1 is a diagram showing a flow of a dynamic RAM read method in the first embodiment of the present invention.

FIG. 2 shows the dynamics of the first embodiment of the present invention.
Word line 12, first bit line pair 8 when reading RAM,
FIG. 6 is a diagram showing a potential change of a second bit line pair 7.

FIG. 3 is a diagram showing a read circuit of the dynamic RAM, but since it has been explained when the conventional technique is explained, the detailed explanation is omitted here.

First, the read circuit of the dynamic RAM shown in FIG.
Dynamic RAM of this embodiment with reference to FIGS.
As shown in FIG. 1, first, all the word lines 12 and 13 are turned off and all the first lines are read.
The potentials of the bit line pair 8 and the second bit line pair 7 are kept at the precharge potential, all the first switch elements 21 and 9 are turned on, all the second switch elements 10 and 16 are turned off, and all the third switch elements are turned on. Turn off 5,6,17,18, turn off all 4th switch elements 23,24
After turning it off, first select one word line 1 to be selected.
2 is driven, the potential difference generated in the selection target first bit line pair 8 is latched by the selection target sense amplifier circuit 3, the selection target first switch element 21 is turned off, and the selection target third switch elements 5 and 6 are turned on. When turned on, the selection target sense amplifier circuit 3 is activated, and when the potential difference of the selection target first bit line pair 8 is sufficiently obtained, the selection target first switch element 21
Is turned on and rewriting is performed, and at the same time, the second switch element 10 to be selected is turned on, and the first switch element 9 not to be selected is turned off, so that the potential difference of the first bit line pair 8 to be selected is changed. , To the second bit line pair 7, and at the same time that the selection-target sense amplifier circuit 3 and the non-selection target second switch element 16 are turned on, the selection-unselected third switch elements 19 and 20 are turned on. A plurality of non-selection target sense amplifier circuits 22 activated by the above amplify the potential difference between the selection target first bit line pair 8 and the second bit line pair 7,
Further, it is amplified by the amplifier circuit 4 which is activated by turning on the fourth switch elements 23, 24 to be selected.

As described above, according to this embodiment, the potential difference between the selection target first bit line pair 8 and the selection target second bit line pair 7 is amplified by the selection target sense amplifier circuit 3 and the plurality of non-selection target sense amplifier circuits 22. Therefore, the charging and discharging currents do not concentrate on the selected charging and discharging circuit lines 1 and 2, respectively,
It is possible to reduce problems such as disconnection of charging / discharging circuit lines due to electromigration and reliability of elements due to heat generation. Further, even when the current drive capability gm of one sense amplifier circuit 3 to be selected cannot be sufficiently obtained due to the layout area, it is also used as a charge / discharge circuit driver. Even if the current drivability gm of one third switch element 5 or 6 to be selected cannot be sufficiently obtained due to the layout area, a plurality of sense amplifier circuits 3 and 16 are connected via the second bit line 7. Since they operate in parallel, it is possible to increase the entire charge / discharge current driving capability gm, and it is possible to shorten the sense amplifier amplification period and the rewrite period when reading the dynamic RAM. Further, the layout area of the circuit can be reduced.

Further, by turning off the non-selection target second switch element 16, the capacity of the second bit line pair 7 can be reduced. Therefore, initial amplification is performed only by the selection target sense amplifier circuit 3 and the potential difference When transmitting to the 2-bit line pair 7, it can be transmitted efficiently.

Further, by turning off the non-selection target first switch element 9, the capacity of the bit line amplified by the non-selection target sense amplifier circuit 22 can be reduced, so that the charge and discharge currents are reduced and the power consumption is reduced. Is possible.

Effects of the Invention As described above, according to the present invention, the following effects can be obtained.

(1) The charge / discharge current concentrated on one charge / discharge circuit line can be reduced, and the problem of line disconnection due to electromigration and the problem of element reliability due to heat generation can be reduced.

(2) In order to make the current driving capability gm of one sense amplifier circuit sufficiently large, the current of one third switch element used as a charge / discharge circuit drive unit does not have to be large in layout area. Even if the layout area is not made large in order to make the driving capacity gm sufficiently large, the multiple charging / discharging current driving capacity gm can be increased because the above circuits operate in parallel. Can be reduced.

(3) Since the charging / discharging current driving capability gm of the whole can be increased, the sense amplifier amplification period and the rewriting period can be shortened when reading the dynamic RAM.

[Brief description of drawings]

FIG. 1 shows a dynamic RA in the first embodiment of the present invention.
FIG. 2 is an explanatory diagram showing the flow of the M reading method, and FIG. 2 shows potential changes of the lead line, the first bit line pair, and the second bit line pair at the time of reading of the dynamic RAM in the first embodiment of the present invention. Fig. 3 shows dynamic RAM
FIG. 4 is a circuit diagram showing the read circuit of FIG. 4, FIG. 4 is an explanatory view showing the flow of a conventional dynamic RAM read method, and FIG. 5 is a word line, a first bit line pair, FIG. 9 is a characteristic diagram showing a potential change of a 2-bit line pair. 3 ... selection target sense amplifier circuit, 7 ... second bit line pair, 8 ... selection first bit line pair, 10 ... selection second switch element, 12 ... selection word line, 21 ... First switch element to be selected.

Claims (3)

[Claims] 1. A plurality of first bit line pairs and the plurality of first bit line pairs.
Driving a selected word line in a dynamic RAM having a second bit line pair provided corresponding to a bit line pair and a plurality of sense amplifier circuits provided respectively corresponding to the plurality of first bit line pairs By doing so, the potential difference generated in the first bit line pair is detected by the sense amplifier circuit provided corresponding to the first bit line pair, and the charge / discharge circuit unit included in the sense amplifier circuit is driven. By
The sense amplifier circuit is activated, the potential difference generated in the first bit line pair is initially amplified, and then the output line pair of the sense amplifier circuit is connected to the second bit line pair, and the first bit line pair, A potential difference is generated in the second bit line pair, and in that state, it is connected to the second bit line pair and is amplified by the other plurality of sense amplifier circuits which are separated from the respective front air first bit line pairs. Dynamic RAM read method. 2. A pair of output lines of a plurality of sense amplifier circuits and a first line
Connection with the second bit line pair provided corresponding to the bit line pair is performed through a plurality of second switch elements controlled by a control circuit, and the potential difference between the first and second bit line pairs is
2. The method for reading a dynamic RAM according to claim 1, wherein the control circuit controls the opening / closing of the second switch element so that the selected number of the sense amplifier circuits amplifies. 3. A sense amplifier circuit provided corresponding to a first bit line pair and said first bit line pair are connected via a first switch element controlled by a control circuit, and said control circuit 2. The method of reading a dynamic RAM according to claim 1, wherein opening / closing of the first switch element is controlled so that the sense amplifier circuit amplifies a potential difference between the first and second bit line pairs.