JPH0743934B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a circuit that stabilizes the operation when the charge / discharge time of a data line is long. .

[Background of the Invention]

In a semiconductor device, the wiring width is becoming finer with the increase in capacity, so that signal delay due to wiring resistance is becoming a problem. That is, this delay appears as a malfunction due to a mismatch in operating speed between the memory array and peripheral circuits. This will be described with reference to FIG.

FIG. 1 is a circuit diagram of a main part of a conventional dynamic memory composed of n-channel MOS. In the memory shown in FIG. 1, the read operation is performed as follows. First, the precharge signal Φ _{P is set} to a high level, the precharge circuit PRC precharges the data line D or the common source line CS of the differential amplifier circuit SA to a high level, and the node in the dummy cell DM that generates the reference signal is grounded. Set to potential. After that, after setting Φ _P to a low level, a word line, for example W, is generated by the X decoder signals XD ₁ and XD _2.
2 is selected, and a signal is output on the data line D from each memory cell MC connected thereto. X decoder signal at the same time
A reference signal is output on the data line from each dummy cell DM connected to the dummy word line DW ₂ selected by XD ₁ ′, XD ₂ ′ and the like. After that, the pulse Φ _{s is set} to a high level and the common source line CS of the SA is discharged to the ground potential, thereby operating the SA and amplifying the signal output to the data pair line D. Then, the pulse Φ _s is delayed by the delay circuit DLYC.
By the pulse Φ _r delayed by a certain time by ₁ , the data line high potential compensation circuit AR is operated, and the data line on the high potential side (either D or D depending on the information of the memory cell) reaches the rewrite level. Boost. The amplified signal is output to the switch SW selected by the Y decoders YD ₁ and YD _m.
By applying a pulse [Phi _y, the input and output lines I / O, ▲
It is output to ▼ and taken out to the outside as data output through various circuits. The write operation also depends on the data input information applied from the outside, I / O line I / O, ▲
It is applied to ▼ and is written in a predetermined memory cell MC through the selected switch SW. Here, the delay circuit DLYC ₂ is used so that the pulse Φ _y rises after a certain time from the pulse Φ _s.
Generated by the pulse Φ _sd output from The first
In the figure, Φ _c is a pulse that changes from low level to high level after the end of the memory operation, and the word line clear circuit WC discharges the selected word line and dummy word line to the ground potential.

The following problems occur in the memory shown in FIG. That is, in the SA close to the MOS transistor Q ₀ that discharges the common source line CS to the ground potential, the source side of SA immediately becomes a low potential, so that the signal amplification of the data pair line D ₁ , ▲ ▼, that is, the discharge of the data line is prompt. To be done. On the other hand, in SA far from Q ₀ , the wiring resistance of CS causes a delay in the time when the source side of SA becomes low potential, which delays signal amplification, that is, discharge of the data line. Therefore, when the timing setting of Φ _r and Φ _y is not appropriate, the operation of the high-potential compensating circuit AR and the connection with the input / output line are performed before the signal is sufficiently amplified, so that the stored information is destroyed or erroneously read. Cause. On the other hand, in the prior art, in consideration of the characteristic variation due to the manufacturing variation, the operation of the AR and the connection with the input / output line are designed to be sufficiently delayed by the delay circuit. However, this slows down the operation speed and makes it impossible to speed up the operation.

[Object of the Invention]

An object of the present invention is to provide a semiconductor device capable of improving such conventional problems, preventing destruction and erroneous reading of stored information caused by delay due to resistance of a common source line, and capable of high-speed operation. is there.

[Outline of Invention]

The present invention for achieving the above object is characterized in that an actual pulse response of a data line or a wiring equivalent thereto is detected to perform the next operation. More specifically, the discharge of the data line is detected, and the detection output thereof is used to operate the data line high potential compensation circuit and connect to the input / output line.

Example of Invention

 The present invention will be specifically described below with reference to examples.

FIG. 2 is a circuit diagram of essential parts of a semiconductor device showing an embodiment of the present invention. The memory array portion CA shown by the dotted line is the same as that in FIG.

As shown in FIG. 2, in this embodiment, a new data line
D _d , ▲ ▼ is provided on the side far from the MOS transistor Q ₀ , and the circuit 1 for detecting that one of the data lines has become almost OV is provided on this data pair line, and the output pulse thereof is set to the high potential of the data line. It is used as an input of an AND circuit (AND ₀ ) for generating drive pulses Φ _r and Φ _{y of the} compensation circuit AR. This newly provided data pair line D _d , ▲ ▼ is the same as the data pair line in the memory array CA, and the data line capacitance discharged by SA is made equal to other data pair lines. Since this data pair line does not need to be connected to the input / output line I / O, ▲ ▼, the gate of the switch SW _d is connected to the ground potential. Further, the reason why the data pair line Dd, ▲ ▼ is provided on the side far from Q ₀ is that the discharge of the data line at this position is most delayed. Further, in the detection circuit 1, for example, as shown in FIG. 2, when the potential of the data line becomes lower than the reference level Vref ₁ (for example, a level slightly higher than the ground potential), the output becomes low level circuit DA ₁ ( For example, it can be composed of a differential amplifier circuit), a NAND circuit (NAND ₁ ) that receives the outputs of these two circuits, and A of the NAND output and the pulse Φ _s.
It can be configured with an AND circuit (AND ₁ ) that obtains the ND output. Alternatively, depending on the design, the circuit DA ₁ may be omitted and D _d , ▲
It is also possible to use ▼ directly as the input of the NAND circuit. That is, it is used as Vref of the threshold voltage (discrimination level of “0” or “1”) of the circuit itself. This also applies to each of the following embodiments. According to this embodiment,
The operation of the AR and the connection of the input / output line are not performed before the signal is sufficiently amplified by SA, and the stored information is not destroyed or erroneously read. In addition, since it does not unnecessarily delay the operation of the AR and the connection with the input / output line, high-speed memory operation becomes possible.

FIG. 3 is a main part circuit diagram of a semiconductor device showing another embodiment of the present invention. This embodiment is the same as the embodiment shown in FIG.
A circuit 2 is added which detects that any one of D _d and ▲ ▼ has reached the rewrite level by AR, and generates a signal for operating the word clear circuit WC by AND logic of the detection output and the pulse Φ _c. It was done. This allows
In the present embodiment, in addition to the effect shown in FIG. 2, the discharge of the word line is not started before the rewriting level is sufficiently transmitted to the memory cell, and sufficient accumulated charge is always stored in the memory cell. You can In the detection circuit 2, for example, as shown in the same figure, the potential of the data line is the reference level Vre.
f ₂ ) For example, _two circuits DA ₂ (which can be composed of, for example, a differential amplifier circuit like DA ₁ ) whose output becomes high when the voltage becomes higher than the rewriting level). OR circuit (OR ₂ ) that receives the output of DA ₂ of
It can be configured by an AND circuit (AND ₂ ) which receives the OR output and the pulse Φ _c as inputs.

In the embodiment shown in FIGS. 2 and 3, a new data pair line D _d , ▲ ▼ is provided to prevent an extra load from being connected to the data pair line in the CA and to detect the detection circuit. The layout of the connection with 1 or 2 is designed so that it can be done easily, but the data pair line in CA (however, the data line pair farthest from Q ₀ , D _n , ▲ ▼ in Fig. 1) The detection circuit 1 may be connected, or the detection circuit 2 may be connected to another data pair line, for example, the data pair line (D ₁ , ▲ ▼ in FIG. ₁ ) farthest from the side to which the drive pulse Φ _{r of} AR is applied. You may connect. As a result, the increase in area can be made as small as possible in comparison with the prior art (FIG. 1), and the effects described in FIGS.

FIG. 4 is a main part circuit diagram of a semiconductor device showing another embodiment of the present invention. In FIG. 4, the data line D _d after amplification by SA
The data line D _d is switched through the switch SW _d by the Y decode signal YD which becomes high level regardless of which data pair line in CA is selected so that ▲ is always high potential and ▲ ▼ is low potential. At high level, ▲ ▼ is connected to the ground potential, and these potentials are respectively written in the memory cells connected to the data lines D _d , ▲ ▼.
A circuit 3 for detecting that the level of the data line is almost OV is provided only on the data line ▲ ▼ side, and its output pulse is an AND circuit (A for generating AR drive pulses Φ _r and Φ _y).
ND ₀ ) is input. In this embodiment, the data line ▲
Since ▼ always has a low potential, the circuit for detecting the potential of the data line is simpler than that of the embodiment shown in FIG. For example, as shown in FIG. 4, the detection circuit 3 includes a circuit DA ₁₁ for inputting the data line D _d and a complementary (completion) pulse (Φ _s )
mentary) pulse ▲ ▼ and a NOR circuit (NOR ₃ ) which receives the output of the circuit DA ₁ as an input. Depending on the design, this DA ₁ can be omitted and ▲ ▼ can be directly used as the input of the NOR circuit. Further, the NOR circuit may be constructed by the circuit described in FIG. 9 or FIG. 11 of Japanese Patent Application No. 58-55012.

FIG. 5 is a main part circuit diagram of a semiconductor device showing still another embodiment of the present invention. In the embodiment shown in FIGS. 2 and 4, the data line is newly provided and the potential of the data line is detected. However, in FIG. 5, instead, it is almost on the low potential side of the data line. The detection circuit 3 is provided at the far end (viewed from the MOS transistor Q ₀ ) of the common source line CS at the same potential, and it detects that the potential becomes almost OV, and operates the AR and connects with the input / output line. Is to do. According to this embodiment, it is possible to obtain the same effect as that of the embodiment shown in FIG. 2 or 4 without newly providing a data pair line.

FIG. 6 is a circuit diagram of a main part of a semiconductor device showing still another embodiment of the present invention. The embodiment shown in FIGS. 2 to 5 shows an example of the dynamic memory constituted only by the n-channel MOS, but in FIG. 6, the present invention is applied to the dynamic memory using the CMOS. Here is an example: In the figure, the differential amplifier circuit SAC for increasing the signal read to the data line and the circuit SC for shorting the data line are shown in CA up to FIG.
Is a different part of. The MOS transistor indicated by an arrow in the figure is a p-channel MOS. Also, as shown in FIG. 4, a data pair line D _d , ▲ ▼ is newly added to CA, and D _d is set to a high level through the switch SW _d.
Is connected to ground potential. Furthermore, in D _d , ▲ ▼, D _d was almost at the rewrite level and ▲
A circuit 4 is provided to detect that ▼ has almost reached OV,
The output pulse is used as the input of the AND circuit (AND ₀ ) for generating Φ _y . In the figure, the read operation is performed as follows. First, the precharge signal Φ _{P is set} to the high level, and the data line D, is set to the intermediate level by the short circuit SC.
Initialize to 1 / 2V _C. Then, after making Φ _P low, a pulse is applied to the selected word line by the X driver XDR, and a signal is output to the data line from each memory cell connected thereto. At the same time, the dummy word line is selected,
A reference signal is output from each dummy cell connected thereto to the other data line. After that, the pulse Φ _{s is set} to the high level, the pulse ▲ ▼ is set to the low level, and the differential amplifier SA
Operate C, the high potential side of the data line to high level V _C ,
Charge and discharge the low potential side to the ground potential. The newly added data line pair D _d, ▲ ▼ even, D _d
Is charged to a high level V _C , ▲ ▼ is charged and discharged to the ground potential,
When the detection circuit 4 detects that the battery has been sufficiently charged and discharged, an output pulse is generated from the detection circuit 4 and the data line and
Connection with I / O line is made.

In this way, also in this embodiment, as in the embodiments described so far, erroneous reading at the time of connection with the input / output line caused by the delay due to the resistance of the common source line CS or the common drain line CD is prevented. You can do it. As shown in the figure, the data line D _d , ▲ ▼ is the MOS that drives the SAC.
It is necessary to arrange it on the side far from the transistors Q ₀ and Q ₁ .

The detection circuit 4 is, for example, as shown in FIG.
Circuit with ▼ and reference level Vref ₁ as input DA ₁ and data line D
_{A circuit that receives d} and the reference level Vref ₂ as input, and the output becomes low level when the potential of D _d becomes higher than Vref _2.
(The output is almost complementary to the circuit DA ₂ shown in FIG. 3,
When configured with a differential amplifier circuit, DA ₂ and ▲ ▼ can have the same circuit configuration only with different output terminals), and a NOR circuit (NO with these outputs and pulse Φ _s as input).
R ₄ ) and can be composed of. According to the design,
DA ₁ can be omitted and ▲ ▼ can be directly used as the input of the NOR circuit.

FIG. 7 is a circuit diagram of essential parts of a semiconductor device showing still another embodiment of the present invention. In the embodiment shown in FIG. 6, the MOS transistors Q ₀ and Q ₁ are operated almost at the same time, but in the embodiment shown in FIG. 7, Q ₀ is operated first so that the low potential side of the data line is sufficiently discharged. It is detected by the detection circuit 5 that the output pulse Φ _ss causes Q ₁ to operate, and the high potential side of the data line is charged to the rewrite level. Then, the detection circuit 6 detects that the data line has been sufficiently charged to the rewrite level (that is, the potential difference between the data lines D _d and ▲ ▼ has been sufficiently amplified), and its output is Φ _y. It is used as the input of the generation AND circuit (AND ₀ ). According to this embodiment, since there is no possible n-channel and p-channel MOS transistor in the SAC gates are common and summer is simultaneously turned ON when the signal amplification, between a power supply potential V _C and ground potential flowing through both transistors The through current can be prevented. Further, since the connection with the input / output line is performed after the amplification is sufficiently performed, erroneous reading can be prevented. As shown in the figure, for example, the detection circuit 5 has a circuit DA ₁ that inputs the data line D _d and the reference level V ref ₁ that are always on the low potential side and an output of the pulse ▲ ▼ and DA ₁ as inputs, and both inputs. It can be configured with an OR circuit (OR ₅ ) whose output becomes low level when is low level. In addition, the detection circuit 6
Is always on the high potential side and the data line ▲ ▼ and reference level
A circuit DA ₂ having Vref ₂ as an input and a complementary pulse ▲ ▼ of the output pulse Φ _ss of the detection circuit 5 and an AND circuit (AND ₆ ) having an output of DA ₂ as an input can be used. Also in this figure, in some cases, DA ₁ may be omitted and D _d may be directly used as the input of the OR circuit.

Although some embodiments of the present invention have been described above, it goes without saying that the scope of application of the present invention is not limited to the embodiments described here, and various modifications can be made without departing from the spirit of the invention. For example, here the memory cell (folded bitline arrangement
nt or a folded type memory cell) is shown as an example, but a memory using a cell (open bitline arrangement or open type memory cell) in which the data pair line D is spatially separated is also shown. The present invention can be similarly applied. Further, in the embodiment shown in FIGS. 6 and 7, a memory array configuration in which the dummy cells DM are omitted can be used.

〔The invention's effect〕

As described above, according to the present invention, since the operation of the data line high potential compensation circuit or the connection with the input / output line is performed after the amplification state of the data line is detected, the common source of the differential amplification circuit is used. Even if the delay time of the line is large, it is possible to prevent the destruction and erroneous reading of the stored information and to operate at high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a conventional dynamic memory, and FIG.
FIG. 1 is a circuit diagram of a main part of a semiconductor device showing an embodiment of the present invention,
FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7 and FIG. 7 are main circuit diagrams of a semiconductor device showing another embodiment of the present invention. 1,2,3,4,5,6 …… Detection circuit, SA, SAC …… Read signal amplification circuit, AR …… Data line high potential compensation circuit, PRC …… Precharge circuit, DM …… Dummy cell, MC …… Memory cells,
CA: Memory main part, MA: Memory cell array, WC ...
Word clear circuit, XDR ... X driver circuit, IOG ... input / output selection circuit, SC ... short circuit, DA ... differential amplification circuit, CS ... common source line, CD ... common drain line.

Continuation of front page (56) Reference JP-A-57-195387 (JP, A) JP-A-52-84929 (JP, A) JP-A-53-60125 (JP, A) JP-A-57-195387 (JP , A) JP-A-59-87694 (JP, A) JP-A-59-92492 (JP, A) Actually developed 57-152698 (JP, U)

Claims (8)

[Claims] 1. A data line group, a word line group, a memory cell group arranged at a desired intersection of the data line group and the word line group, and a voltage of each data line of the data line group. Detecting and amplifying circuit group for detecting and amplifying, common source line for driving the detecting and amplifying circuit group, driving means for applying a drive signal to the common source line, and each data line of the data line group And a high potential compensating means for charging each of the data lines to a predetermined voltage, further comprising: a far end portion of the common source line with respect to the driving means in the data line group. A semiconductor device comprising: a detection circuit which is connected to a provided data line and detects a voltage of the data line; and a unit which operates the high potential compensating unit based on an output of the detection circuit. 2. The semiconductor device according to claim 1, wherein the output of the detection circuit is connected to a circuit for charging and discharging the word line group. 3. The semiconductor device according to claim 1, wherein the data line to which the detection circuit is connected is connected to a power supply via a switch, and the switch is controlled by the output of the detection circuit. A semiconductor device characterized by the following. 4. A data line group, a word line group, a memory cell group arranged at a desired intersection of the data line group and the word line group, and a voltage of each data line of the data line group. Detecting and amplifying circuit group for detecting and amplifying, common source line for driving the detecting and amplifying circuit group, driving means for applying a drive signal to the common source line, and common data common to the data line group A line and a connection control means that is provided for each data line of the data line group and that controls the connection between each of the data lines and the common data line. A detection circuit connected to a data line provided at the far end of the common source line with respect to the driving unit, and detecting the voltage of the data line, and operating the connection control unit based on the output of the detection circuit. Hand Wherein a has and. 5. The semiconductor device according to claim 4, wherein the output of the detection circuit is connected to a circuit for charging and discharging the word line group. 6. The semiconductor device according to claim 4, wherein the data line to which the detection circuit is connected is connected to a power supply via a switch, and the switch is controlled by the output of the detection circuit. A semiconductor device characterized by the following. 7. A data line group, a word line group, a memory cell group arranged at a desired intersection of the data line group and the word line group, and a voltage of each data line of the data line group. Detecting and increasing sense amplifier circuit group, common source line for driving the sense amplifier circuit group, driving means for applying a drive signal to the common source line, and common data common to the data line group A semiconductor device having a line and a connection control unit that is provided for each data line of the data line group and that controls the connection between each of the data lines and the common data line, further comprising: A semiconductor having a detection circuit connected to the far end of the common source line to detect the voltage at the far end, and a means for operating the connection control means based on the output of the detection circuit. apparatus. 8. The semiconductor device according to claim 7, wherein the output of the detection circuit is connected to a circuit for charging and discharging the word line group.