JPH0743937B2 - Multi-directional read one-way write memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device capable of selecting an address from one direction and writing data in the one direction, and reading data in response to address selection from a plurality of directions.

[0002]

2. Description of the Related Art A conventionally proposed unidirectional access static memory cell is shown in FIG. As shown in FIG. 8A, the memory cell 1 has two input / output terminals 2 and 3.
Information holding means by the static flip-flop 4 having, transistors 5, 6 composed of, for example, n-channel MIS type field effect transistors, word line 7,
It has bit lines 8 and 9. In this case, the word line 7 is a signal line for selecting the memory cell 1, and the bit lines 8 and 9 are signal lines for transferring write data to the memory cell 1 or read data from the memory cell 1. The static flip-flop 4 has four transistors 10 to 13
For example, the transistors 10 and 11 are n-channel MIS type field effect transistors, and the transistor 1 is
Reference numerals 2 and 13 are p-channel MIS field effect transistors. Transistors 10 and 11 have one ends connected to input / output terminals 2 and 3, respectively, and the other ends commonly grounded.
The transistors 12 and 13 have one ends connected to the input / output terminals 2 and 3, respectively, and the other ends commonly connected to the power supply terminal 14. The gates of the transistors 10 and 12 are commonly connected to the input / output terminal 3. The gates of the transistors 11 and 13 are commonly connected to the input / output terminal 2. The input / output terminal 2 of the static flip-flop 4 is a transistor 5
To the bit line 8, and the input / output terminal 3 of the static flip-flop 4 is connected to the bit line 9 via the transistor 6. On the other hand, the gates of the transistors 5 and 6 are commonly connected to the word line 7. The above is the configuration of the unidirectional access memory cell 1 that has been conventionally proposed.

The operation of the unidirectional access memory cell 1 will be described below. [Data Writing] In order to write data in the conventional memory cell 1 having such a configuration, a potential having the same phase as that of the data to be written is applied to the bit line 8 and a potential opposite to that of the data to be written is applied to the bit line 9. In addition, the word line 7 is set to a high potential. Since the word line 7 has a high potential, the transistors 5 and 6 are turned on and become conductive, so that the potential of the bit line 8 is equal to the potential of the input / output terminal 2 and the potential of the bit line 9 is equal to the potential of the input / output terminal 3. Moreover, the potential of the input / output terminal 2 and the potential of the input / output terminal 3 have different polarities. Therefore, the on / off state of the transistors 10 to 13 of the static flip-flop 4 is determined,
Data is written to the unidirectional access memory cell 1.

[Data Retention] In order to retain this data, the word line 7 is set to a low potential and the transistors 5 and 6 are turned off, so that the data is held between the input / output terminal 2 and the bit line 8 and between the input / output terminals. 3 and the bit line 9 may be made non-conductive to disconnect the flip-flop 4 from the bit lines 8 and 9.

[Reading of Data] In order to read data, the bit lines 8 and 9 are precharged to an equal potential to a high potential, and then the word line 7 is set to a high potential and written to the static flip-flop 4. The bit line 8 is informed of the current state. Here, the logical value "1" corresponds to a high potential and the logical value "0" corresponds to a low potential. When the logical value “1” is written in the input / output terminal 2 of the static flip-flop 4, since the input / output terminal 2 has a high potential, the potential of the high-potential bit line 8 does not change. The logical value "1" is read. On the other hand, when the logical value “0” is written in the input / output terminal 2 of the static flip-flop 4, the input / output terminal 2 has a low electric potential, and therefore the electric potential of the bit line 8 having a high electric potential is lowered. Thus, the logical value "0" is read. On the other hand, the state written in the input / output terminal 3 can be similarly read out from the bit line 9. Also, the written state can be read by detecting the potential difference between the bit lines 8 and 9. When the memory device is configured by the above memory cells, the unidirectional access memory device 15 is configured by arranging m × n memory cells 1 in m rows and n columns as shown in FIG. 8B. . I-th (i = 1, 2, ..., M)
Select the address WXi corresponding to the word line 7 of
1, BY2, ..., BYn through bit lines 8 or BY1 ', BY2', ..., BYn '.
, Cin, which are the memory cells 1, are read and written via the memory cells.

[0006]

In the fields of image recognition, character recognition, etc., complicated processing or addition of a large amount of hardware is required. For example, in character recognition, as shown in FIG. 9A, one piece of character data 16 is set in the X-axis direction (horizontal direction), diagonally upper right direction, diagonally upper left direction, Y.
It is necessary to scan in four directions in the axial direction (vertical direction), which requires complicated processing or addition of a large amount of hardware. In the memory device shown in FIG. 8, m = 7, n
FIG. 9B shows a case in which the character “F” is written in the pattern memory device with = 5. In this case, a unidirectional access memory device 17 of 7 words × 5 bits is used.
Addresses WX1 to WX7 and bit line BY in FIG. 9B
1 to BY5 have the same meaning as in FIG. In the above device, when scanning data in the X-axis direction,
Since the selected direction coincides with the direction of the word line of the memory device 17, the data for one word in the X-axis direction can be read by one address selection. Further, in the case of scanning the data in the diagonally upper right direction, for example, in order to read the 5-bit data on the R line in FIG. Bit BY on line BY3 and address WX4
Each data of the bit line BY5 is sequentially read at Y4 and address WX3. Therefore, in this case, it is necessary to select five times, which is the number of bits, for scanning once in the diagonally upper right direction. Further, in the case of scanning the data in the diagonally upper left direction, for example, to read 5-bit data on the L line in FIG. The data of the bit line BY2 is sequentially read from the line BY3 and the address WX4, and the data of the bit line BY1 is sequentially read from the address WX3. Therefore, in this case, it is necessary to select five times, which is the number of bits, for scanning once in the diagonally upper left direction. Further, when scanning data in the Y-axis direction, addresses WX1 to WX7 are sequentially read out for a specific bit line to be scanned. Therefore, it takes 7 scans to scan once in the Y direction.
It is necessary to select once. From the above, generally m rows n
In a column unidirectional access memory device, worst case m selections are required to scan once in a direction different from the word line.

FIG. 10 shows an example in which a dedicated pattern memory device is provided for each scanning direction in order to reduce the increase in scanning time seen in the example of FIG. 7 line 5 shown in FIG.
The column memory device 18 is a memory device for the X-axis direction.
The memory device 19 of 11 rows and 5 columns shown in FIG. 10B is a memory device for the diagonally upper right direction. 1 shown in FIG.
The memory device 20 of 1 row and 5 columns is a memory device for the diagonal upper left direction. 5 × 7 memory device 2 shown in FIG.
Reference numeral 1 is a memory device for the Y-axis direction. Here, the scanning of data in each direction can be performed by one-time address selection reading to each memory device. For that purpose, character data is rearranged in advance according to the scanning direction as shown in FIG. The operation to write in the memory device is added,
In addition, a memory device of 4 times or more is required. Note that FIG.
The X mark in the middle indicates an unused memory cell.

As described above, when the conventional unidirectional access memory device is used to scan data in a direction different from the direction of the word line peculiar to the memory device, the number of times the memory device is selected is scanned. The number of bits required is equal to the number of bits, and the access time to the memory device becomes huge. In addition, in order not to increase the number of selections to the memory device, a memory device for rearranging and storing data in advance for each scanning direction is required, which not only increases the amount of additional hardware but also increases the amount of additional memory. There is a drawback that a complicated operation of rearranging and writing the data in the scanning direction corresponding to each of the devices is also necessary so that the data can be read out by one-time selection to the memory device.

An object of the present invention is to realize a memory device capable of reading data from a plurality of directions in order to solve these drawbacks.

[0010]

In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the present invention, a conventional unidirectional access memory cell is provided with one third transistor and K other transistors (K ≧ 0, an integer), and a memory device is provided. , K-direction word lines and M-direction (K ≧ M ≧ 0, integer) bit lines are added, and the gate of the third transistor is the L-th bit line (L = connect to 1 or 2), the
One end of the other gate of the third transistor is connected to the L-th input and output terminals of the static flip-flop, a third
The other end other than the gate of the transistor is connected to one word line, and the Nth transistor (K ≧
(N ≧ 0, integer) and the Nth word line of the K direction word line are connected to each other, and one end other than the gates of the K transistors is connected to two input / output terminals of the static flip-flop. connect the other hand, the one bit line also of the N-th other end other than the gate of the transistor is the gate of the transistor is not connected two bit lines and the M direction of the bit lines of the K of the transistor
Has a configuration connected to the one word line . In addition,
The minimum unit of the memory cell of the above invention, that is, K = M = 0
The circuit of is a circuit shown in FIG. 1 described later. Further, the one third transistor corresponds to, for example, the transistor 51 in FIG. 1 or FIG. 5 described later, and the word line in the K direction is
For example, it corresponds to the word lines 63 and 64 in FIG. 5 described later.

[0011]

With the above-described structure, in the present invention, address selection can be performed by K + 1 word lines or one bit line to which the gate of the transistor is connected,
Data can be read from a word line that also has the function of a bit line or a bit line in the M direction. Therefore, if a plurality of these memory cells are arranged in an array, K + 2
It is possible to realize a memory device which can select the address of the memory cell array in the direction M and read data from the direction M + 2. or,
It is also possible to select addresses in the M + 1 direction and simultaneously read from the bit lines in the M + 1 direction.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before explaining the embodiments, the circuit which is the basis of the present invention will be explained. FIG. 2 is a circuit diagram of a memory cell which is the basis of the present invention. The memory cell 30 includes an information holding unit including a static flip-flop 4 having two input / output terminals 2 and 3, and three transistors 5, 6, and 3 formed of, for example, an n-channel MIS type field effect transistor.
1 and 2 word lines 7 and 32 and 3 bit lines 8 and
9 and 33. Static flip-flop 4
Has two input / output terminals 2 and 3, and has an internal circuit configuration similar to that of FIG. The gates of the first transistor 5 and the second transistor 6 are commonly connected to the first word line 7. The gate of the third transistor 31 is connected to the second word line 32. The first input / output terminal 2 of the static flip-flop 4 is connected to the first bit line 8 via the first transistor 5. The first input / output terminal 2 is also connected to the third bit line 33 via the third transistor 31.
On the other hand, the second input / output terminal 3 of the static flip-flop 4 is connected to the second bit line 9 via the second transistor 6. The above is the configuration of the memory cell 30. The operation of the memory cell 30 will be described below.

[Data Writing] In the memory cell 30 having such a configuration, a potential having the same phase as the data to be written is applied to the first bit line 8 and a potential having a phase opposite to the write data is applied to the second bit line 9. To bring the first word line 7 to a high potential. In this way, the first word line 7
The first transistor 5 and the second transistor 6 controlled by the ON state are turned on and become conductive. Therefore, the potential of the first bit line 8 and the potential of the first input / output terminal 2 become the same potential. Further, the potential of the second bit line 9 and the potential of the second input / output terminal 3 become the same potential. In this way, the in-phase and anti-phase potentials are applied to the data to be written to the two input / output terminals 2 and 3 of the static flip-flop 4, so that the on / off state of the static flip-flop 4 is changed accordingly. You can make transitions and write data.

[Data Retention] In order to retain this data, both the word lines 7 and 32 are set to a low potential, and the two input / output terminals 2 and 3 are both set to a high impedance state. The state of 4 is maintained.

[Reading of Data] Lateral Access After the first bit line 8 and the second bit line 9 are precharged to the same potential and set to the high potential, the first word line 7 is set to the high potential. Data can be read by transmitting the state held in the static flip-flop 4 to the first bit line 8 and the second bit line 9 and detecting the potential difference between these bit lines 8 and 9. Similarly, after the bit lines 8 and 9 are precharged to the same potential and set to the high potential, the first word line 7 is set to the high potential and the potential of the first input / output terminal 2 is transmitted to the first bit line. Data can also be read by detecting the potential change of 8.
Similarly, after the bit lines 8 and 9 are precharged to the same potential and set to the high potential, the first word line 7 is set to the high potential and the second
The data can also be read by detecting the potential change of the second bit line 9 through which the potential of the input / output terminal 3 of FIG.

Vertical Access To access data in the vertical direction and read data, the third bit line 33 is precharged to a high potential, and then the second bit line 33 is read.
The potential of the third bit line 33 is detected and the data is read.

Orthogonal Simultaneous Access A read operation by a combination of the first word line 7 and the first bit line 8 or the second bit line 9 and the second word line 32 and the third bit line 33. The read operation by combination can be performed at the same time. For example, after pre-charging the bit lines 8, 9, 33 to a high potential to make them equipotential, the first word line 7 is laterally accessed to access from the first bit line 8 and the second bit line 9. Read the data. At the same time, the second word line 32 is used for vertical access to read data from the third bit line 33. In this way, it is possible to access from two directions at the same time. As described above, it is possible to configure a two-way access static memory cell that can equally read data from two directions.

FIG. 3 shows the memory cell 30 shown in FIG.
Signal lines 7, 8, 9, 3 are arranged in (m × n) rows and n columns.
Reference numerals 2 and 33 denote two-way access static memory devices 3 which are wired in common with adjacent vertical and horizontal memory cells.
It is a conceptual diagram of 4. Since address circuits, signal line drive circuits and the like necessary for constructing the two-way access static memory device 34 can use the same circuits as those used in the conventional static memory device, they are all omitted in FIG. I am doing it. In FIG. 3, the first word line 7 is selected when it is accessed in the horizontal direction, is given addresses WX1, WX2, ..., WXm, respectively, and the first bit line 8 is bit lines BY1, BY2 ,. The second bit lines 9 are bit lines BY1 ', BY2', ...,
Data is read and written via BYn '. Also, the second word line 32 is selected when accessing in the vertical direction and given the addresses WY1, WY2, ..., WYn, respectively, and the third bit line 33 is connected to the bit lines BX1, BX2.
,, Read out via BXm.

The operation of the memory device 34 will be described below. [Data Writing] Memory Cell Cij (i = 1, 2,
,, m j = 1, 2, ..., N), when writing data to the first word line 7 of the address WXi,
The word lines 7 and 32 of other addresses are set to a low potential, and the potential in the same phase as the data to be written is set to BYj of the first bit line 8.
And a potential having a phase opposite to that of the data to be written is applied to BYj 'of the second bit line 9.

[Reading of Data] Lateral Access The method of laterally accessing and reading data from the memory device 34 is as follows. The first word line 7 designated by the address WXi (i = 1, 2, ..., M). Is set to a high potential, the first word line 7 having an address other than WXi is set to a low potential, and the first bit line 8 and second
Bit lines 9 to memory cells Ci1, Ci2, ..., Cin
Read the data of.

The second word line 32 designated by the vertical access address WYj (j = 1, 2, ..., N) is set to a high potential, and the second word line 32 having an address other than WYj is set to a low potential. , The data of the memory cells C1j, C2j, ..., Cmj are read from the pre-charged third bit line 33.

Simultaneous two-way access Data can be accessed in the horizontal direction and at the same time in the vertical direction and read from two directions. For example, the first word line 7 designated by the address WXi is set to a high potential, the first word line 7 having an address other than this is set to a low potential, and the first pre-charged first bit line 8 and 2 bit lines 9 to memory cells Ci1, Ci
Read the data of 2, ..., Cin. At the same time, the second word line 32 designated by the address WYj is set to high potential, the second word lines 32 having other addresses are set to low potential, and the pre-charged third bit line 33 is set. , Memory cells C1j, C2j, ..., Cmj
Read the data stored in. In this way, the two-way access static memory cell 30 can realize a two-way access static memory device capable of reading data from two directions equally, which is impossible with the conventional one-way access memory device.

[Embodiment of the Invention] FIG. 1 shows a first embodiment of the present invention.
FIG. In FIG. 1, the memory cell 50 is
Information holding means by a static flip-flop 4 having two input / output terminals 2 and 3, for example, an n-channel MI
It has three transistors 5, 6, 51 formed of S-type field effect transistors, one word line 7, and two bit lines 8, 9. The static flip-flop 4 has two input / output terminals 2 and 3, and the inside is the same as in FIG.
It has the same circuit configuration as. The gates of the first transistor 5 and the second transistor 6 are commonly connected to the word line 7. The gate of the third transistor 51 is connected to the first bit line 8. The first input / output terminal 2 of the static flip-flop 4 is connected to the first bit line 8 via the first transistor 5. At the same time, the first input / output terminal 2 is connected to the word line 7 via the third transistor 51.
The second input / output terminal 3 of the static flip-flop 4 is connected to the second bit line 9 via the second transistor 6. The above is the configuration of the memory cell 50.

The operation of the memory cell 50 will be described below. [Data Writing] In the memory cell 50 having such a configuration, a potential having the same phase as the data to be written is applied to the first bit line 8 and a potential having the opposite phase to the data to be written is applied to the second bit line 9. , The word line 7 is set to a high potential. In this way, the first transistor 5 controlled by the word line 7
Then, the second transistor 6 is turned on and becomes conductive. Therefore, the potential of the first bit line 8 and the potential of the first input / output terminal 2 become the same potential. Also, the second bit line 9
And the potential of the second input / output terminal 3 become the same potential.
In this way, the in-phase and anti-phase potentials are applied to the data to be written to the two input / output terminals 2 and 3 of the static flip-flop 4, so that the on / off state of the static flip-flop changes. Data can be written. Here, the potential of the first bit line 8 changes depending on the data to be written, and the on / off state of the third transistor 51 controlled by the first bit line 8 transitions. In addition to the write path via the first transistor 5, a path via the third transistor 51 may occur. However, there is no contradiction in writing for the reasons described below.
That is, when the data to be written is "1", the first bit line 8 has a high potential and the third transistor 51 is conductive. As a result, the word line 7 is connected to the first input / output terminal 2.
The new potential is applied, but since it has the same high potential as the first bit line 8, there is no contradiction. When the data to be written is "0", the first bit line 8 has a low potential, and the third bit line 8 has the third potential.
Transistor 51 is non-conductive. Therefore, only the potential of the first bit line via the first transistor 5 is the first
It is applied to the input / output terminal 2 of and there is no conflict.

[Holding of Data] In order to hold this data, both the word line 7 and the first bit line 8 are set to a low potential, and the two input / output terminals 2 and 3 are both set to a high impedance state. As a result, the state of the static flip-flop 4 is maintained.

[Reading of Data] Lateral Access After the first bit line 8 and the second bit line 9 are discharged to the same potential and set to the low potential, the word line 7 is set to the high potential and the static flip-flop 4 is set. Is transmitted to the first bit line 8 and the second bit line 9 and the potential difference between these bit lines 8 and 9 is detected,
Data can be read. Similarly, after the bit lines 8 and 9 are discharged to an equal potential and set to a low potential, the word line 7 is set to a high potential and the potential of the first bit line 8 through which the potential of the first input / output terminal 2 is transmitted. Data can also be read by detecting a change. Similarly, after the bit lines 8 and 9 are discharged to an equal potential and set to a low potential, the word line 7 is set to a high potential and the second input / output terminal 3
The data can also be read by detecting the change in the potential of the second bit line 9 through which the potential of 2 is transmitted. In the above access, the bit line is discharged before the word line is set to the high potential. This means that if the first bit line 8 is precharged, the third transistor 51 is turned on, the high potential of the word line 7 is applied to the first input / output terminal 2, and the data is written in the flip-flop 4. This is because there is a possibility that the state cannot be maintained.

Vertical Access In order to access data in the vertical direction and read data, the word line 7 is discharged to a low potential while the second bit line 9 is at a low potential, and then the first bit line is discharged. 8 is set to a high potential, the change in the potential of the word line 7 is detected, and the data is read. Here, the second bit line 9 is set to a low potential for the following reason. If "1" is written in the first input / output terminal 2, the potential of the word line 7 rises after discharging and the second transistor becomes conductive, but the second bit line 9 is set to a low potential. Therefore, "0" is written in the second input / output terminal 3, and the data can be read while holding the data. As described above, it is possible to configure a two-way access static memory cell that can equally read data from two directions.

FIG. 4 shows the memory cell 50 shown in FIG.
Two (m × n) rows are arranged in n rows and the signal lines 7, 8 and 9 are arranged so as to be shared by adjacent vertical and horizontal memory cells, respectively.
3 is a conceptual diagram of a directional access static memory device 52. FIG. Since address circuits, signal line drive circuits and the like necessary for constructing the two-way access static memory device 52 can use the same circuits as those used in the conventional static memory device, they are all omitted in FIG. I am doing it. The word line 7 is selected when it is accessed in the horizontal direction and given the addresses WX1, WX2, ..., WXm, respectively, and the first bit line 8 is set to the bit lines BY1, BY.
2, ..., BYn and the second bit line 9 are bit lines BY
Data is read and written via 1 ', BY2', ..., BYn '. Further, the first bit line 8 is selected when accessing in the vertical direction, and the addresses WY1, WY2, and
..., WYn (WYj = BYj, j = 1, ..., n),
The word lines 7 are BX1, BX2, ..., BXm (BXi = WX
i, i = 1, ..., M) also has the function of the bit line.

The operation of the memory device 52 will be described below. [Data Writing] Memory Cell Cij (i = 1, 2, ...,
When writing data to m j = 1, 2, ..., N), the word line 7 of the address WXi is set to a high potential, the word lines 7 of other addresses are set to a low potential, and the potential in the same phase as the data to be written is set to the first potential. It is applied to BYj of the bit line 8 and a potential opposite in phase to the data to be written is applied to BYj 'of the second bit line 9.

[Reading of Data] Lateral Access In the method of laterally accessing and reading data from the memory device 52, the word line 7 designated by the address WXi (i = 1, 2, ..., M) is set to a high potential. Then, the word lines 7 of addresses other than this are set to a low potential, and the data of the memory cells Ci1, Ci2, ..., Cin are read from the first bit line 8 and the second bit line 9 which have been discharged in advance.

Vertical access With the second bit lines 9 all set to low potential, the first bit line 8 designated by the address WYj (j = 1, 2, ..., N) is set to high potential, and Memory cells C1j, C2j, ..., From the previously discharged word line 7 to the first bit line 8 of an address other than
Read the data of Cmj. In this way, the two-way access static memory device which can perform the data read from the two directions equally, which is impossible in the conventional one-way access memory device, is provided as the two-way access static memory cell 5.
It can be realized by 0.

Further, in the present invention, the amount of hardware can be greatly reduced by sharing the word line and the bit line. This will be described below. The minimum unit circuit of the present invention shown in FIG. 1 (when K = 0 and M = 0)
, The word line 7 (WX
m) also serves as a bit line (BXm), and the bit line 8 (BYn) also serves as a word line (WYn). Therefore, the number of word lines or bit lines can be significantly reduced.

Next, FIG. 5 is a second embodiment of the present invention. 5, a memory cell 60 is the same as the memory cell 50 of FIG. 1 except that two transistors 61 and 62 each composed of, for example, an n-channel MIS field effect transistor.
And a static flip-flop 4 configured by adding two word lines 63 and 64, two input / output terminals 2 and 3, transistors 5, 6 and 51, a first word line 7 and a bit line 8 , 9 have the same connection relationship as the memory cell 50. In this embodiment, there are two word lines.
Although it is added, since there is no bit line added, K = 2,
This corresponds to the case of M = 0.

The gate of the fourth transistor 61 has the second
Is connected to the word line 63. The gate of the fifth transistor 62 is connected to the third word line 64. The first input / output terminal 2 of the static flip-flop 4 is connected to the word line 7 via the fifth transistor 62.
It is connected to the. The second input / output terminal 3 of the static flip-flop 4 is connected to the second bit line 9 via the fourth transistor 61. The above is the configuration of the memory cell 60.

The operation of the memory cell 60 will be described below. [Data Writing] In the memory cell 60 having such a configuration, a potential having the same phase as the data to be written is applied to the first bit line 8 and a potential having the opposite phase to the data to be written is applied to the second bit line 9. , The first word line 7 is set to a high potential.
In this way, the first transistor 5 and the second transistor 6 controlled by the word line 7 are turned on,
Conduct. Therefore, the potential of the first bit line 8 and the potential of the first input / output terminal 2 become the same potential. Further, the potential of the second bit line 9 and the potential of the second input / output terminal 3 become the same potential. In this way, the static flip-flop 4
Since the in-phase and anti-phase potentials are applied to the data to be written to the two input / output terminals 2 and 3, the on / off state in the static flip-flop changes accordingly, and the data can be written.

[Holding of Data] In order to hold this data, all of the word lines 7, 63, 64 and the first bit line 8 are set to low potential, and the two input / output terminals 2 and 3 are both set to high. By setting the impedance state, the state of the static flip-flop 4 is maintained.

[Reading of Data] Lateral Access Data is read in the same manner as the memory cell 50. However, the word lines 63 and 64 are kept at a low potential. Vertical access Data is read in the same manner as the memory cell 50 described above. However, the word lines 63 and 64 are kept at a low potential. Diagonal upper right access With the word line 7 at a low potential, the second word line 63
Is set to a high potential, the potential change of the second bit line 9 is detected, and the data is read. Oblique upper left direction access With the first bit line 8 set to a low potential, the third word line 64 is set to a high potential, the potential change of the first word line 7 is detected, and the data is read. With the above configuration, the address is selected from four directions and two directions are selected.
From the data reading can be configured in four directions access static memory cell that allows equivalent.

FIG. 6 shows the memory cell 60 shown in FIG.
Signal lines 7, 8, 9, 6 are arranged in (m × n) rows and n columns.
Reference numerals 3 and 64 are conceptual views of a four-way access static memory device 65 in which shared wiring is made with adjacent vertical and horizontal memory cells. 4-way access static memory device 6
Since the address circuit, the signal line drive circuit, and the like necessary for forming 5 can be the same as the circuits used in the conventional static memory device, they are omitted in FIG. Address WX of first word line 7
1, WX2, ..., WXm, BY1, of the first bit line 8
BY2, ..., BYn, BY1 ′, B of the second bit line 9
, BYn ', addresses WY1, WY2, ..., WYn by the first bit line 8 and BX1, BX2, ..., BXm by the first word line 7 are used similarly to the memory device 52 of FIG. To be On the other hand, the addresses WR1, WR2, ..., WR (m + n-1) are given to the second word line 63 and are selected when accessing in the diagonally upper right direction, and the addresses WL1, WL2 ,. , WL (m + n-
1) is given and is selected when accessing diagonally to the upper left. The operation of the memory device 65 will be described below.

[Data Writing] Memory Cell Cij (i
= 1, 2, ..., Mj = 1, 2, ..., N), when writing data to the address WX as in the memory device 52 described above.
The first word line 7 of i is set to a high potential, the word lines 7, 63, 64 of the other addresses and the bit line 8 are set to a low potential, and a potential in the same phase as the data to be written is applied to BYj of the first bit line 8. Then, the potential opposite in phase to the data to be written is applied to the second bit line 9BYj '.

[Reading of Data] Horizontal Access Data is read in the same manner as the memory device 52. However, word lines other than the corresponding address are set to low potential.

Vertical access Data is read in the same manner as the memory device 52 described above. However, word lines other than the corresponding address are set to low potential.

The second word line 63 designated by the diagonally upper right access address WRi (i = 1, 2, ..., M + n-1) is set to a high potential, and the second word lines 63 of other addresses are set. And all the first word lines 7 are set to a low potential, and the data of the corresponding memory cell is read from the second bit line 9 which is previously discharged.

Oblique upper left access With the second bit line 9 set to a low potential in advance, the third word line 64 designated by the address WLi (i = 1, 2, ..., M + n-1) is set to a high potential. Then, the third word line 64 of all other addresses and all the first bit lines 8 are set to a low potential, and the data of the corresponding memory cell is read from the first word line 7 which is previously discharged. As described above, the four-direction access static memory device capable of selecting the addresses from the four directions and reading the data from the two directions is equivalent to the four-direction access static memory cell 60.
It can be configured by. In this way, it is possible to realize a four-way access static memory device that can equally select addresses from four directions, which was impossible with the conventional unidirectional access memory device.

As described above, in the first embodiment according to the present invention, 1
In the case of a memory cell capable of reading data in two directions by selecting word lines and two bit lines in the two-direction address, in the second embodiment,
The case of a memory cell capable of reading 4-direction address selection 2-direction data of 3-word line 2-bit line type is shown. As shown in these embodiments, a conventional unidirectional access memory cell has one first transistor and K other (K
By adding a transistor of ≧ 0, an integer) and a word line in the K direction and a bit line of the M direction (K ≧ M ≧ 0, an integer), K + 1 word lines or gates of transistors are connected. Addresses can be selected with a single bit line provided, and word line or M
A memory cell capable of multi-directional address selection capable of reading data from a bit line in the direction can be formed. When a plurality of these memory cells are arranged in an array, the memory cell array is selected in the K + 2 direction, and the M + 2 direction is selected. It is possible to realize a memory device that can read data from the memory. Also, M + 1
It is also possible to select addresses in the direction and read simultaneously from the bit lines in the direction M + 1.

As described above, according to the memory cell of the present invention, a memory device capable of address selection from multiple directions can be realized. In the case of processing two-dimensionally arranged data such as image processing and character recognition, the multidirectional access static memory device including the memory cell of the present invention cannot be used in the conventional unidirectional access static memory device. It becomes possible to easily read data from the existing multiple directions. As an example, FIG. 7 shows an example in which the 4-way access static memory device according to the present invention is applied to the pattern memory devices 17 to 21 in the examples of FIGS. 9 and 10 described in the section of the prior art. A four-way access static memory device 70 capable of address selection from four directions shown in FIG. 7 is realized when m = 7 and n = 5 of the pattern memory device 65 of the present invention shown in FIG.
Addresses and bit lines of the pattern memory device 70 of FIG. 7 are used for the same purpose as the memory device 65. The operation of the above device is as follows. When data is scanned in the horizontal direction, it is selected by the addresses WX1 to WX7, and the bit lines BY1 to BY5 or the bit lines BY1 'to BY5' are selected.
Read from. When data is scanned in the vertical direction, it is selected by the addresses WY1 to WY5 and the bit lines BX1 to BX are selected.
Read from X7. When scanning the data in the diagonally upper right direction, the data is selected by the addresses WR1 to WR11 and read from the bit lines BY1 'to BY5'. When scanning the data in the diagonally upper left direction, the data is selected by the addresses WL1 to WL11 and read from the bit lines BX1 to BX7.
From the above, one access is sufficient no matter which direction, vertical, horizontal or diagonal, the data is read. That is, in the conventional unidirectional access memory device having m rows and n columns, when scanning in a direction different from the word line,
In the worst case, m accesses are required, whereas the multi-directional access memory device of the present invention can be executed with one access.

Although only a few examples of the memory cell have been described above, various modifications and changes can be made without departing from the spirit of the present invention.

[0047]

As described above, according to the present invention, it is possible to easily read data from multiple directions, which is impossible with the conventional unidirectional access static memory device. Further, according to the present invention, not only is it unnecessary to provide a memory device for each scanning direction, but it is not necessary to change the arrangement for each scanning direction in advance and write data to the memory device, which reduces the hardware amount and the selection time. There is a significant reduction effect. Further, in the present invention, since the bit lines can be shared in multiple directions, and the word line and the bit line can be used in common,
Since the number of bit lines and word lines can be reduced and the peripheral circuits associated with those lines can be reduced accordingly, the effect that the total hardware amount can be significantly reduced is achieved. can get.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a one-word-line / two-bit-line bidirectional access memory cell according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory cell which is the basis of the present invention.

FIG. 3 is a circuit diagram of a memory device in which the memory cells of FIG. 2 are arranged in an array.

FIG. 4 is a circuit diagram of a bidirectional access memory device in which the bidirectional access memory cells of FIG. 1 are arranged in an array.

FIG. 5 is a circuit diagram of a 4-word access memory cell of 3 word lines and 2 bit lines type according to a second embodiment of the present invention.

6 is a circuit diagram of a 4-way access memory device in which the 4-way access memory cells of FIG. 5 are arranged in an array.

FIG. 7 is a conceptual diagram of a 4-way access pattern memory device for character data.

FIG. 8 is a circuit diagram of a conventional unidirectional access memory device including 1 word line and 2 bit line unidirectional access memory cells.

FIG. 9 is a conceptual diagram when there is one pattern memory device for character data.

FIG. 10 is a conceptual diagram when there are four character data pattern memory devices. Explanation of reference numerals 1 ... Unidirectional access memory cell 2, 3 ... Input / output terminal 4 ... Static flip-flop 5, 6 ... N channel MIS field effect transistor 7 ... Word line 8, 9 ... Bit line 10, 11 ... N channel MIS field effect transistor 12, 13 ... P-channel MIS field effect transistor 14 ... Power supply terminal 15 ... Unidirectional access memory device 16 ... Character data 17, 18 ... Unidirectional access memory device of 7 rows and 5 columns 19, 20 11-row, 5-column unidirectional access memory device 21 ... 5-row, 7-column unidirectional access memory device 30 ... 2-word line 3-bit line 2-way access memory cell 31 ... n-channel MIS field effect transistor 32 ... Word line 33 ... Bit line 34 ... Bidirectional access memory device 50 ... 1 Word line 2 Bit line type 2-way Access memory cell 51 ... N-channel MIS field effect transistor 52 ... 2-way access memory device 60 ... 3 word line 2-bit line 4-way access memory cell 61, 62 ... N-channel MIS field effect transistor 63, 64 ... Word line 65 ... 4-direction access memory device 70 ... Pattern memory device for character data

Claims (1)

[Claims] 1. A first and a second transistor, and 2
A static flip-flop having a plurality of input / output terminals, one end other than the gate of the first transistor is connected to the first input / output terminal of the static flip-flop, and one end other than the gate of the second transistor is connected. A plurality of memory cells, each of which is connected to the second input / output terminal of the static flip-flop, are combined in a matrix of m rows and n columns, and one word line in each row and first and second rows in each column. 2 bit lines, the gates of the 2 transistors in each memory cell are commonly connected to the 1 word line in the corresponding row, and the other end other than the gate of the 1st transistor is in the corresponding column. Of the second transistor connected to the first bit line and the other end other than the gate of the second transistor connected to the second bit line of the corresponding column. The each memory cell, one of the
3 transistors and K other than that (K ≧ 0, integer)
, A word line in the K direction and a bit line in the M direction (K ≧ M ≧ 0, an integer) are added to the memory device, and the gate of the third transistor is added to the memory device.
Connected to the L-th bit line (L = 1 or 2) of the two bit lines, and one end other than the gate of the third transistor is connected to the L-th input / output terminal of the static flip-flop, The other end other than the gate of the third transistor is connected to the one word line, and is the N-th (K ≧ N ≧ 0, integer) for each of the K transistors.
And the N of the word line in the K direction.
The word line of the Kth transistor is connected to one of the two input / output terminals of the static flip-flop and the gate of the Nth transistor of the Kth transistor. The other end except the above is not connected to the gate of the transistor
Connected to one bit line or one of the M-direction bit lines or the one word line, and selects data from one direction to write data from one direction.
A multi-directional read one-way write memory device characterized in that an address can be selected from the K + 2 direction and data can be read from the M + 2 direction.