JPH0743946B2 - Non-volatile CAM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a non-volatile CAM, and in particular, in addition to a normal memory function of reading and writing data by designating an address, A non-volatile CAM (Conte
nt-Addressable Memory).

[Prior Art] Figure 6 shows the ISSCC (Digest of Technical Papers 42 or
It is an electric circuit diagram which shows the conventional volatile CAM shown in page 43 (1985)).

In FIG. 6, the CAM is composed of a CMOS static RAM section 1 and a coincidence detection section 2. There are four match detection units 2.
It consists of MOS transistors 3 to 6, MOS transistors 3 and 4 are connected in series, and MOS transistors 5 and 6 are connected in series. The source of the MOS transistor 3 is grounded, the gate is connected to the second storage node N2 of the CMOS static RAM unit 1 including a flip-flop, and the gate of the MOS transistor 4 is a bit line BL forming a bit line pair.
, And the drain is connected to the coincidence detection line M.

The source of the MOS transistor 5 is grounded and the gate is CMOS
It is connected to the first storage node N1 of the static RAM unit 1, the gate of the MOS transistor 6 is connected to the bit line ▲ ▼, and the drain is connected to the match detection line M.

The CMOS static RAM section 1 is composed of four MOS transistors 7 to 10 and also includes two MOS transistors 12 and 13 serving as transfer gates. CMOS static
The source of the MOS transistor 12 is connected to the first storage node N1 of the RAM unit 1, and the drain is connected to the bit line BL.
The gate is connected to the word line W. The source of the MOS transistor 13 is connected to the second storage node N2 of the CMOS static RAM unit 1, and the drain is the bit line ▲.
The gate is connected to the word line W.

Next, the operation of the conventional CAM shown in FIG. 6 will be described. First, when performing a match search, all the word lines W are set to the "L" level, the match detection line M is precharged to the "H" level, the search data is given to the bit line BL, and the bit line ▲ ▼ is supplied. This is performed by applying an inverted signal of search data. For example, when searching for "1", the bit line BL is set to "H" level and the bit line ▲ ▼ is set to "L" level. When “1” is stored in the CMOS static RAM unit 1, that is, when the first storage node N1 is “H” and the second storage node N2 is “L” level, the MOS is Transistor
Although 4,5 are conductive, the MOS transistors 3 and 6 are non-conductive, so that the match detection line M is kept at the "H" level. If "0" is stored in the CMOS static RAM unit 1, that is, if the first storage node N1 is at "L" level and the second storage node N2 is at "H" level, then the MOS transistor 3, 4 become conductive, the coincidence detection line M is discharged to the ground potential.

[Problems to be Solved by the Invention] As described above, the conventional CAM is a C including flip-flops.
It consists of a MOS static RAM unit 1 and a match detection unit 2. Therefore, when power is turned off, CMOS static RA
There is a drawback that the data stored in the M section 1 is erased.

Therefore, a main object of the present invention is to provide a nonvolatile CAM in which data is not lost even when the power is turned off.

[Means for Solving the Problem] According to the present invention, a plurality of memory cells arranged in a matrix of rows and columns, each of which has a first storage node and a second storage node, and each of which stores information, and each of which is a column. A plurality of word lines for selecting memory cells aligned in the direction, a plurality of bit line pairs connected to the memory cells aligned in the column direction, information of the bit line pairs and information stored in the memory cells A non-volatile CAM that outputs a match signal when the two match, the gate is connected to the first storage node of the memory cell, and the first conductive terminal is one of the bit line pair. And a first MOS transistor having a second conduction terminal connected to the coincidence detection line, a gate connected to the second storage node of the memory cell, and a first conduction terminal connected to the other of the bit line pair. Connected and the second lead The communication terminal includes a second MOS transistor connected to the coincidence detection line, and the memory cell is composed of a nonvolatile memory.

[Operation] Since the memory cell of the non-volatile CAM according to the present invention is composed of the non-volatile memory, there is no fear that the data stored up to that time will be erased even when the power is turned off.

[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. First, the configuration of an embodiment of the present invention will be described with reference to FIG. The NVRAM 11 is a non-volatile memory and includes first and second storage nodes N1 and N2. First
The storage node N1 is connected to the gate of the first MOS transistor 14, the drain is connected to the bit line BL, and the source is connected to the coincidence detection line M. The gate of the second MOS transistor 15 is connected to the second storage node N2, the drain thereof is connected to the bit line ▲ ▼, and the source thereof is connected to the coincidence detection line M. The source of the third MOS transistor 12 is connected to the first storage node N1, the gate is connected to the word line W, and the drain is connected to the bit line BL. A fourth MOS transistor 1 is provided at the second storage node N2.
The source of 3 is connected, the gate is connected to the word line W, and the drain is connected to the bit line.

The operation as the nonvolatile CAM shown in FIG. 1 is the same as that of the conventional example shown in FIG. That is, the word line W is set to the "L" level, the match detection line M is precharged to the "H" level, the search data signal is applied to the bit line BL, and the inverted signal of the search data is supplied to the bit line ▲ ▼. Is given. If the information stored in the NVRAM 11 matches the search data, the match detection line M maintains the "H" level, and if they do not match, the match detection line M is discharged to the "L" level.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. The embodiment shown in FIG. 2 is shown in FIG.
A MOS transistor 16 is connected in series to the MOS transistor 14, and a MOS transistor is connected to the MOS transistor 15.
17 are connected in series. More specifically, the gate of the MOS transistor 14 has the second storage node N2.
And the source is grounded. MOS transistor 14
The drain of is connected to the source of the MOS transistor 16, and M
The gate of the OS transistor 16 is connected to the bit line BL, and the drain is connected to the match detection line M. The gate of the MOS transistor 15 is connected to the first storage node N1 and the source is grounded. The drain of the MOS transistor 15 is MOS
MOS transistor 1 connected to the source of transistor 17
The gate of 7 is connected to the bit line ▲ ▼, and the drain is connected to the coincidence detection line M. Even if the non-volatile CAM is configured as described above, the same operation as that in FIG. 1 described above can be performed.

FIG. 3 is a more specific electric circuit diagram of the nonvolatile CAM shown in FIG. In FIG. 3, the NVRAM 11 is composed of a static RAM 20 and an EEPROM 23. Information is stored and read by the static RAM 20. When nonvolatile storage is required, the data stored in the static RAM 20 is transferred to the EEPROM 23. .

To explain the more specific configuration, static RA
M20 is an N-channel depletion type MOS transistor 26,2
7 and N-channel enhancement type MOS transistor 18,1
Composed of 9 and. A power supply voltage is applied as a first reference potential to the drain of the N-channel depletion type MOS transistor 26, and the gate and source thereof are the first storage node N1.
Connected to. A power supply voltage is applied to the drain of the N-channel depletion type MOS transistor 27, and its gate and source are connected to the second storage node N2. N channel
The gate of the MOS transistor 18 is connected to the second storage node N2, the drain is connected to the first storage node N1, and the source is connected to the ground potential which is the second reference voltage. N
The gate of the channel MOS transistor 19 is connected to the first storage node N1, the drain is connected to the second storage node N2, and the source is grounded.

Further, N channel MOS transistors 12 to 15 are provided, the gate of the N channel MOS transistor 12 is connected to the word line W, the drain is connected to the bit line BL, and the source is connected to the first storage node N1. It The gate of the N-channel MOS transistor 13 is connected to the word line W, the drain is connected to the bit line {circle around (5)}, and the source is connected to the second storage node N2. The gate of the N-channel MS transistor 14 is connected to the first storage node N1, the drain is connected to the bit line BL, and the source is the match detection line M.
Connected to. The gate of the N-channel MOS transistor 15 is connected to the second storage node N2, the drain thereof is connected to the bit line ▲ ▼, and the source thereof is connected to the coincidence detection line M.

The EEPROM 23 is composed of N-channel MOS transistors 21 and 24 and a memory transistor 22. The clock signal CLK is applied to the gate of the N-channel MOS transistor 21, the source is connected to the second storage node N2, and the drain is connected to the source of the memory transistor 22. The program signal PRO is applied to the gate of the memory transistor 22 and the drain thereof is connected to the source of the N-channel MOS transistor 24. The clear signal CLR is applied to the drain and gate of the N-channel MOS transistor 24.

Next, the specific operation of the embodiment shown in FIG. 3 will be described. First, when transferring data, use the clock signal
CLK becomes "L" level, program signal PRO is set to "L" level, and high voltage pulse is N as clear signal CLR.
The data supplied to the drain and gate of the channel MOS transistor 24 and stored in the EEPROM 23 is erased. That is, the electrons accumulated in the floating gate of the memory transistor 22 of the EEPROM 23 are extracted and the threshold value becomes low.

Next, the clock signal CLK is set to “H” level, the clear signal CLR is set to “L” level, and a high voltage pulse is applied to the gate of the memory transistor 22 as the program signal PRO. If "1" is stored in the static RAM 20, the first storage node N1 is at "H" level and the second storage node N2 is at "L" level, so the drain of the memory transistor 22 is grounded. A potential is applied, and electrons are injected into the floating gate.

If "0" is stored in the static RAM 20, the first storage node N1 is at "L" level, and the second storage node N2 is at "H" level, the voltage of the drain of the memory transistor 22. Remains high, no electron injection into the floating gate occurs. That is, since the potential difference between the gate and the drain of the memory transistor 22 is small, the charge accumulated in the floating gate does not change. In this way, static RAM 20 to E
Data is transferred to EPROM23.

Next, the data transfer from the EEPROM 23 to the static RAM 20 is performed by setting the clock signal CLK, the program signal PRO and the clear signal CLR to the “H” level and gradually increasing the power supply to the NVRAM 11 from 0V. At this time, if the threshold value of the EEPROM 23 is low, the second
The storage node N2 is charged and the static RAM 20 is set to "0". On the other hand, if the threshold value of the EEPROM 23 is high, the first storage node N1 is charged to the "H" level and the static RA is set to "1".
M20 is configured.

FIG. 4 is an electric circuit diagram of another embodiment of the present invention. The embodiment shown in FIG. 4 is a static RAM 20 and an EEPRO.
The M23 is constructed in the same manner as the embodiment shown in FIG.
The gate of the MOS transistor 17 is connected to the first storage node N1, the drain of the MOS transistor 17 is connected to the coincidence detection line M, and the source is connected to the drain of the MOS transistor 15. The gate of the MOS transistor 15 is connected to the bit line () and the source is grounded. Further, the MOS transistor 16 is connected to the second storage node N2.
Of the MOS transistor 16 is connected, the drain of the MOS transistor 16 is connected to the coincidence detection line M, and the source is the MOS transistor 14
Connected to the drain of. The gate of the MOS transistor 14 is connected to the bit line BL, and the source is grounded.

By configuring the non-volatile CAM in this way, similar to the embodiment shown in FIG. 3 described above, normal data is stored in the static RAM 20, and when non-volatile storage is required, it is stored in the static RAM 20. The stored data can be transferred to the EEPROM 23.

FIG. 5 is an electric circuit diagram showing another embodiment of the present invention. In this embodiment, a sensor line S, for giving data to be searched is newly provided. And
The gate of the MOS transistor 14 is connected to the first storage node N1, and the sensor line is connected to the drain thereof. MOS
The source of transistor 14 is connected to the gate of MS transistor 25. The second storage node N2 has a MOS transistor 1
The gate of 5 is connected, the sensor line S is connected to the drain, and the source is connected to the gate of the MOS transistor 25. The drain of the MOS transistor 25 is connected to the coincidence detection line M, and the source is grounded.

When searching for data in this embodiment, the word line W is set to the "L" level, the coincidence detection line M is precharged to the "H" level, the inverted signal of the search data is given to the sensor line, and the search line is searched. This is done by giving S a search signal. For example, to search for "1", the sensor line is set to the "L" level and the sensor line S is set to the "H" level. If "1" is stored in the static RAM 20, the first storage node N1 is at "H" level, and the second storage node N2 is at "L" level, the MOS transistor 14 becomes conductive. , The gate potential of the MOS transistor 25 becomes "L" level and the MOS transistor 25 becomes non-conductive, so that the coincidence detection line M maintains "H" level.
If "0" is stored in the static RAM 20, the first storage node N1 is at "L" level, and the second storage node N2 is at "H" level, the MOS transistor 15 And 25 become conductive, and the coincidence detection line M becomes the ground potential.

[Effects of the Invention] As described above, according to the present invention, since the memory cell is configured by the non-volatile memory, there is no possibility of erasing data even when the power is cut off.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. FIG. 3 is a specific electric circuit diagram of the nonvolatile CAM shown in FIG. FIG. 4 is an electric circuit diagram of another embodiment of the present invention. FIG. 5 is an electric circuit diagram showing another embodiment of the present invention. FIG. 6 is an electric circuit diagram showing a configuration of a conventional CAM. In the figure, 11 is NVRAM, 12 to 17, 21, 24, 25 are N-channel MOS transistors, 18 and 19 are N-channel enhanced MOS transistors, 20 is static RAM, 22 is memory transistor, 23 is EEPROM, 26, 27. Indicates an N-channel depletion type MOS transistor.

Claims (1)

[Claims] 1. A plurality of memory cells arranged in a matrix of rows and columns, each having a first storage node and a second storage node, for storing information and aligned in the column direction. A plurality of word lines for selecting a memory cell, a plurality of bit line pairs connected to the memory cells aligned in the column direction, information of the bit line pairs and information stored in the memory cells. Non-volatile with a match detect line that outputs a match signal when there is a match
CAM comprising a gate and first and second conducting terminals, said gate being connected to a first storage node of said memory cell, said first conducting terminal being connected to one of said bit line pairs , The second conduction terminal is connected to the coincidence detection line, and
A MOS transistor, and a gate and first and second conduction terminals, the gate being connected to a second storage node of the memory cell, the first conduction terminal being connected to the other of the bit line pair, The second conduction terminal is a second connection terminal connected to the coincidence detection line.
Including a MOS transistor, wherein the memory cell is composed of a non-volatile memory,
Non-volatile CAM.