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JPH0744328B2 - Electroplating method for electronic component substrates - Google Patents
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JPH0744328B2 - Electroplating method for electronic component substrates - Google Patents

Electroplating method for electronic component substrates

Info

Publication number
JPH0744328B2
JPH0744328B2 JP61056815A JP5681586A JPH0744328B2 JP H0744328 B2 JPH0744328 B2 JP H0744328B2 JP 61056815 A JP61056815 A JP 61056815A JP 5681586 A JP5681586 A JP 5681586A JP H0744328 B2 JPH0744328 B2 JP H0744328B2
Authority
JP
Japan
Prior art keywords
electroplating
surface wiring
wiring pattern
external terminal
coating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61056815A
Other languages
Japanese (ja)
Other versions
JPS62214690A (en
Inventor
哲也 渡辺
正雄 関端
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61056815A priority Critical patent/JPH0744328B2/en
Publication of JPS62214690A publication Critical patent/JPS62214690A/en
Publication of JPH0744328B2 publication Critical patent/JPH0744328B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子部品用基板の電気めっき方法に係り、電
気めっきの陰極電極となるべき外部端子と接続のない表
面配線パターンにも電気めっきを可能にする好適な電気
めっき方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for electroplating a substrate for electronic parts, and also to electroplating a surface wiring pattern which is not connected to an external terminal to be a cathode electrode for electroplating. A suitable electroplating method that enables

〔従来の技術〕[Conventional technology]

従来、電気めっきの陰極電極となるべき外部端子と接続
のない表面配線パターンに電気めっきを施そうとする場
合、特開昭59-153891号公報に記載のように、前記端子
と接続のあるパターンを又は前記端子を導電塗布層で連
結しさらにその上に絶縁材を被覆し露出したパターンの
みに所望の電気めっきを施していた。しかしこの方法で
は、導体塗布層とパターンの間の接続抵抗大により所望
の電気めっきが得られない不良が生じる可能性があっ
た。
Conventionally, when attempting to perform electroplating on a surface wiring pattern which is not connected to an external terminal to be a cathode electrode for electroplating, as described in JP-A-59-153891, a pattern having a connection with the terminal. Alternatively, the terminals are connected by a conductive coating layer, and an insulating material is further coated on the terminals, and only the exposed pattern is subjected to desired electroplating. However, in this method, there is a possibility that a desired electroplating cannot be obtained due to a large connection resistance between the conductor coating layer and the pattern.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記従来技術は、電気めっきのための陰極電極となる導
体塗布層と塗布層下の配線パターン間の接触抵抗と電気
めっきのつきまわりの関係について配慮がされておら
ず、上記接触抵抗が大であると所望の電気めっきが析出
しないという問題があった。
The above-mentioned prior art does not consider the relationship between the contact resistance between the conductor coating layer serving as the cathode electrode for electroplating and the wiring pattern under the coating layer and the throwing power of electroplating, and the contact resistance is large. If so, there is a problem that desired electroplating does not deposit.

本発明の目的は、上記接触抵抗の大小にかかわらず、所
望の電気めっき及び膜を形成することにある。
An object of the present invention is to form a desired electroplating and film regardless of the magnitude of the contact resistance.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記目的を達成するために、電気めっきの陰
極となる外部端子(4)と、該外部端子(4)に導通し
ている表面配線パターン(2a)と、該外部端子(4)に
導通していない複数の表面配線パターン(2b)とを有す
る電子部品用基板(1)の電気めっき方法において、該
外部端子(4)に導通している表面配線パターン(2a)
と該外部端子に導通していない複数の表面配線パターン
(2b)とを剥離可能な導電ペースト(5)で接続し、該
導電ペースト(5)のうち少なくとも前記表面配線パタ
ーン同士を共通に接続している部分(7)を前記表面配
線パターンとの境界部分を含めて露出させて絶縁材
(6)で被覆した後、電気めっきを施するようにしたこ
とを特徴としている。
In order to achieve the above object, the present invention provides an external terminal (4) serving as a cathode for electroplating, a surface wiring pattern (2a) conducting to the external terminal (4), and the external terminal (4). A method for electroplating an electronic component substrate (1) having a plurality of surface wiring patterns (2b) not electrically conducting to a surface wiring pattern (2a) electrically conducting to the external terminal (4)
And a plurality of surface wiring patterns (2b) which are not electrically connected to the external terminals are connected by a peelable conductive paste (5), and at least the surface wiring patterns of the conductive paste (5) are commonly connected. The exposed portion (7) including the boundary portion with the surface wiring pattern is exposed and covered with the insulating material (6), and then electroplating is performed.

〔作用〕[Action]

電子部品用セラミック基板に外部端子を取付けた後、電
気めっきを施す場合この外部端子を電気めっきの陰極電
極として外部端子と接続のある表面配線パターンに電気
めっきを施すことができる。一方外部端子と接続のない
表面パターンに電気めっきを施す場合、外部端子と接続
のあるパターンとないパターンを導電塗布層で連結し、
さらにその上に絶縁材を被覆し、めっきし導電塗布層と
絶縁材を除去する方法があるが、この方法では、導電塗
布層と表面配線パターンの接続抵抗が大きいと、外部端
子と接続のないパターンに電気めっきが析出しない。本
発明では上記導電塗布層を絶縁材よりわずかに露出させ
ることにより、その部分に電気めっきが析出し、そのめ
っき膜が表面配線パターンと接続されることにより、導
電塗布層と絶配線パターンの接続抵抗が大きくても所望
のめっき膜を形成できる。
When the external terminals are attached to the ceramic substrate for electronic parts and then electroplated, the external terminals can be used as a cathode electrode for electroplating and the surface wiring pattern connected to the external terminals can be electroplated. On the other hand, when performing electroplating on the surface pattern that is not connected to the external terminal, connect the pattern that is connected to the external terminal and the pattern that is not connected with the conductive coating layer,
Furthermore, there is a method of coating the insulating material on it and plating it to remove the conductive coating layer and the insulating material. In this method, if the connection resistance between the conductive coating layer and the surface wiring pattern is large, there is no connection with the external terminal. Electroplating does not deposit on the pattern. In the present invention, by exposing the conductive coating layer slightly from the insulating material, electroplating is deposited on that portion, and the plating film is connected to the surface wiring pattern, thereby connecting the conductive coating layer and the disconnection wiring pattern. A desired plating film can be formed even if the resistance is high.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図,第2図および第3図
により説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 3.

第1図は、メタライズ印刷を行った後、積層焼結を行な
うことにより所望の表面配線パターン2aおよび2bを有す
るセラミック基板の外部端子取付けパッド3に外部端子
4を接続し、表面配線パターンを導電塗布層(導電ペー
スト)5により電気結線されたところである。ここで、
表面配線パターン2aは外部端子4に内部結線などで導通
されている配線パターンであり、表面配線パターン2bは
外部端子4には電気的に接続されていない(導通されて
いない)配線パターンである。この表面配線パターンは
他の装置、例えば半導体チップキャリヤーと接続するた
めのものである。また導電塗布層はフェノール樹脂に銀
粉を分散混合して形成され、60℃20分のベーク処理を施
してある。
FIG. 1 shows that after the metallized printing is performed, the lamination is performed and the external terminals 4 are connected to the external terminal mounting pads 3 of the ceramic substrate having the desired surface wiring patterns 2a and 2b, and the surface wiring patterns are electrically conductive. It has just been electrically connected by the coating layer (conductive paste) 5. here,
The surface wiring pattern 2a is a wiring pattern that is electrically connected to the external terminal 4 by an internal connection or the like, and the surface wiring pattern 2b is a wiring pattern that is not electrically connected (not electrically connected) to the external terminal 4. This surface wiring pattern is for connecting to another device, for example, a semiconductor chip carrier. The conductive coating layer is formed by dispersing and mixing silver powder in phenol resin, and is baked at 60 ° C. for 20 minutes.

第2図はセラミック基板上の表面配線パターンの被めっ
き部を露出させるよう、また上記導電塗布層をわずかに
露出させるよう(導電塗布層露出部7)絶縁材層6を被
覆した状態の平面図及び断面図である。絶縁材層6は上
記導体塗布層と同時剥離除去可能なめっきレジストを選
べばよい。
FIG. 2 is a plan view showing a state in which the insulating material layer 6 is coated so as to expose the plated portion of the surface wiring pattern on the ceramic substrate and slightly expose the conductive coating layer (conductive coating layer exposed portion 7). FIG. The insulating material layer 6 may be selected from a plating resist that can be peeled off and removed simultaneously with the conductor coating layer.

第3図は、第2図示のセラミック基板に電気めっき法
で、表面配線パターンに所望のめっき層8を形成した
後、めっきレジスタ及び導電塗布層を導電塗布層7の部
分を除きたとえばクロロセン等の有機溶剤を用いて洗浄
除去した後、導電塗布量7の表面に析出しためっき膜を
ホーニング、たとえばサンドブラストにより除去した状
態の平面図及び断面図である。本発明によれば、電気め
っきの陰極電極である外部端子と接続のないセラミック
基板の表面配線パターンへの電気めっきを可能にした。
FIG. 3 shows that after a desired plating layer 8 is formed on the surface wiring pattern by the electroplating method on the ceramic substrate shown in FIG. 2, the plating register and the conductive coating layer are made of, for example, chlorothene except for the conductive coating layer 7. FIG. 5 is a plan view and a cross-sectional view showing a state in which the plating film deposited on the surface of the conductive coating amount 7 is removed by honing, for example, sandblasting, after being washed and removed using an organic solvent. According to the present invention, it is possible to perform electroplating on a surface wiring pattern of a ceramic substrate that is not connected to an external terminal that is a cathode electrode for electroplating.

〔発明の効果〕〔The invention's effect〕

本発明によれば、電気めっきの陰極電極となる導電塗布
層をわずかに露出させることにより、導電塗布層と被め
っきパターンとの接続抵抗が高くても所望のめっき膜が
得られ、通常20%出ていためっき不析出不良が0%に低
減できた。
According to the present invention, by slightly exposing the conductive coating layer to be the cathode electrode for electroplating, a desired plating film can be obtained even if the connection resistance between the conductive coating layer and the pattern to be plated is high, usually 20%. The plating non-precipitation defect that had appeared could be reduced to 0%.

【図面の簡単な説明】[Brief description of drawings]

第1図〜第3図は本発明の一実施例の工程を示す図であ
る。 1……セラミック基板、2a……外部端子と導電している
表面配線パターン、2b……外部端子と導電していない表
面配線パターン、3……外部端子取付パット、4……外
部端子、5……導電塗布層、6……絶縁材層、7……導
電塗布層露出部、8……めっき層。
1 to 3 are views showing steps of one embodiment of the present invention. 1 ... Ceramic substrate, 2a ... Surface wiring pattern that is conductive with external terminals, 2b ... Surface wiring pattern that is not conductive with external terminals, 3 ... External terminal mounting pad, 4 ... External terminals, 5 ... ... conductive coating layer, 6 ... insulating material layer, 7 ... conductive coating layer exposed portion, 8 ... plating layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】電気めっきの陰極電極となる外部端子と、
該外部端子に導通している表面配線パターンと、該外部
端子に導通していない複数の表面配線パターンとを有す
る電子部品用基板の電気めっき方法において、 該外部端子に導通している表面配線パターンと該外部端
子に導通していない複数の表面配線パターンとを剥離可
能な導電ペーストで接続し、該導電ペーストのうち少な
くとも前記表面配線パターン同士を共通に接続している
部分を前記表面配線パターンとの境界部分を含めて露出
させて絶縁材で被覆し、その後電気めっきを施すように
したことを特徴とする電気めっき方法。
1. An external terminal serving as a cathode electrode for electroplating,
In a method of electroplating a substrate for an electronic component, which has a surface wiring pattern conducting to the external terminal and a plurality of surface wiring patterns not conducting to the external terminal, a surface wiring pattern conducting to the external terminal And a plurality of surface wiring patterns that are not electrically connected to the external terminals are connected by a peelable conductive paste, and at least a portion of the conductive paste that connects the surface wiring patterns to each other is the surface wiring pattern. The method of electroplating is characterized in that it is exposed including the boundary portion thereof, is covered with an insulating material, and is then electroplated.
JP61056815A 1986-03-17 1986-03-17 Electroplating method for electronic component substrates Expired - Lifetime JPH0744328B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61056815A JPH0744328B2 (en) 1986-03-17 1986-03-17 Electroplating method for electronic component substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61056815A JPH0744328B2 (en) 1986-03-17 1986-03-17 Electroplating method for electronic component substrates

Publications (2)

Publication Number Publication Date
JPS62214690A JPS62214690A (en) 1987-09-21
JPH0744328B2 true JPH0744328B2 (en) 1995-05-15

Family

ID=13037872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61056815A Expired - Lifetime JPH0744328B2 (en) 1986-03-17 1986-03-17 Electroplating method for electronic component substrates

Country Status (1)

Country Link
JP (1) JPH0744328B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003002786A1 (en) * 2001-06-29 2003-01-09 Ryowa Co., Ltd. Electroplating method and printed wiring board manufacturing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103046031B (en) * 2012-12-11 2014-08-13 胜宏科技(惠州)股份有限公司 Method for chemically gold-plating circuit board

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5425302B2 (en) * 1971-09-01 1979-08-27

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003002786A1 (en) * 2001-06-29 2003-01-09 Ryowa Co., Ltd. Electroplating method and printed wiring board manufacturing method

Also Published As

Publication number Publication date
JPS62214690A (en) 1987-09-21

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