JPH0744393B2 - Operational amplifier - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an operational amplifier, and more particularly to an operational amplifier used in a switched capacitor circuit and having an initial stage of a cascade structure.

[Conventional technology]

Conventionally, the operational amplifier used for the switched capacitor filter is to prevent the influence of the parasitic capacitance generated between the gate and the source of the input transistor and between the gate and the drain,
As shown in FIG. 3, the first stage 1 has a cascade structure. The first-stage differential amplifier circuit 1 is for preventing the influence of the parasitic capacitance generated between the differential transistors M31 and M32 that commonly receive a constant current from the current source transistor M35 and the inverting input terminal VIN− and the drain of the transistor M31. Transistor M41
And M42 and their active load transistors M33 and M34. The second-stage amplifier circuit 2 includes a current source transistor M36
And an output transistor M37 that receives a signal from the first-stage differential amplifier circuit 1, a transistor M30 for phase compensation, and a capacitor.
It consists of C1. Further, the bias circuit 3 uses the current source I ₁
And the transistor M38 provide the bias voltage VB1 to the current source transistors M35 and M36. The bias circuit 4 includes the current source I ₂ and the transistors M39 and M40, and the transistors M41 and M42.
Bias voltage VB2 is applied to. VDD is the first constant potential source,
GND is the second constant potential source, ACM is the third constant potential source which is the reference level of the signal of the differential multiplier, and VOUT is the output terminal. Also, M3
1, M32, M35, M36, M38, M39, M40, M41, M42 are N-channel type M
OS transistor, M30, M33, M34, M37 are N-channel type MOS
It is a transistor.

In the conventional operational amplifier, since the bias power supply VB2 is supplied by the bias circuit 4, the bias circuit is complicated and the power consumption is large.

[Problems to be Solved by the Invention]

The conventional operational amplifier described above has a complicated bias circuit,
It had the drawback of high power consumption. An object of the present invention is to provide an operational amplifier that simplifies the bias circuit and consumes less power.

[Means for Solving the Problems]

According to the present invention, a constant current source, first and second field effect transistors for receiving a constant current from the constant current source in each source, and a source connected to the drain of the first field effect transistor. Third field effect transistors, and first and second load circuits each including fourth and fifth field effect transistors acting as loads connected to respective drains of the second and third field effect transistors, An input terminal connected to the gate of the first field effect transistor, a constant potential source connected to each gate of the second and third field effect transistors, and a drain of the fourth or fifth field effect transistor. An operational amplifier having an output terminal connected to the operational amplifier.

As described above, according to the present invention, since the gates of the second and third field effect transistors are connected to the common constant potential source, the number of constant potential sources is small and the bias circuit is simple. Also, the power consumption can be reduced.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of an embodiment of the present invention. In the figure, 1 is an initial step amplifier circuit, 2 is a second stage amplifier circuit, 3 is a bias circuit, VIN- is an inverting input terminal, and VOUT is an output terminal. VDD is the first power source, GND is the second constant potential source, ACM
Is a third constant potential source and VB is a bias power source. Also, M1, M
2 is an N-channel first stage differential pair MOS transistor, M3 and M4 are P
Channel load MOS transistors, M5 and M6 are N-channel constant current source MOS transistors, M7 is a driving stage P-channel MOS transistor M8 is a bias circuit N that forms a bias power supply VB.
The channel MOS transistors M11 and M12 are the reference level of the operational amplifier, and the third constant potential source ACM which is the gate potential of M2.
It is an N-channel depletion type MOS transistor biased to. C1 is a phase compensation capacitance, and this capacitance C1
A phase compensation and zero compensation circuit is constituted by a feedback loop formed by a series connection of ON resistances of the P channel MOS transistor M0 and the P channel MOS transistor M0. I is a current source.

N-channel depletion type MOS transistors M11, M12
By making the gate of the third constant potential source ACM, the influence of the parasitic capacitance generated between the inverting input terminal and the drain of the transistor M1 can be prevented, and the bias power supply to give to the gates of the transistors M11 and M12 can be provided. A built-in bias circuit is unnecessary. Therefore, since the bias circuit is unnecessary, the power consumption is reduced and the IC chip area is also reduced.

Here, the transistors M11 and M12 are depletion type MOS transistors, but it is obvious that they may be non-doped transistors.

Next, another embodiment of the present invention is shown in FIG.

All symbols in FIG. 2 are the same as those in FIG. In this embodiment, the cascade is only on the drain side of the first stage inverting input transistor M1.
Even at this time, if the gate of the transistor M11 in the cascade is set to the third constant potential source ACM which is the potential of the non-inverting input terminal, it is possible to prevent the influence of the parasitic capacitance generated between the inverting input terminal and the drain of the transistor M1. Since the bias circuit for generating the bias power supply for supplying the gate of the transistor M11 is unnecessary, the power is reduced and the chip area of the IC is also reduced.

It is also clear that the transistor M11 may be a non-doped transistor.

〔The invention's effect〕

As described above, the present invention is an operational amplifier having a cascade structure used in a switched capacitor circuit or the like,
By setting the bias power supply to the gates of the cascade transistors to the potential of the non-inverting input terminal of the operational amplifier, the bias circuit becomes unnecessary, so the power consumption can be reduced and the IC chip area can be reduced. effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a circuit diagram showing an example of a conventional operational amplifier. 1 ... First stage differential amplifier circuit, 2 ... Second stage amplifier circuit, 3,4
...... Bias circuit, VIN− …… Inversion input terminal, VOUT ……
Output terminals, VDD ...... first constant potential source, GND ...... second constant potential source, ACM ...... third constant potential _{source, I, I 1, I 2} ...... current source, VB, VB
1, VB2 …… Bias power supply, M0 to M12, M30 to M42 …… MOS transistor, C1 …… Capacity.

Claims (1)

[Claims] 1. A differential amplifier having a differential input transistor pair, an active load, and a constant current source, comprising a gate grounded transistor cascade-connected to at least one of the differential input transistor pair, and the gate grounded. An operational amplifier, wherein the gate of the transistor is connected to one gate of the differential input transistor.