JPH0744406B2 - Operational amplifier circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an operational amplifier circuit suitable for an integrated circuit.

[Conventional technology]

In general, various operational amplifier circuits have been proposed. Among them, the circuit shown in FIG. 3 is known as a folded cascode operational amplifier circuit.

The circuit of FIG. 3 includes a differential pair of transistors 107 and 108 and a transistor 106 connected to the transistors 107 and 108.
And the cascode stages of transistors 109, 110, 115, 116,
And a current mirror circuit of transistors 111 to 114. In addition, the current source 40 and the transistors 101 to 105 form a bias circuit.

This circuit has a good power supply voltage rejection ratio at high frequencies,
Moreover, it is known that a high DC gain can be obtained.

[Problems to be Solved by the Invention]

In the conventional folded cascode operational amplifier circuit described above, the input impedance of the built-in current mirror circuit is large. Therefore, the input section has a relatively large time constant, and it is difficult to widen the frequency characteristic of the input voltage gain. is doing. Further, if the bias current is increased in order to reduce the time constant, there is a drawback that the amplification gain is lowered together with the increase of power consumption.

An object of the present invention is to eliminate the above drawbacks and to provide an operational amplifier which operates at high speed and consumes less power.

[Means for Solving the Problems]

To achieve the above object, the present invention connects a positive voltage source to the source of a fourth transistor (p-channel),
The gate of the transistor is connected to the bias power supply, the drain of the fourth transistor is connected to the sources of the fifth transistor (p channel) and the sixth transistor (p channel), and the gate of the fifth transistor is connected to the first input terminal. A differential circuit composed of the gate of the sixth transistor connected to the second input terminal, and a positive voltage source connected to the source of the eighth transistor (p-channel), and the gate of the eighth transistor Is connected to a bias power supply, the drain of the eighth transistor is connected to the gate of the ninth transistor (n-channel) and the drain of the seventh transistor (n-channel), the source of the seventh transistor is grounded, and the source of the ninth transistor is connected. Connected to the gate of the 7th transistor and the drain of the 10th transistor (n-channel), The first cascode circuit is composed of a gate connected to a bias power supply and the source of the 10th transistor grounded, and a positive voltage source connected to the source of the 14th transistor (p-channel). The drain of the 14th transistor is connected to the gate of the 18th transistor (p-channel) and the 11th transistor (n
Channel), the gate of the eleventh transistor is connected to the bias power supply, the source of the eleventh transistor is grounded, and the positive voltage source is connected to the source of the nineteenth transistor (p-channel). The gate of the transistor is connected to the bias power supply, and the drain of the 19th transistor is connected to the
A second cascode circuit composed of the gate of 14 transistors and the source of 18th transistor, and the drain of 18th transistor connected to the output terminal, and the positive voltage source to the 13th transistor (p-channel) The gate of the 13th transistor is connected to the bias power supply, the drain of the 13th transistor is connected to the gate of the 17th transistor (n-channel) and the drain of the 15th transistor (n-channel), and the 15th transistor , The drain of the 17th transistor is connected to the output terminal, the source of the 17th transistor is connected to the gate of the 15th transistor and the drain of the 16th transistor (n channel), and the source of the 16th transistor is grounded. And a third cascode circuit composed of The drain of the transistor 9
The drain of the sixth transistor is connected to the source of the transistor, the drain of the sixth transistor is connected to the drain of the twelfth transistor (n-channel), the source of the twelfth transistor is grounded, and the drain of the ninth transistor constituting the first cascode circuit is connected to the drain of the ninth transistor. The 16th circuit which is connected to the drain of the 19th transistor which forms the 2nd cascode circuit and which forms the 3rd cascode circuit
The gate of the transistor is connected to the gate of the twelfth transistor, and the gate and drain of the twelfth transistor are connected.

To achieve the above object, the present invention connects a positive voltage source to the source of the 24th transistor (p-channel), connects the gate of the 24th transistor to a bias power supply, and connects the drain of the 24th transistor to The sources of the 25th transistor (p-channel) and the 26th transistor (p-channel) were connected, the gate of the 25th transistor was connected to the first input terminal, and the gate of the 26th transistor was connected to the second input terminal. And a positive voltage source connected to the source of the 31st transistor (p-channel), the drain of the 31st transistor being the gate of the 35th transistor (p-channel) and the 29th transistor (n
Channel), the gate of the 29th transistor is connected to the bias power supply, the source of the 29th transistor is grounded, and the positive voltage source is connected to the source of the 36th transistor (p-channel). Connected to the bias power supply, and the drain of the 36th transistor to the
A first cascode circuit consisting of the gate of the 31st transistor and the source of the 35th transistor, and the drain of the 35th transistor connected to the output terminal, and the positive voltage source to the 30th transistor (p-channel) , The gate of the 30th transistor is connected to the bias power supply, the drain of the 30th transistor is connected to the gate of the 34th transistor (n channel) and the drain of the 32nd transistor (n channel), The source is grounded, the drain of the 34th transistor is connected to the output terminal, the source of the 34th transistor is connected to the gate of the 32nd transistor and the drain of the 33rd transistor (n-channel), and the source of the 33rd transistor is grounded. The second cascode circuit that is composed of the The drain of Njisuta 27
Connect the drain of the transistor (n-channel), ground the source of the 27th transistor, connect the gate of the 27th transistor to the gate of the 28th transistor (n-channel), connect the drain of the 27th transistor to the gate of the 27th transistor Connected, the drain of the 28th transistor is connected to the drain of the 36th transistor which constitutes the first cascode circuit, the source of the 28th transistor is grounded, and the drain of the 26th transistor constitutes the second cascode circuit It is connected to the source of the transistor.

[Action]

The present invention provides a differential pair in which the gates of two transistors are connected to the first and second input terminals, respectively.
A first cascode circuit having a polarity opposite to that of the differential pair having an amplifying means from an input to a gate electrode, in which a first drain output of the differential pair is connected to an input, and an output of the first cascode circuit is connected to an input A second cascode circuit having a polarity opposite to that of the first cascode circuit having an amplifying means from the input to the gate electrode; a current mirror circuit having the second drain output of the differential pair connected to the input; It has a first cascode circuit having an amplifying means for the gate electrode and a third cascode circuit having the same polarity, and the respective outputs of the second and third cascode circuits are commonly connected to the output terminal.

The present invention also provides a differential pair in which the gates of two transistors are connected to the first and second input terminals, respectively, and a differential pair in which the first drain output of the differential pair is connected to the input. A first cascode circuit of the same polarity as the differential pair having a current mirror circuit of opposite polarity, an output of the current mirror circuit connected to an input, and amplification means from the input to the gate electrode; A drain output of the second cascode circuit is connected to the input and has a differential pair having an amplifying means from the input to the gate electrode and a second cascode circuit of opposite polarity, and the respective outputs of the first and second cascode circuits are output. Commonly connected to the terminals.

As a result, the present invention can reduce the input impedance of the built-in current mirror circuit. Further, by using the cascode circuit having the amplifying means, high speed operation and high amplification gain can be obtained.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an example of an operational amplifier circuit according to the present invention. The operational amplifier circuit shown in FIG. 1 has a power supply terminal.
A bias circuit is constituted by the current source 40 connected to 44 and the transistors 1 to 3, 10, and 19.

The transistors 4 to 6 form a differential circuit.

The drain of the transistor 5 whose gate is connected to the input terminal 41 is connected to the input of the first cascode circuit including the transistor 9 and the bias circuit and the amplifier circuit including the transistors 7 and 8.

The drain of the transistor 9 is connected to the input of a second cascode circuit having a transistor 18, a bias circuit and an amplifier circuit composed of the transistors 11 and 14.

The drain of the transistor 6 whose gate is connected to the input terminal 22 of the differential circuit is connected to the input of the current mirror circuit composed of the transistors 12 and 16.

The drain of the transistor 16 is connected to the input of a third cascode circuit having an amplifier circuit composed of the transistor 17 and the transistors 13 and 15.

The outputs of the second and third cascode circuits are led to the output terminal 23.

In such an operational amplifier circuit, the time constant occurring at the input part of the current mirror circuit included in the signal path of transistor 6 → transistor 12 → transistor 16 → transistor 17 is small because there is one transistor. Further, by forming an inverting amplifier circuit with the transistors 13 and 15 and using it to include the transistor 17 forming the cascode circuit in the feedback system, the input impedance of the cascode circuit is reduced equivalently and the output impedance is reduced. increase.
Therefore, the cascode circuit has a remarkably wide band and a high gain.

Therefore, the signal delay of this signal path is small enough
And the gain is large.

On the other hand, transistor 5 → transistor 9 → transistor
Since the 18 signal paths are composed of two stages of the cascode circuit having the above-mentioned amplifier circuit, the signal delay is also sufficiently small and the gain is large. Therefore, the frequency characteristics of the input / output voltage gain of the entire operational amplifier can be widened, and
It is possible to make the DC gain very large.

FIG. 2 is a circuit diagram showing another example of the operational amplifier circuit according to the present invention. The operational amplifier circuit shown in FIG. 2 includes a current source 40 connected to a power supply terminal 44 and transistors 21 to 23,33,36.
Constitutes a bias circuit.

The transistors 24 to 26 form a differential circuit.

The drain of the transistor 25, whose gate is connected to the input terminal 41, has a current source composed of transistors 27 and 28.
It is connected to the input of the mirror circuit. The drain of the transistor 28 is connected to the input of a first cascode circuit having an amplifier circuit composed of a transistor 35 and transistors 29 and 31.

The drain of the transistor 26 whose gate is connected to the input terminal 42 of the differential circuit is the transistor 34 and the transistor 30.
It is connected to the input of a second cascode circuit having an amplifier circuit constituted by 32 and 32. The outputs of the first and second cascode circuits are led to the output terminal 43.

In such an operational amplifier circuit, the time constant occurring at the input part of the current mirror circuit included in the signal path of transistor 25 → transistor 27 → transistor 28 → transistor 35 is small because there is one transistor. Further, by forming an inverting amplifier circuit with the transistors 29 and 31 and using it to include the transistor 35 forming the cascode circuit in the feedback system, the input impedance of the cascode circuit is equivalently reduced and the output impedance is reduced. increase.
Therefore, the cascode circuit has a remarkably wide band and a high gain. Therefore, the signal delay of this signal path is sufficiently small and the gain is large.

On the other hand, the signal path from the transistor 26 to the transistor 34 is
Since it is composed of one stage of the cascode circuit having the above-mentioned amplifier circuit, the signal delay is also sufficiently small, and
The gain is large. Therefore, the frequency characteristic of the input / output voltage gain of the entire operational amplifier can be broadened, and the DC gain can be greatly increased.

〔The invention's effect〕

As described above, according to the present invention, the input impedance of the built-in current mirror circuit can be lowered, and by using the cascode circuit having the amplifying means, high-speed operation and high amplification gain can be obtained. Have.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of the operational amplifier circuit according to the present invention, FIG. 2 is a circuit diagram showing another example of the operational amplifier circuit according to the present invention, and FIG. 3 is a conventional operational amplifier circuit. It is a circuit diagram which shows an example. 1 to 16,21 to 36,101 to 116 …… Transistor 40 …… Constant current source 41,42 …… Input terminal 43 …… Output terminal 44 …… Power supply terminal

Claims (2)

[Claims] 1. A positive voltage source is connected to a source of a fourth transistor (p-channel), a gate of the fourth transistor is connected to a bias power supply, and a drain of the fourth transistor is connected to a fifth transistor (p-channel) and a fifth transistor (p-channel). A differential circuit formed by connecting the sources of six transistors (p-channel), the gate of the fifth transistor to the first input terminal, and the gate of the sixth transistor to the second input terminal. A positive voltage source connected to the source of the eighth transistor (p-channel), the gate of the eighth transistor connected to the bias power supply, the drain of the eighth transistor connected to the gate of the ninth transistor (n-channel) and the seventh Connect to the drain of the transistor (n-channel), ground the source of the 7th transistor, and connect the source of the 9th transistor to the 7th transistor. A first cascode circuit that is connected to the gate of the transistor and the drain of the tenth transistor (n-channel), the gate of the tenth transistor is connected to the bias power supply, and the source of the tenth transistor is grounded, A positive voltage source is connected to the source of the 14th transistor (p channel), and the drain of the 14th transistor is connected to the gate of the 18th transistor (p channel) and the 11th transistor (n channel).
Channel), the gate of the eleventh transistor is connected to the bias power supply, the source of the eleventh transistor is grounded, and the positive voltage source is connected to the source of the nineteenth transistor (p-channel). The gate of the transistor is connected to the bias power supply, and the drain of the 19th transistor is connected to the
A second cascode circuit composed of the gate of 14 transistors and the source of 18th transistor, and the drain of 18th transistor connected to the output terminal, and the positive voltage source to the 13th transistor (p-channel) , The gate of the 13th transistor is connected to the bias power supply, the drain of the 13th transistor is connected to the gate of the 17th transistor (n-channel) and the drain of the 15th transistor (n-channel), and the 15th transistor , The drain of the 17th transistor is connected to the output terminal, the source of the 17th transistor is connected to the gate of the 15th transistor and the drain of the 16th transistor (n-channel), and the source of the 16th transistor is grounded. And a third cascode circuit composed of The drain of the transistor 9
The drain of the sixth transistor is connected to the source of the transistor, the drain of the sixth transistor is connected to the drain of the twelfth transistor (n-channel), the source of the twelfth transistor is grounded, and the drain of the ninth transistor forming the first cascode circuit is connected to the drain of the ninth transistor. The 16th circuit which is connected to the drain of the 19th transistor which forms the 2nd cascode circuit and which forms the 3rd cascode circuit
An operational amplifier circuit characterized in that the gate of a transistor is connected to the gate of a twelfth transistor, and the gate and drain of the twelfth transistor are connected. 2. A positive voltage source is connected to the source of the 24th transistor (p-channel), the gate of the 24th transistor is connected to the bias power supply, and the drain of the 24th transistor is connected to the
25 transistors (p-channel) and 26th transistor (p-channel) connected to the sources, the 25th transistor gate connected to the first input terminal, the 26th transistor gate connected to the second input terminal And a positive voltage source connected to the source of the 31st transistor (p-channel), the drain of the 31st transistor being the gate of the 35th transistor (p-channel) and the 29th transistor (n
Channel), the gate of the 29th transistor is connected to the bias power supply, the source of the 29th transistor is grounded, and the positive voltage source is connected to the source of the 36th transistor (p-channel). Connected to the bias power supply, and the drain of the 36th transistor to the
A first cascode circuit consisting of the gate of the 31st transistor and the source of the 35th transistor, and the drain of the 35th transistor connected to the output terminal, and the positive voltage source to the 30th transistor (p-channel) , The gate of the 30th transistor is connected to the bias power supply, the drain of the 30th transistor is connected to the gate of the 34th transistor (n channel) and the drain of the 32nd transistor (n channel), The source is grounded, the drain of the 34th transistor is connected to the output terminal, the source of the 34th transistor is connected to the gate of the 32nd transistor and the drain of the 33rd transistor (n-channel), and the source of the 33rd transistor is grounded. The second cascode circuit that is composed of the The drain of Njisuta 27
Connected to the drain of the transistor (n-channel),
The source of the transistor is grounded, the gate of the 27th transistor is connected to the gate of the 28th transistor (n channel), the drain of the 27th transistor is connected to the gate of the 27th transistor, and the drain of the 28th transistor is connected to the first It is characterized in that it is connected to the drain of the 36th transistor forming the cascode circuit, the source of the 28th transistor is grounded, and the drain of the 26th transistor is connected to the source of the 34th transistor forming the second cascode circuit. Operational amplifier circuit.