JPH0744452B2 - Clock reproduction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an error measuring instrument for evaluating a PCM line,
Or, it relates to a jitter measuring device. In particular, the clock used in these measuring instruments is the RZ input to the measuring instruments.
The present invention relates to a clock regenerator circuit (clock regenerator) for extracting from input data of a format (return to zero format).

[Conventional technology]

Since this type of measuring instrument has the purpose of measuring and evaluating PCM line equipment, it must have a larger jitter tolerance than PCM line equipment, and the number of zero continuations in the input signal of the RZ data format is better. It has to be very tolerable.
An injection-locked clock pulse oscillator has already been considered to achieve these objectives (Jitsuko Sho 59-3628).
If the Q of this oscillator is designed to be high, the jitter component of the input signal does not respond faithfully and a signal in which the high frequency component is lost is generated. On the contrary, when the Q of the oscillator is designed to be small, the oscillation frequency changes due to the temperature change, and the jitter component of the oscillator itself (hereinafter referred to as residual jitter) increases. Therefore, there is a drawback that a large residual jitter occurs even when an input signal having a small jitter component is applied.

In addition, other conventional technology (Shown in 1969, the 4th Conference of The 4th Electrical Society of Japan)
In "Oscillator experiments using digital ICs"), a resonator was inserted between the inputs and outputs of two NOR gates or AND gates to oscillate and clock recovery was performed, as shown in FIG. When the damping resistance of this oscillator is reduced, the load Q of the oscillator decreases, so that the resonance frequency of the resonator easily changes with temperature. In this case, the allowable number of zero continuous lines in the RZ data format input signal is reduced. Moreover, when an RZ input signal with a small jitter component is applied, a signal containing residual jitter larger than the jitter of the input signal is output, and the fidelity of jitter measurement is lost. On the other hand, when the damping resistance in this oscillator is increased, the load Q becomes higher, and therefore, the high frequency component of the jitter included in the input signal is lost, and there is a drawback that it does not respond faithfully.

[Problems to be Solved by the Invention]

The following two characteristics can be pointed out when looking at the flow of the prior art of an injection locking type pulse oscillating circuit capable of synchronizing high frequencies up to the microwave frequency. The first is the pulse generating circuit disclosed in Japanese Patent Laid-Open No. 59-224928 and
As in the carrier recovery circuit for the phase variation modulation signal disclosed in Japanese Patent Publication No. 48-41892, the output frequency of the injection-locked oscillator is controlled by the AFC circuit, and the second is Japanese Patent Publication No. 54-38462. The point is that the load Q of the oscillator is lowered in order to obtain a frequency width capable of injection locking, as provided in the injection locking oscillator disclosed in Japanese Patent Publication No.

The invention of the present application also absorbs this technical idea, but in the case of an error measurement for evaluating the quality of the PCM line, or a measuring instrument for the purpose of jitter measurement, the PCM signal transmitted and received by the PCM line device under test is used. When the clock is regenerated, the measured P
A clock pulse regeneration circuit that can tolerate greater jitter than CM line equipment is required. The clock quality is regenerated from the RZ format input signal, and the line quality is error-measured and evaluated. Therefore, we would like to be able to take a large allowable value of the number of zero continuations in the input signal of RZ format. This is the first object of the invention of the present application.

The second problem is to be able to respond to high-speed fluctuations of the input signal. That is, it is desired to faithfully respond to the jitter component of the input signal. For that purpose, it is necessary to realize a clock regenerating circuit which can follow the jitter and can be quickly synchronized, in other words, can be synchronized with one pulse.

The third problem is to solve the second problem by lowering the load Q of the oscillator in the prior art so as not to lose the high frequency component of jitter, and by lowering the Q, temperature fluctuations. To solve the problem of reconciling the disadvantages with the increase.

In the following explanation, the input signal of RZ format will be described.
A technique for converting RZ input data to NRZ data by using a clock of a clock extractor is also described in the latter stage, and it is shown that NRZ data can be created from the clock regenerator of the RZ input signal of the present invention.

[Means for Solving the Problems]

In order to solve the above-mentioned three main problems, the clock recovery circuit of the present invention, first, in addition to the gate that opens and closes the RZ input signal at the entrance, opens (signal passing state) and closes (signal blocking state) the gate. And decided to control. Depending on whether (i) the output of the oscillator is adjusted to a desired frequency by the control circuit, the input signal is set to free running (free running state) or (ii) the input signal is synchronized. Are controlled to (i) closed or (ii) open.

Secondly, the control circuit is provided with a switching means (switch) and a memory, and the memory outputs the clock pulse train signal output from the extractor (the output of the oscillator with the AFC operation including the Lo Co series resonance circuit) and the reference signal. The comparison value (result value after signal processing) is stored, and in particular (i) at the time of starting or resetting, that is, when a start signal is added, the gate circuit is closed and synchronized with the RZ input signal. In the state not to do, let the oscillator run freely, and feed back the comparison value with the reference signal to the frequency varying means of the oscillator,
The frequency is adjusted to a predetermined frequency, and the adjusted comparison value is stored in the memory.

(Ii) The comparison value stored in the memory is added to the frequency changing means of the oscillator, and the gate circuit is opened to synchronize the input signal to recover the clock. At this time, Lo C
The series resonance circuit does not have such a large Q value because it allows the high frequency component of the jitter.

[Action]

The present invention is a circuit that receives an RZ data signal, extracts its clock, and reproduces it, but in order to be able to reproduce a continuous pulse signal that is synchronized even for one pulse input, a gate is provided at the entrance. It was equipped with a circuit, and was specially characterized by gate (open) closing control at startup. Hereinafter, the operation of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention. In the figure, when the activation signal B is introduced into the control circuit, the control circuit sets the control signal C to the level of "0". When the control signal becomes "0", the gate Q1 is closed even if the RZ input data is input, and the level at point A becomes "0". Therefore, the OR gate Q2 is Lo, Co, Ro,
It oscillates at a frequency determined by the delay time of C1 and Q3 and its gain. At this time, the oscillation frequency is not locked to the input bit rate fo, but is free running. This signal is introduced into the counter circuit, counted, and its value is introduced into the control circuit. The control circuit compares the output value of the counter with the input bit rate (input frequency fo) and corrects the value corresponding to the difference, and the digital-analog converter (D / A)
Output to the converter). The voltage converted into analog here is applied to the variable capacitance diode Q3 to bring the oscillation frequency of the OR gate Q2 close to the input bit rate. The above loop forms an automatic frequency control (AFC) loop. This loop is repeatedly corrected several times, and is stopped by the control signal of the control circuit 3 when the input bit rate falls within ± 0.1%, for example. That is, the control signal is "1".
Change to. At this time, the gate Q1 is opened, and the RZ input data is introduced to the point A (signal A) where it is output.

In the control circuit 3 shown in FIG. 1, when the start signal B (“0” level) is introduced into the control circuit, the feedback output loop is completed regardless of whether the determination output signal is true or false, that is, “1” or “0”. It is fixed at "0" level. FI
The signal (d) outputs the value of the memory recorded previously. This signal passes through the D / A converter 4 and controls the oscillation frequency of the clock extractor 1, and the oscillation frequency value is introduced from the clock counter 2 into the control circuit 3. The difference between the oscillation frequency (the output value of the clock counter 2) and the reference clock value fo is obtained and fD is output.
The judgment circuit 3c judges whether it is within 0.1% of fo,
If it is false, the calculation circuit 3b performs the calculation of (kfD + X). Here, k is a frequency change coefficient of the D / A converter 4 and the clock extractor 1, and X is a fixed constant thereof. The output signal of the arithmetic circuit 3b is written into the memory as soon as the arithmetic operation is completed, and is output as the FI signal. The difference between the output value of the clock counter 2 and the reference clock value fo is calculated by the subtraction circuit 3a, and if the value fD is within 0.1% of fo (judgment output is true), the above operation is not performed and the value is stored in the memory. The switch 3e is switched so as to output the stored value. That is, the switch 3e is controlled by a circuit including the AND circuits 3f and 3g and the inverter 5. Further, the control signal C is changed to "1" level.

〔Example〕

 Details of the embodiment will be described with reference to FIGS.

FIG. 2 is a diagram in which the way of taking blocks is changed while keeping the configuration of FIG. 1 as it is. Therefore, the operation of FIG. 2 is the same as the operation of FIG.

In FIG. 2, the dotted line shows the flow of control signals, and the solid line shows the flow of signals.

According to the configuration of FIG. 1, the present invention provides a gate circuit 11 for passing or blocking an RZ digital data signal by a control signal, and an oscillation for oscillating a clock pulse train signal in response to the RZ digital data signal passing through the gate circuit. A clock extractor 1 including a circuit and a frequency varying means Q3 for changing the oscillation frequency of the oscillation circuit, a clock pulse train signal from the clock extractor and a reference signal, and comparing both signals to obtain a signal of the difference. It comprises a comparator 13 for outputting, a control circuit 3 having a switching means 12 and a memory 3d for storing the output of the comparator.

Further, in summary, the basic operation of the control circuit 3 is summarized as follows: (a) A control signal for opening the gate circuit while sending a signal stored in the memory to the frequency varying means through the switching means. B) When receiving a start signal, the latest value of the comparator is stored in the memory, and the output of the comparator is fed back to the frequency changing means, and the gate circuit is also supplied. It is designed to send a control signal to close the.

FIGS. 3 to 5 are waveform diagrams showing a state in which the RZ input data and the oscillator of the clock extractor are operating at different times in the block diagram of FIG. For convenience of explanation, the gate Q1 and
Let us assume that the delay time of Q2 is zero and that the bit rate of the RZ input data and the frequency of the oscillator of the clock extractor match first.

First, FIG. 3 shows the case where the phase B of the oscillator of the clock extractor and the phase A of the RZ input data match (same phase). In this case the oscillator phase B is not affected by the RZ input data A at all.

In FIG. 4, even when the phase B of the oscillator of the clock regenerator is delayed from the phase A of the RZ input data by Δt, the rising edge of the output pulse C coincides with the falling edge of the pulse A.

In FIG. 5, even when the phase B of the oscillator of the clock regenerator leads the phase A of the RZ input data by Δt, the trailing edge of the pulse A coincides with the trailing edge of the output pulse C.

Thus, in all cases the oscillator is resynchronized with one input pulse. Therefore, when the RZ input data contains a jitter, the oscillator is synchronized each time following the jitter.

Next, regarding the RZ-NRZ converter that converts RZ input data to NRZ (non-return zero) data using the clock of the clock extractor when the bit rate of the RZ input data and the frequency of the oscillator of the clock extractor differ Consider. FIG. 6 shows that the RZ input data including 9 consecutive zeros is introduced to the D input of the D-type flip-flop, and the clock of (10 / 9.5) times and the clock of (10 / 10.5) times of the bit rate are input. It is a timing waveform of NRZ data output when introduced into the C input of the flip-flop. In this case, the set-up time and the hold time of the D-type flip-flop are set to zero (ideal state) for the sake of simplifying the description. At any clock frequency, the RZ data is faithfully converted to NRZ. RZ
NRZ faithfully when the oscillation frequency is higher than the data
The limit value for obtaining data is calculated by the following formula.

However, fo: Reference clock (same as input bit rate) f1: Oscillation frequency N: Number of continuous zeros of RZ input data Next, faithfully when the oscillation frequency is lower than RZ data
The limit value for obtaining NRZ data is calculated by the following formula.

From equations (1) and (2), the limit value for obtaining the NRZ data faithfully when the oscillation frequency is different from the RZ data is equation (3).

The following equation can be expressed by the ratio δ of the difference between the input bit rate fo of the RZ data fo and the oscillation frequency f1.

Equation (5) is obtained from equations (3) and (4).

When the difference between fo and f1 is small, f1 / fo can be regarded as 1.0, and equation (6) is obtained.

For example, to faithfully convert RZ data including 120 zeros into NRZ, δ = 0.41%.

FIG. 7 is a diagram showing the phases of the reference clock and the recovered clock at a frequency higher than the RZ input bit rate when the frequencies of the RZ input data bit and the clock extractor are different.

In the case of zero continuous RZ data, the phase change increases as the number of zero continuous phases increases by one. Jitter is generally UI
Using the unit of (Unit Interval), the phase change for 1 clock corresponds to 1 UI. The jitter J at zero continuity is expressed by equation (7).

J = N (1-fo / f1) UI (7) For example, when N = 3 and J ≦ 0.005, (fo / f1) ≧ 0.99833 and (f1 / fo) ≦ 1.00167, and f1 is compared with fo. If it changes by 0.167%, it will be allowed.

〔The invention's effect〕

According to the present invention, a clock extractor for extracting a clock pulse from RZ digital data is provided, and a gate is provided at this input to control the opening and closing of the gate. ) State, the comparator output at that time is stored in the memory, the switching means is then switched to the memory side, the gate is opened at the same time, and the clock recovery circuit is operated by the signal stored in the memory. I was allowed to. That is, since the clock extractor is included in the feedback mechanism to control whether the output of the comparator is used directly as the feedback signal to the clock extractor or the stored one is stored, (i) the AFC loop Since the oscillating frequency of the clock extractor was made to approach the input bit rate by using, the number of zero consecutive RZ data could be increased and the residual jitter of the circuit could be reduced.

(Ii) Even if the load Q of the resonance circuit was lowered, the high frequency component of the jitter contained in the RZ input data was not lost, and a clock signal with high fidelity could be obtained. In other words, we were able to realize a clock pulse regeneration circuit that can tolerate greater jitter than the PCM circuit under test.

(Iii) A circuit that can also obtain an NRZ data signal by regenerating a clock from an RZ data signal has been realized.

As described above, the effect of the present invention is very large.

[Brief description of drawings]

1 and 2 are diagrams showing an embodiment of the present invention, and FIGS. 3 to 7 are timing charts for explaining the operation of the present invention. FIG. 3 is a timing chart in the case of the same phase. FIG. 4 is a timing chart when the phase is delayed by Δt, and FIG. 5 is a timing chart when the phase is advanced by Δt. FIGS. 6 and 7 ( FIGS. 8A and 8B are diagrams showing a time chart of NRZ data, and FIG. 8 is a diagram showing a conventional technique. In the figure, 1 is a clock extractor, 2 is a clock counter, and 3
Is a control circuit, 4 is a digital-analog converter, 6 is an input terminal, 7 is an output terminal, 8 is a D-type flip-flop for converting RZ data into NRZ data, 9 is an NRZ data output terminal, and 11 is a gate circuit. , 12 is switching means, 13 is a comparator,
30 is a control means, Q1 is a gate circuit, Q2 is an OR gate, Q3 is a frequency variable means (variable capacitance diode), Ro and R2 are resistors, a is RZ input data, b is a start signal, c is a control signal,
D is the FI signal, C, C0 and C1 are capacitors, and L and Lo are coils.

Claims (1)

[Claims] 1. A gate circuit (11) for passing or blocking an input RZ digital data signal by a control signal, an oscillating circuit for receiving a RZ digital data signal passing through the gate circuit and oscillating a clock pulse train signal, and A clock extractor (1) including a frequency changing means (Q3) for changing the oscillation frequency of the oscillator circuit, and a clock pulse train signal from the clock extractor, which is set to a difference frequency between the frequency and a reference constant frequency. Comparator (1 that outputs a corresponding signal
3) having switching means (12) for forming a path of a feedback signal to the gate circuit and the frequency varying means, and a memory (3d) for storing the output of the comparator; To generate a control signal for closing the gate circuit and a control signal for forming a feedback loop from the comparator toward the clock extractor to the switching means, and (b) opening the gate circuit. A control means (30) having means for generating a control signal and a control signal for releasing the formation of the feedback loop and sending the signal stored in the memory to the frequency varying means. Clock recovery circuit.