JPH0744526B2 - Signal synchronization method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal synchronization method, and in particular, by using a data transmission line connecting two points separated from each other, for example, a numerical value such as a transmission line current value is simultaneously measured. The present invention relates to a signal synchronization method of sampling signals for measurement.

[Prior Art] In recent years, adoption of a digital current operated relay device as a transmission line protection relay has been progressing. In this digital current-actuated relay, the current information of both terminals of the power transmission line is converted into a digital value, which is transmitted through a digital transmission line such as a microwave or an optical fiber, and a protective operation is performed by differential calculation. ing. Therefore, it is necessary to simultaneously generate sampling signals at both terminals separated from each other. However, since there is a transmission delay time in the transmission line, the sampling signal cannot be synchronized by the conventional data transmission technique.

A method for solving this problem is shown in FIGS. 4 (a) and 4 (b).
A synchronization method such as that shown in Japanese Patent Publication No. 59-5 has been proposed.
No. 1209). That is, data of specific sampling numbers from the master station and the slave stations connected by the opposite transmission path, respectively.
Dm and Ds are mutually transmitted in a cycle T, and this cycle T is set so that T> 2τ with respect to the transmission delay time τ between both stations. Further, tm is the time required from the master station transmitting data Dm to receiving data Ds, and ts is the time required from the slave station transmitting data Ds to receiving data Dm.
Advance or delay the transmission of data Ds in the slave station so that tm = ts. However, as shown in Fig. 4 (b), tm
When + ts> T, the transmission timing of the slave station is first changed so that the difference between tm and ts becomes large, and tm + ts <T as shown in FIG.

As described above, the sampling can be synchronized.

[Problems to be Solved by the Invention] That is, in this synchronization method, sampling is performed by advancing or delaying the transmission timing on the slave station side based on the result of the comparison of the required time data tm and ts obtained at each cycle T. Is intended to be synchronized. Therefore, the difference Δf between the transmission timing signal frequency fm of the master station and the transmission timing signal frequency fs of the slave station causes a deviation δT = TΔf / f between the transmission timings of both stations during the period T (where f = (fm + fs ) / 2) is a prerequisite that is small enough to be ignored. If this deviation δT is large,
It is necessary to increase the timing control amount tc for each cycle T. As a result, the control becomes rough and the synchronization error increases.

For example, when the cycle T = 20 ms, the deviation | δT | = 0.8 μs at | Δf = f | = 2 × 10 ⁻⁵ , which means that the above method cannot maintain synchronization or a synchronization error of about ± 5 μs. Is always generated, so a stability of | Δf / f | ≦ 2 × 10 ⁻⁶ is required.

For this reason, a highly accurate and highly stable clock generation circuit is required in order to perform highly accurate synchronization by the above-mentioned synchronization method.

However, in order to realize such a clock generation circuit, it is necessary to keep the circuit temperature constant by using a constant temperature bath or the like in addition to the precise adjustment of the circuit, which leads to an increase in size of the device and a decrease in reliability. , And increased prices and other problems.

Thus, an object of the present invention is to solve the above-mentioned problems of the prior art and to provide a signal synchronization method capable of performing highly accurate synchronization without using a highly accurate and highly stable clock generation circuit. is there.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the signal synchronization signal of the present invention has a transmission delay time of τ between two transmitting / receiving devices connected by a data transmission path. In this case, the data of the same transmission format to which the repeated sampling number is added with the cycle T larger than 2τ are transmitted to each other, and the respective devices transmit the data Dm or Ds of the specific sampling number of the own device to the specific sampling from the partner device. Measures the time tm or ts until the reception of the number data Ds or Dm.
tm is transmitted after being multiplexed with other data, and on the other hand, the device that is the slave station for synchronization determines the transmission timing control amount using time tm, ts, and advances or delays the transmission timing based on this transmission timing control amount. Thus, in the signal synchronization method in which the sampling synchronization signal is generated in synchronization with the sampling synchronization signal of the device serving as the master station, the device serving as the slave station is connected to the clock generation circuit that outputs a clock pulse and the clock generation circuit. In addition to inputting clock pulses from the clock generation circuit, input a number of control pulse signals corresponding to the transmission timing control amount and a control direction instruction signal for instructing the advance or delay direction, and generate the clock pulses based on these signals. With a pulse sampling insertion circuit that extracts or inserts and outputs as a clock signal , And a fixed frequency divider connected to the pulse sampling / insertion circuit to divide the clock signal and output the transmission timing signal, and connected to this fixed frequency divider to transmit the transmission data Ds by the transmission timing signal to the main station side. Together with a data transmission circuit that outputs a transmission synchronization signal and a control timing signal of a predetermined cycle, and receives the reception data Dm transmitted from the main station and outputs the reception synchronization signal and the required time tm extracted from the reception data Dm. Time required between the data reception circuit and the transmission synchronization signal and the reception synchronization signal output from the data transmission circuit and the data reception circuit, respectively.
It is connected to the clock circuit that measures ts by the clock signal and the data receiving circuit and the clock circuit.
Synchronous control circuit that determines the optimal transmission timing control amount from the data of, and is connected to this synchronous control circuit and also to the data transmission circuit. When the control timing signal is input from the data transmission circuit, it corresponds to the transmission timing control amount. It consists of a lead-lag control circuit that outputs the control pulse signal of the specified number and the control direction instruction signal that indicates the control direction to the pulse sampling insertion circuit, and the past number of the transmission timing control amount and the time difference tm-ts. It is necessary to estimate the relative deviation between the transmission timing frequencies of the master and slave stations and the time difference tm-ts after performing the transmission timing control from the known data for each batch, and then determine the transmission timing control amount from these estimated values. It is a characteristic signal synchronization method.

[Operation] With such a configuration, the relative deviation Δf / f (however, Δ
Even if f = fm-fs, f = (fm + fs) / 2) is not made small, it is possible to determine and synchronize the transmission timing control amount of the slave station so that the next required time tm and ts are made equal. Therefore, a highly accurate and highly stable clock generation circuit becomes unnecessary.

EXAMPLES Examples of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a slave station in a signal synchronization system according to an embodiment of the present invention. In the figure, 1 is a clock signal with a period σ
A clock generation circuit that outputs MCK. A control pulse signal CL and a control direction (advance or delay) instruction signal FO are input to the clock generation circuit 1, and clock pulses of the clock signal MCK are extracted based on these signals. Alternatively, a pulse extracting / inserting circuit 2 for inserting and outputting as a clock signal CK is connected. Further, the pulse sampling / inserting circuit 2 divides the clock signal CK into a transmission timing signal TC.
Is connected to a fixed frequency divider 3 which outputs the fixed frequency divider 3
Further, a data transmission circuit 4 for transmitting the transmission data Ds to the main station side by the transmission timing signal TC and outputting the transmission synchronization signal TS and the control timing signal CT of a predetermined cycle T is connected.

In addition, 5 is the required time tm for receiving the reception data Dm transmitted from the main station and extracting it from the reception synchronization signal RS and the reception data Dm.
Is a data receiving circuit for outputting, and 6 is a clock for measuring a required time ts between the transmission synchronizing signal TS and the receiving synchronizing signal RS output from the data transmitting circuit 4 and the data receiving circuit 5 by the clock signal MCK. Circuit. And
The data receiving circuit 5 and the time counting circuit 6 have a past required time tm.
And ts data for the next optimum transmission timing control amount
A synchronous control circuit 7 for determining tc is connected to the synchronous control circuit 7 from the data transmission circuit 4 to the control timing signal CT.
Is input, a lead / lag control circuit 8 is connected which outputs to the pulse sampling / inserting circuit 2 the control pulse signals CL of the number corresponding to the transmission timing control amount tc and the control direction instruction signal FO for instructing the control direction.

Next, the operation of this embodiment will be described.

First, when the transmission data Ds is transmitted from the data transmission circuit 4, the transmission synchronization signal TS is output from here, and when the reception data Dm is received by the data reception circuit 5, the reception synchronization signal RS is output from here to the timing circuit 6. To be done. And the timing circuit 6
At time ts between transmission sync signal TS and reception sync signal RS
Is measured, and the required time ts and the required time tm from the data receiving circuit 5 are input to and stored in the synchronization control circuit 7.

In the synchronous control circuit 7, the optimum transmission timing control amount tc for the next time is determined from the required times tm and ts for the past several times, and the lead / lag control circuit 8 further controls the control pulse signal CL and the control direction corresponding to the transmission timing control amount tc. The instruction signal FO is output, and the pulse extracting / inserting circuit 2 extracts or inserts the pulse of the clock signal MCK based on these signals.

The clock signal CK obtained in this way is used by the fixed frequency divider 3
The frequency is divided by and input to the data transmission circuit 4 as the transmission timing signal TC, from which the transmission data Ds is transmitted based on the transmission timing signal TC. As a result, the sampling is synchronized.

Here, a method of determining the transmission timing control amount tc in the synchronous control circuit 7 will be described with reference to the timing chart of FIG.

In the figure, t _mi and t _si (i is an integer) are periods iT ≦ t <
It represents the measured values of the required time tm and ts at (i + 1) T, and the transmission timing control amount t _ci in this period is t _ci = Ki · σ (Ki is a control value) by using the cycle σ of the clock signal MCK. Will be represented. Now, let us consider determining the optimum control value K ₀ for the next time (time t = T) at time t = ₀ . That is, the past control values K _-1 , K _-2 , K _-3 ... and the required time t _s-1 , t _s-2 , t _s-3 ... are known, and the required time t _mi from the master station. Due to the transmission delay of t _m-3 , t
_m-4 , t _m-5 ... Are known.

By the way, during the period T, the relative deviation Δf / f between the transmission timing frequencies fm and fs between the master and slave stations (where Δf = fm-fs,
The time difference t _mi -t _si is 2δT = 2 due to f = (fm + fs) / 2)
Increases by T · Δf / f. On the other hand, the transmission timing of the slave station
The time difference t _mi -t _si decreases by −2 Ki σ when advanced by Ki σ. Here, the coefficient 2 is based on the fact that the same amount increases and decreases between the required times tm and ts. Therefore, t _{mi + 1} -t _{si + 1} = t _mi -t _si + 2δT-2Kiσ (1) holds. Therefore, if δT is known, the above (1)
Unknown time difference t _m-2 -t _s-2 , t _m-1 -t _s-1 , t _mo -t
_so can be estimated.

Further, δT is an equation using the known time difference t _mi −t _si and the control value Ki. Can be estimated by However, n is a positive integer and indicates the number of samples.

From these equations (1) and (2), the optimum control value K ₀ such that t _mi = t _si is determined as follows.

Since t _mi and t _si include a measurement error of −σ or 0, an error also occurs in the estimated values of δT and (t _mo −t _so ). To suppress this error, for example, The number of samples n in the equation (2) should be large.

Further, in FIGS. 3 (a) and 3 (b), T / σ = 86400, Δf / f =
The result of the simulation using the above method in the case of 2 × 10 ⁻⁵ is shown. Figure 3 (a) shows ((t _mi -t _si ).
3 / (b), the determined control value Ki is shown in FIG. 3 (b), and the measurement error is also taken into consideration. As can be seen from this result, the control value Ki is determined with extremely high accuracy.

The control value Ki determined in this way is multiplied by the period σ to obtain the transmission timing control amount t _ci , and the next data transmission is performed based on this transmission timing control amount t _ci .

[Effects of the Invention] As described above, according to the signal synchronization system of the present invention, the following excellent effects are exhibited.

That is, highly accurate synchronization can be performed without using a highly accurate and highly stable clock generation circuit. Therefore,
Since it is not necessary to stabilize the temperature of the clock generation circuit by using a thermostatic chamber or the like, miniaturization of the transmission system, improvement of reliability, improvement of maintainability, cost reduction, etc. are achieved.

[Brief description of drawings]

FIG. 1 is a block diagram of a slave station in a signal synchronization system according to an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the embodiment, and FIGS. 3 (a) and 3 (b) are transmission timings according to the embodiment. Graphs showing the results of simulations using the control amount determination method, and FIGS. 4A and 4B are explanatory views showing a conventional synchronization method. In the figure, 1 is a clock generation circuit, 2 is a pulse extracting / inserting circuit, 3 is a fixed frequency divider, 4 is a data transmitting circuit, 5 is a data receiving circuit, 6 is a clock circuit, 7 is a synchronous control circuit, 8 is a lead / lag. It is a control circuit.

Claims (1)

[Claims] 1. When the transmission delay time between two transmission / reception devices connected by a data transmission path is τ,
Data of the same transmission format added with a sampling number repeated at a cycle T larger than 2τ are transmitted to each other, and in each of the above devices, data of a specific sampling number of its own device Dm or Ds to data of a specific sampling number from a partner device are transmitted. The time tm or ts until the reception of Ds or Dm is measured, and in the device which is the main station for synchronization, the time tm is multiplexed with other data and transmitted,
On the other hand, regarding the synchronization, the slave station device determines the transmission timing control amount by using the time tm and ts, and advances or delays the transmission timing based on this transmission timing control amount, thereby sampling sampling signal of the master station device. In the signal synchronization system that generates the sampling synchronization signal in synchronization with the clock generation circuit, the slave station device receives the clock pulse from the clock generation circuit connected to the clock generation circuit and the clock generation circuit and outputs the clock pulse. The number of control pulse signals corresponding to the timing control amount and the control direction instruction signal for instructing the advance or delay direction are input, and the clock pulse is extracted or inserted based on these signals and output as the clock signal. Connect to the sampling / insertion circuit and the pulse sampling / insertion circuit. A fixed frequency divider that divides the clock signal to output the transmission timing signal, and transmits the transmission data Ds to the main station side by the transmission timing signal that is connected to this fixed frequency divider and also transmits the transmission synchronization signal of a predetermined cycle. And a data transmission circuit for outputting a control timing signal, a data reception circuit for receiving the reception data Dm transmitted from the main station and outputting a reception synchronization signal and a required time tm extracted from the reception data Dm, and a data transmission The clock circuit connected to the circuit and the data reception circuit, which measures the required time ts between the output synchronization signal and the reception synchronization signal output by the clock signal, and the past required time tm connected to the data reception circuit and the timing circuit. , And a synchronization control circuit that determines the optimum transmission timing control amount from the data of ts, and is connected to this synchronization control circuit and also to the data transmission circuit. When the control timing signal is input from the data transmission circuit, it consists of a number of control pulse signals corresponding to the transmission timing control amount and a lead-lag control circuit that outputs a control direction instruction signal that indicates the direction of control to the pulse sampling insertion circuit. Cage,
Estimate the relative deviation of the transmission timing frequency of the master station and the slave station and the time difference tm-ts after performing the transmission timing control from the past several times of known data of the transmission timing control amount and the time difference tm-ts, and A signal synchronization method characterized in that the transmission timing control amount is determined from these estimated values.