JPH0744527B2 - Bit synchronization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit, that is, a circuit for facilitating the diagnosis of a failure of a bit synchronization circuit which correctly receives a signal having phase jitter in a synchronous digital communication system.

[Background of the Invention]

The bit synchronization circuit absorbs jitter due to variations in delay time due to fluctuations in electrical characteristics of the transmission line (temperature, power supply, noise, etc.) in switching networks and computer-to-computer communications that transmit and receive at the same frequency, and correct the received waveform. It controls the uptake. For such a circuit, a multi-phase clock is prepared on the receiving side as described in Japanese Patent Application No. 57-173219.
By detecting the correlation between the change point of the input data and the phase of the above clock, and controlling the clock selection so that the clock with the farthest phase from the change point becomes the latch clock of the input data, the jitter is absorbed. I have to.

However, as circuits for communication are being integrated on a large scale, such a circuit in which the clock is automatically selected is realized in the integrated circuit for failure inspection during manufacturing or usually. In order to prevent malfunctions due to noise that may occur during operation of the device, it is necessary to directly access it from the outside. There is a drawback that it takes man-hours.

[Object of the Invention]

An object of the present invention is to provide a bit synchronization circuit that can prevent loss of synchronization due to malfunction of the clock selection circuit due to noise or the like.

Another object of the present invention is to provide a bit synchronization circuit that enables a test operation or state monitoring by a control signal from an external device.

[Outline of Invention]

In order to achieve the above object, in the present invention, a means for comparing the phases of an input digital signal having a constant frequency and an input latch signal, and outputting a detection signal indicating that synchronization is lost, and the detection signal A bit synchronizing circuit comprising a counter means for counting operation and a selecting means for selecting one of a plurality of multiphase clocks according to the count value of the counter means and outputting it as the input latch signal. In the above, there is provided means for inhibiting the counting operation of the counter means in response to a control signal from an external device such as a processor.

Another feature of the bit synchronization circuit of the present invention is a means for reading the detection signal and the count value of the counter means to an external device in response to a control signal from the external device, or the counter means from the external device. And a means for performing a test operation according to the control signal.

Example of Invention

 Hereinafter, examples of the present invention will be described in detail.

FIG. 1 shows the configuration of an embodiment of a bit synchronizing circuit according to the present invention. In the figure, 301 and 302 are inverters for shaping the waveform of the input signal, 303 is an edge trigger type flip-prop, 304 and 305 are delay elements for detecting the edge of the input waveform and exclusive (exclusive) NOR, 306, 311 are NOR, 307, 309.
Is an inverter, 308 is an SR flip-flop, 310, 314 are 4-input multiplexers, 320 is a decoder, 313, 315, 317, 32
2,327,328,330,333 is NAND, 316,321,325,335 is AND, 318,
326,329,334 is an inverter, 312 is a through latch, 319,324,
332 is an edge trigger type flip-flop that constitutes a counter, 336 to 340 are tri-state gates that become high impedance when the control signal is 0, data bus DB is a bidirectional bus connected to an external processor, and SEL is externally bit-synchronized. A control signal for selecting a circuit, R / W is a signal for specifying writing / reading to a register, and TEST is a signal directly selected from the outside for inspection.

FIG. 2 shows the relationship between the state of the decoding circuit 320 in FIG. 1 and the clock selected by the multiplexers 310 and 314 at this time.

FIG. 3 shows the meaning of the bits when writing / reading each bit of the data bias DB of FIG.

FIG. 4 shows the phase relationship of each clock of φ _{0 to} φ ₃ in FIG.

An embodiment will be described below with reference to the above-mentioned drawings. First, the following conditions are set in order to explain the operation in the normal state. In the state where φ ₀ is selected as the input data latch clock and the normal operation is performed, the Q outputs of 319, 324 and 332 are all 0, and in the decoder 320, U0 is '1' and the others are "0". At this time, the φ ₀ signal is output at 310 and the φ ₂ signal is output at 314.

In addition, the clock is automatically selected when out of sync.
Q output of 312 is set to "1".

When the change point of the input signal to 301 is at a timing other than φ ₀ , the output of 309 is “1”, and even if a pulse corresponding to the change point is output from 305, 306 is masked and its output remains “0”. Flip Flop does not change. Follow 313
Since the output of does not change, 319 also retains its original state.
When the change point of the input of 302 enters between "1" of the φ ₀ clock while operating in such a state, 303 is latched at the trailing edge of φ ₀ , and the phase margin is reduced. Therefore, in such a case, another clock needs to be selected. In the above case, when a pulse is output to 305, φ ₀ is “1”, so the output of 309 is “0” and the change of 305 is transmitted to 307. As a result of this change 308 is set,
As a result, 313 changes from "0" to "1". (However, TEST is always set to "1" at this time.) The output of 313 is input to the clock terminal of 319, and the reverse polarity of the Q output of 319 is input to the D terminal when the Q of 312 is "1". Therefore, it is reversed according to the rise of the clock. 308 is reset by the next clock (here φ ₂ ) to the selected clock to cope with the next change. In this circuit, 319 is used to remove the loss of synchronization once so that the loss of synchronization is not immediately caused by the instantaneous disturbance of data due to noise or the like.

If there is a change in the data when φ ₀ is '1' after 319 has changed, 308 is reset again, which causes the counter clock to rise again, and as a result the Q output of 324 changes to "1". Then, the output U1 of the decoder 320 becomes "1", and 3
The output of 10 changes from φ ₀ to φ ₁ , and the output of 314 changes from φ ₂ to φ ₄ .

In this way, when the phases of the selected clock and the data change point are close to each other, the selected clock is switched in the direction in which the phase margin can be secured as described above.

The above is the operation of the bit synchronization circuit, and basically, the function can be realized if only such a circuit is provided. However, when this circuit is built into an integrated circuit,
Since it is difficult to observe the defective state of this circuit from the outside because the internal state at the time of initial setting cannot be confirmed and it cannot be set to an arbitrary state, the inspection cost becomes large and the meaning of built-in is diminished. For this reason, as shown in FIG. 1, a function is added around the basic circuit to enable access from the outside. This function will be described below.

When SEL is “1” and R / W is “0”, 316 becomes “1”, and at this time, external write is performed. 308 is reset when 316 is "1". The function of each bit is shown below. When b ⁰ is “1”, 319 is reset. When it is “0”, there is no change. b ¹ and b ² are the setting information for 324 and 332, respectively, when b ⁴ is '1', it is the setting information for 324,332, and when b ⁴ is '1', it is 32.
Written to 4,323. When b ⁴ is “0”, the original states of 324 and 332 are maintained. In this writing, 321 becomes 1 and 322,3
This is performed by setting Q to "1" when the terminal is "0" and setting "0" when the terminal is "0" via each NAND of 27,328,333. b ³ controls the count prohibition of the counter 31
When Q of 2 is set to "1", the counter is free-run. When "0", the change of 319 is transmitted to 324 through 317,318,323. To stop the reverse of the 324. These are the third
Shown in the figure.

The internal status can be read when SEL is “1” and R / W is “1”.
Is set to "1", the 336 to 340 tri-state gates are output, and the outputs of the flip-flops 319, 324, 332, and 312, and the clock signal 325 of the counter are output to the DataBus.

To check the function of the counter, use the Test signal to directly apply this signal to the clock terminal (output of 313) of the counter so that the function can be confirmed regardless of the change point of the input data. In, the state of the count-up of the counter is output to DataBus so that it can be directly observed from the outside.

〔The invention's effect〕

According to the present invention, the bit synchronous circuit is provided with a counter operation prohibiting means. Therefore, for example, when the optimum clock is in a selected state, it is possible to prohibit automatic clock selection by external control. As a result, it is possible to prevent erroneous switching of the input latch clock due to noise or the like and maintain the normal operation of the receiving circuit. When a test operation function or monitor function is provided by external control, an arbitrary state can be set by directly controlling from outside without changing the phase of the change point of the input waveform, and its internal state can be directly set. By reading the data, it is possible to reduce the test pattern of the inspection at the time of manufacturing and online monitor at the time of normal operation, so that the reliability of the circuit can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a bit synchronizing circuit according to the present invention, FIG. 2 is a logic diagram of the output of the decoder and multiplexer in FIG. 1, and FIG. 3 is a bit of the process signature interface of FIG. FIG. 4 is a timing diagram of the 4-phase clock used in FIG. 301,302,307,309,318,326,329,334 …… Inverter, 30
6,311 …… NOR gate, 313,315,317,322,327,328,330,33
3 …… NAND gate, 316,321,325,335 …… AND gate, 30
3,319,324,332 …… edge trigger flip-flop circuit, 308 …… SR flip-flop circuit, 312 …… through latch circuit, 320 …… decoder circuit, 310,314 …… multiplexer circuit, 323 …… exclusive OR gate, 30
5,331 …… Exclusive NOR gate, 304 …… Delay circuit, 336,337,338,339,340 …… Tri-state gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Asano Inventor Kenichi Asano 1448, Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi Ultra EPS Engineering Co., Ltd. (56) Reference JP-A-59-63835 (JP, 59-63835) A) JP-A-54-124915 (JP, A) JP-A-59-215148 (JP, A) JP-A-56-42825 (JP, A) JP-A-51-71766 (JP, A)

Claims (2)

[Claims] 1. A constant frequency input digital signal (HWIN)
In the bit period circuit for automatically selecting a clock having a phase synchronized with the digital signal from the multi-phase clocks (φ _{0 to} φ ₃ ) having the same frequency as Means (306 to 308, 313) for comparing the phases of the latch signal and the input digital signal and outputting a detection signal indicating that synchronization has been lost, and a counter means for counting the detection signal ( 319, 324, 332) and selection means for selecting one of a plurality of multiphase clocks (φ _{0 to} φ ₃ ) according to the count value of the counter means and outputting it as the input latch signal. (320, 310)
A means (312) for inhibiting the counting operation of the counter means for an arbitrary period according to a control signal (b ³ ) from an external device, and a control signal (b ⁰ , b ¹ , b from the external device. ² , b ⁴ ) according to
A bit synchronization circuit comprising means (315, 316, 321, 322, 326 to 329, 333) for changing the count value of the counting means to a desired value. 2. The bit synchronization circuit according to claim 1,
Further, means (DB, R / W, 335 to 34 for reading the detection signal and the count value of the counter means to an external device.
0) is provided.